JPS6386566A - Gate turn-off thyristor device - Google Patents
Gate turn-off thyristor deviceInfo
- Publication number
- JPS6386566A JPS6386566A JP23176986A JP23176986A JPS6386566A JP S6386566 A JPS6386566 A JP S6386566A JP 23176986 A JP23176986 A JP 23176986A JP 23176986 A JP23176986 A JP 23176986A JP S6386566 A JPS6386566 A JP S6386566A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- base layer
- gate electrode
- anode
- emitter layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015556 catabolic process Effects 0.000 claims abstract description 8
- 238000002347 injection Methods 0.000 abstract description 8
- 239000007924 injection Substances 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 241000125205 Anethum Species 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 206010021033 Hypomenorrhoea Diseases 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/72—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region
- H03K17/73—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region for dc voltages or currents
- H03K17/732—Measures for enabling turn-off
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0036—Means reducing energy consumption
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、Ｐベース層とＮベース層の双方にゲート電極
を設けた、ダブルゲート構造のゲートターンオフサイリ
スタ（ＧＴＯ）装置に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a gate turn-off thyristor (GTO) device with a double gate structure in which gate electrodes are provided on both the P base layer and the N base layer. Regarding.
（従来の技術） 第３図は通常のＧＴＯ装置の回路構成を示ず。(Conventional technology) FIG. 3 does not show the circuit configuration of a normal GTO device.
ＧＴＯ素子２１のＰベース層にゲート電極が設けられ、
ここにオンゲート電源及びオフゲート電源がそれぞれス
イッチを介して接続される。２２は負荷であり、２３＆
ま主電源である。A gate electrode is provided on the P base layer of the GTO element 21,
An on-gate power supply and an off-gate power supply are connected here via switches, respectively. 22 is the load, 23&
Well, it's the main power supply.
第４図はこのＧＴＯ素子の動作波形である。時刻ｔｌで
オンゲート回路のスイッチ素子が開しると、オンゲート
電源によりゲート電流ｌａが第３図に示す方向に流れ、
ＧＴＯ素子２１はターンオンする。時刻ｔ２以前にオン
ゲート回路のスイッチ素子を間き、時刻ｔ２でオフゲー
ト回路のスイッチ素子をオンにすると、オフゲート電源
によりゲート電＠ Ｉ ｏがターンオンの場合と逆の方
向に流れ、電流の吸い出しが行われる。このときアノー
ド電流ＩＡの減少が始まるまでの時間（１：＋ −ｔ２
）は蓄積時間であり、このｌ１１１間ＧＴＯ素子内部で
は導通領域が次第に狭くなっていく。時刻ｔ３からアノ
ード電流ＩＡが減少し始め、同時にアノード電圧ＶＡが
増加し始める、１７ノード電流ＩＡは時刻ｔ４までに急
激に減少する。この時間（ｔ４−ｔｓ）を降下時間とい
う。時刻ｔ４のアノード電流の値をディル電流初期値と
呼び、これ以降時刻ｔ５まで流れている電流をティルミ
流と呼び、この時間（ｔｓ −ｔ４ ）をテイル明間と
いう。ティルミ流はＮベース層中の残留電荷が排出され
るために生じる電流である。以上の動作中に生じる電力
損失Ｐ （＝ＶＡＸ ＩＡ）は第４図最下段に示す波形
となる。FIG. 4 shows the operating waveforms of this GTO element. When the switch element of the on-gate circuit opens at time tl, the gate current la flows in the direction shown in FIG. 3 due to the on-gate power supply.
The GTO element 21 is turned on. When the switch element of the on-gate circuit is turned on before time t2 and the switch element of the off-gate circuit is turned on at time t2, the gate current @ I o flows in the opposite direction to that when it is turned on due to the off-gate power supply, and the current is sucked out. be exposed. At this time, the time until the anode current IA starts to decrease (1: + -t2
) is the accumulation time, and the conduction region inside the GTO element gradually becomes narrower during this period of 1111. From time t3, the anode current IA begins to decrease and at the same time, the anode voltage VA begins to increase.17 The node current IA rapidly decreases by time t4. This time (t4-ts) is called descent time. The value of the anode current at time t4 is called the Dill current initial value, the current flowing from then until time t5 is called the Tilmi flow, and this time (ts - t4) is called the tail light period. The Tilmi current is a current generated because residual charges in the N base layer are discharged. The power loss P (=VAX IA) generated during the above operation has a waveform shown in the bottom row of FIG. 4.
以−Ｊ二のＧＴＯ動作において、特に電力損失が大きい
のは時刻ｔ３からｔｓまでの期間である。この期間の電
力損失に着目すると、降下時間（ｔ４−１３）が長いと
損失が大きく、またディル電流初期値が大きいとディル
期間の損失が大きくなること、が容易に分かる。この様
なターンオフ時の電力損失を小さくするため従来、電子
線照射や金属ドーピングによりＧＴＯ内部のキャリア寿
命を短縮する、等の解決策が考えられている。しかしこ
れらの方法は、ターンオン損失の増大や順方向電圧降下
の増加等をもたらすという問題がある。In the GTO operation described above, the power loss is particularly large during the period from time t3 to ts. Focusing on the power loss during this period, it is easy to see that the longer the fall time (t4-13) is, the greater the loss is, and the greater the initial value of the dill current, the greater the loss during the dill period. In order to reduce such power loss during turn-off, conventional solutions have been considered, such as shortening the carrier life inside the GTO by electron beam irradiation or metal doping. However, these methods have problems such as increased turn-on loss and increased forward voltage drop.
（発明が解決しようとする問題点）
以上のように従来のＧ丁Ｏでは、ターンオン損失、順方
向電圧降下の増加に伴う電力損失の増加を伴うことなく
、降下時間の短縮とティルミ流値の低減を図ることが難
しい、という問題がある。(Problems to be Solved by the Invention) As described above, in the conventional G-D O, the fall time can be shortened and the Tilmi current value can be reduced without increasing turn-on loss and power loss due to increase in forward voltage drop. There is a problem in that it is difficult to reduce the amount.
本発明は、この様な問題を解決したＧＴＯ装置を提供す
ることを目的とする。An object of the present invention is to provide a GTO device that solves these problems.
［発明の構成］
（問題点を解決するための手段）
本発明は上記問題を解決するため、Ｎベース層に第１ゲ
ート電極２Ｐベース層に第２ゲート電極を設けた所謂ダ
ブルゲート構造とするのが基本である。この場合、アノ
ード・エミッタ層とＮベース層間の降服電圧Ｖａｓｔと
、カソード・エミッタ層とＰベース層間の降服電圧ＶＧ
Ｒ２の関係が、
Ｖａ Ｒ１＞Ｖｏ Ｒ２
であるとき、第１ゲート電極に印加されるオフゲート電
源電圧の絶対値｜Ｅ１｜と、第２ゲート電極に印加され
るオフゲート電源電圧の絶対値ＩＥ２１との関係を、
ＩＦＩ ｌ＞ｌＥ２１
に設定したことを特徴とする。[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention adopts a so-called double gate structure in which a first gate electrode is provided in the N base layer, and a second gate electrode is provided in the P base layer. is the basics. In this case, the breakdown voltage Vast between the anode/emitter layer and the N base layer, and the breakdown voltage VG between the cathode/emitter layer and the P base layer.
When the relationship of R2 is Va R1>Vo R2, the absolute value |E1| of the off-gate power supply voltage applied to the first gate electrode and the absolute value IE21 of the off-gate power supply voltage applied to the second gate electrode It is characterized in that the relationship is set to IFI l>lE21.
（作用）
本発明によるダブルゲートＧＴＯでは、ターンオフ時、
Ｎベース層に形成した第１ゲートＮ極に正のオフゲート
パルスを印加し、Ｐベース層に形成した第２ゲート電極
に負のオフゲートパルスを印加する。これにより、アノ
ード側で導通領域のスクイズ、電子の吸い出し及びアノ
ード・エミッタ層からの正孔の注入抑制の動作が行われ
るど同時に、カソード側でも導通領域のスクイズ、正孔
の吸出し及び電子の注入抑制の動作が行われる。(Function) In the double gate GTO according to the present invention, at turn-off,
A positive off-gate pulse is applied to the first gate N pole formed on the N base layer, and a negative off-gate pulse is applied to the second gate electrode formed on the P base layer. As a result, on the anode side, the conduction region is squeezed, electrons are sucked out, and holes are suppressed from being injected from the anode/emitter layer.At the same time, on the cathode side, the conduction region is squeezed, holes are sucked out, and electrons are injected. A restraining action is taken.
そして本発明では、第１ゲート電極に印加するオフゲー
トＮ源電圧を第２ゲート電極に印加するオフゲート電源
電圧より高くとることにより、ターンオフ動作に従来に
ない挙動が生じる。即ちいま、第１ゲート電極側と第２
ゲート電極側のオフゲート回路が同じ構成であり、従っ
て両回路の配線インダクタンスＬ１．Ｌ２が同じである
とする。In the present invention, by setting the off-gate N source voltage applied to the first gate electrode higher than the off-gate power source voltage applied to the second gate electrode, an unprecedented behavior occurs in the turn-off operation. That is, now the first gate electrode side and the second gate electrode side
The off-gate circuits on the gate electrode side have the same configuration, so the wiring inductance of both circuits L1. Assume that L2 is the same.
このときそれぞれのゲート電流立上り率は、ｄ Ｉａ
ｉ ／ｄ ｔ４Ｅ１／Ｌｔ
ｄｌａ２／ｄｔ弁Ｅ２／Ｌ２
で表わされ、ｌＥｌ １＞ｌＥ２ １ならば、Ｌｔ＝
１−２であるから、
１ｄｌｏ１／ｄｔｌ＞１ｄｌａ２／’ｄｔｌなる関係が
成立する。従って単位時間に第１ゲート電極、第２ゲー
ｉ−電極からそれぞれ排出される電荷量Ｑ＋ 、Ｑ２の
間には、Ｑｌ ＞０２なる関係がある。この両ゲートの
関係を言替えると、第１ゲート電極側のターンオフ動作
は第２ゲート電極側のそれよりも速く進行し、カソード
・エミッタからの電子注入が抑制されるよりも速い時点
でアノード・エミッタからの電子注入が抑制されること
になる。これにより、ターンオン損失や順方向電圧降下
による電力損失を伴うことなく、ターンオフ時の降下時
間の短縮を図り、またティルミ流値を減少させることが
できる。At this time, each gate current rise rate is dIa
It is expressed as i /d t4E1/Lt dla2/dt valve E2/L2, and if lEl 1>lE2 1, then Lt=
1-2, the relationship 1dlo1/dtl>1dla2/'dtl holds true. Therefore, the relationship Ql>02 exists between the amounts of charge Q+ and Q2 discharged from the first gate electrode and the second gate i-electrode, respectively, per unit time. To put this relationship between the two gates in another way, the turn-off operation on the first gate electrode side proceeds faster than that on the second gate electrode side, and the anode turns off at a faster point than the electron injection from the cathode emitter is suppressed. Electron injection from the emitter will be suppressed. As a result, it is possible to shorten the drop time at turn-off and reduce the Tilmi current value without causing power loss due to turn-on loss or forward voltage drop.
（実施例） 以下、本発明の詳細な説明する。(Example) The present invention will be explained in detail below.
第１図は一実施例にかかるダブルゲート構造のＧＴＯ装
置を示す図である。ＧＴＯ素子１は、アノード・■ミッ
タ層１３．Ｎベース腑１１．Ｐベース層１２及びカソー
ド・エミッタｌ１ｉＷ１４のＰＮＰＮ４層構造を基本と
する。アノード・エミッタ層１３とＮベース層１１間の
降服電圧Ｖ Ｇ Ｒ１は、通常のＧＴＯがそうであるよ
うに、カソード・エミッタ層１４どＰベース層１２間の
降服電圧ＶＧ Ｒ２より大きい。１５はアノード電極、
１７はカソード電極であり、Ｎベース層１１には第１ゲ
ート電極１６が、Ｐベース層１２には第２ゲート電極１
８がそれぞれ設けられている。図では詳細に示さなかっ
たが、アノード・エミッタ層とＮベース層は一部短絡さ
れている。第１ゲート電極１６側にはオフゲート電ＷＡ
Ｎ圧Ｆ１とスイッチ素子Ｓ１からなるオフゲートパルス
発生器２が設けられ、第２ゲート電極１８側にはオフゲ
ート電源電圧Ｅ２とスイッチ素子Ｓ２からなるオフゲー
トパルス発生器３が設けられている。第１ゲート電極１
６側のオフゲート電源電圧［１の絶対値は、第２ゲート
電極１８側のオフゲート電源電圧Ｅ２の絶対値より大き
く設定されている。図ではオンゲート回路は省略してい
る。５は負荷、４は主電源である。FIG. 1 is a diagram showing a double gate structure GTO device according to one embodiment. The GTO element 1 includes an anode/mitter layer 13. N base sense 11. It is based on a PNPN four-layer structure including a P base layer 12 and a cathode/emitter l1iW14. The breakdown voltage V G R1 between the anode-emitter layer 13 and the N base layer 11 is larger than the breakdown voltage V G R2 between the cathode-emitter layer 14 and the P base layer 12, as in a normal GTO. 15 is an anode electrode;
17 is a cathode electrode, the N base layer 11 has a first gate electrode 16, and the P base layer 12 has a second gate electrode 1.
8 are provided respectively. Although not shown in detail in the figure, the anode/emitter layer and the N base layer are partially short-circuited. An off-gate voltage WA is provided on the first gate electrode 16 side.
An off-gate pulse generator 2 consisting of an N voltage F1 and a switching element S1 is provided, and an off-gate pulse generator 3 consisting of an off-gate power supply voltage E2 and a switching element S2 is provided on the second gate electrode 18 side. First gate electrode 1
The absolute value of the off-gate power supply voltage [1] on the 6 side is set to be larger than the absolute value of the off-gate power supply voltage E2 on the second gate electrode 18 side. The on-gate circuit is omitted in the figure. 5 is a load, and 4 is a main power source.
このように構成されたＧＴＯ装置の動作を、第２図の波
形図を参照して次に説明する。図には参考のため、シン
グルゲート構造の従来のＧＴＯ装置の特性を併せて示し
である。ターンオン動作の説明は省略し、時刻ｔ２以降
のターンオフ動作について説明すると、第１図のように
正のオフゲートＮ源Ｅ１と負のオフゲート電源Ｅ２が印
加された時、ＧＴＯ素子１内では第１ゲート電極１６に
より電子の吸い出しが行われ、同時に第２ゲート［！１
８によって正孔の吸い出しが行われる。これにより、Ｎ
ベース１１１．Ｐベース層１２内でそれぞれ導通領域の
スクイズが起り、アノード・エミッタ層１３からの正孔
注入の抑制、カソード・エミッタ層１４からの電子注入
の抑制が生じる。The operation of the GTO device configured as described above will now be described with reference to the waveform diagram of FIG. For reference, the figure also shows the characteristics of a conventional GTO device with a single gate structure. The explanation of the turn-on operation will be omitted, and the turn-off operation after time t2 will be explained. When the positive off-gate N source E1 and the negative off-gate power supply E2 are applied as shown in FIG. Electrons are sucked out by the electrode 16, and at the same time the second gate [! 1
8 sucks out holes. This results in N
Base 111. Squeezing of conduction regions occurs in the P base layer 12, and hole injection from the anode/emitter layer 13 and electron injection from the cathode/emitter layer 14 are suppressed.
このときオフゲート電源電圧Ｅｓ 、Ｆ２の絶対値の間
に前述のような差を設けている結果、第２図に示したよ
うに、第１ゲート電極１６によるオフゲート電流の最大
値１ ａ ｐ １は、第２ゲート電（示′１８によるオ
フゲート電流の最大ｔ＋ｔｉ Ｉ。Ｆ２より大きい値を
とる。従って、Ｎベース層１１のスクイズ、電子の吸い
出し及びアノード・エミッタ層１３からの正孔注入の抑
制の動作が、Ｐベース層１２のスクイズ、正孔の吸い出
し及びカソード・エミッタ層１４からの電子注入の抑制
より急速に進む。この結果、降下時間の途中からアノー
ド・エミッタ層からの正孔注入が制限されてテイル期間
に移行するから、ティルミ流の初期饋は従来より著しく
減少し、またテイル期間も短縮される。At this time, as a result of providing the above-mentioned difference between the absolute values of the off-gate power supply voltage Es and F2, as shown in FIG. 2, the maximum value 1 a p 1 of the off-gate current due to the first gate electrode 16 is , the second gate voltage (maximum t+ti I of the off-gate current according to '18) takes a value larger than F2. Therefore, it is possible to squeeze the N base layer 11, suck out electrons, and suppress hole injection from the anode/emitter layer 13. The operation proceeds rapidly by squeezing the P base layer 12, sucking out holes, and suppressing electron injection from the cathode/emitter layer 14. As a result, hole injection from the anode/emitter layer is restricted from the middle of the fall time. The initial feed rate of the Tilmi flow is significantly reduced compared to the conventional method, and the tail period is also shortened.
従ってこの実施例によれば、ＧＴＯ素子内部の電力損失
を効果的に減少させることができる。電力損失の減少は
、スイッチング頻度を高くすることを可能とするため、
高周波駆動ができるという効果も得られる。Therefore, according to this embodiment, the power loss inside the GTO element can be effectively reduced. Reducing power losses allows higher switching frequencies, so
The effect of high frequency drive is also obtained.
［発明の効果］
以上述べたように本発明によれば、ダブルゲート構造と
し、かつそのオフゲート電源電圧に差を持たせることに
より、ターンオン損失、順方向電圧降下に伴う電力損失
の増大を伴うことなく、ターンオフ時の降下時間の短縮
とティルミ流値の低減を図ることができる。[Effects of the Invention] As described above, according to the present invention, by providing a double gate structure and having a difference in off-gate power supply voltage, turn-on loss and power loss due to forward voltage drop are increased. Therefore, it is possible to shorten the descent time at turn-off and reduce the Tilmi flow value.
第１図は本発明の一実施例のＧＴＯ装置を示す図、第２
図はその動作を説明するための波形図、第３図は従来の
ＧＴＯ装置を示す図、第４図はその動作を説明するだめ
の波形図である。
１・・・ＧＴＯ素子、１１・・・Ｎベース層、１２・・
・Ｐベース層、１３・・・アノード・エミッタ層、１４
・・・カソード・エミッタ層、１５・・・アノード電極
、１６・・・第１ゲート電極、１７・・・カソード電極
、１８・・・第２ゲート電極、２，３・・・オフゲート
パル２発生器、４・・・主電源、５・・・０荷、Ｆｌ
、Ｆ２・・・オフゲート電源電圧。FIG. 1 is a diagram showing a GTO device according to an embodiment of the present invention, and FIG.
FIG. 3 is a waveform diagram for explaining its operation, FIG. 3 is a diagram showing a conventional GTO device, and FIG. 4 is a waveform diagram for explaining its operation. 1... GTO element, 11... N base layer, 12...
・P base layer, 13... Anode emitter layer, 14
... Cathode/emitter layer, 15... Anode electrode, 16... First gate electrode, 17... Cathode electrode, 18... Second gate electrode, 2, 3... Off gate pal 2 Generator, 4...Main power supply, 5...0 load, Fl
, F2... Off-gate power supply voltage.
Claims (3)
及びカソード、エミッタ層のＰＮＰＮ４層構造を有し、
Ｎベース層に第１ゲート電極、Ｐベース層に第２ゲート
電極を設け、これらゲート電極を駆動するゲートパルス
発生器を設けたゲートターンオフサイリスタ装置におい
て、前記アノード・エミッタ層とＮベース層間の降服電
圧Ｖ＿Ｇ＿Ｒ＿１と、前記カソード・エミッタ層とＰベ
ース層間の降服電圧Ｖ＿Ｇ＿Ｒ＿２の関係が、Ｖ＿Ｇ＿
Ｒ＿１＞Ｖ＿Ｇ＿Ｒ＿２ であるとき、前記第１ゲート電極に印加されるオフゲー
ト電源電圧の絶対値｜Ｅ＿１｜と前記第２ゲート電極に
印加されるオフゲート電源電圧の絶対値｜Ｅ＿２｜の関
係を、 ｜Ｅ＿１｜＞｜Ｅ＿２｜ に設定したことを特徴とするゲートターンオフサイリス
タ装置。(1) It has a PNPN four-layer structure of an anode/emitter layer, an N base layer, a P base layer, a cathode, and an emitter layer,
In a gate turn-off thyristor device in which a first gate electrode is provided on the N base layer, a second gate electrode is provided on the P base layer, and a gate pulse generator is provided for driving these gate electrodes, breakdown between the anode/emitter layer and the N base layer is provided. The relationship between the voltage V_G_R_1 and the breakdown voltage V_G_R_2 between the cathode/emitter layer and the P base layer is V_G_
When R_1>V_G_R_2, the relationship between the absolute value |E_1| of the off-gate power supply voltage applied to the first gate electrode and the absolute value |E_2| of the off-gate power supply voltage applied to the second gate electrode is |E_1 A gate turn-off thyristor device characterized by setting |>|E_2|.
絡されている特許請求の範囲第１項記載のゲートターン
オフサイリスタ装置。(2) The gate turn-off thyristor device according to claim 1, wherein the anode/emitter layer and the N base layer are partially short-circuited.
値の絶対値｜Ｉ＿Ｇ＿Ｐ＿１｜と前記第２ゲート電極に
よるオフゲート電流の最大値の絶対値｜Ｉ＿Ｇ＿Ｐ＿２
｜との関係が、 ｜Ｉ＿Ｇ＿Ｐ＿１｜＞｜Ｉ＿Ｇ＿Ｐ＿２｜ である特許請求の範囲第１項記載のゲートターンオフサ
イリスタ装置。(3) Absolute value of the maximum value of the off-gate current due to the first gate electrode |I_G_P_1| and absolute value of the maximum value of the off-gate current due to the second gate electrode |I_G_P_2
The gate turn-off thyristor device according to claim 1, wherein the relationship with | is |I_G_P_1|>|I_G_P_2|.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23176986A JPS6386566A (en) | 1986-09-30 | 1986-09-30 | Gate turn-off thyristor device |
| US07/101,790 US4821083A (en) | 1986-09-30 | 1987-09-28 | Thyristor drive system |
| EP87308676A EP0262958B1 (en) | 1986-09-30 | 1987-09-30 | Thyristor drive system |
| DE3751268T DE3751268T2 (en) | 1986-09-30 | 1987-09-30 | Thyristor driver system. |
| US07/701,002 US5132767A (en) | 1986-09-30 | 1991-05-13 | Double gate GTO thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23176986A JPS6386566A (en) | 1986-09-30 | 1986-09-30 | Gate turn-off thyristor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6386566A true JPS6386566A (en) | 1988-04-16 |
Family
ID=16928740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23176986A Pending JPS6386566A (en) | 1986-09-30 | 1986-09-30 | Gate turn-off thyristor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6386566A (en) |
-
1986
- 1986-09-30 JP JP23176986A patent/JPS6386566A/en active Pending
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