JPS61182261A - Driving method of gate turn-off thyristor - Google Patents

Driving method of gate turn-off thyristor

Info

Publication number
JPS61182261A
JPS61182261A JP60021888A JP2188885A JPS61182261A JP S61182261 A JPS61182261 A JP S61182261A JP 60021888 A JP60021888 A JP 60021888A JP 2188885 A JP2188885 A JP 2188885A JP S61182261 A JPS61182261 A JP S61182261A
Authority
JP
Japan
Prior art keywords
layer
gate
short
turn
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60021888A
Other languages
Japanese (ja)
Inventor
Katsuhiko Takigami
滝上 克彦
Takashi Yotsudo
孝 四戸
Hiromichi Ohashi
弘通 大橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60021888A priority Critical patent/JPS61182261A/en
Publication of JPS61182261A publication Critical patent/JPS61182261A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/74Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744Gate-turn-off devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)
  • Thyristor Switches And Gates (AREA)

Abstract

PURPOSE:To reduce switching loss by starting the application of the driving voltage of a gate for a FET short-circuiting PE and NB prior to the application of negative voltage between PB and NE when driving a GTOSCR having PENBPBNE structure. CONSTITUTION:A FET9 short-circuiting at low resistance is formed between an anode 5 and an NB layer 3, and a power supply 10 giving a bias and a switching element 11 are fitted among gates 7a, 7b and a cathode 6 on a PB layer 2. A PE and an NB are short-circuited by a signal G1 first on the starting of a turn-OFF, the injection of holes from a PE layer 4 is inhibited remarkably, anode currents ia are reduced, a signal G2 is added delayed by a time Td, a reverse bias is applied to an NE layer 1 and a PB layer 2, and the injection of electrons from the NE layer 1 is stopped. According to the driving method, the PE and the NB are short-circuited at low resistance only on the turn-OFF, thus minimizing switching loss without a forward voltage drop and the increase of latching.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、ゲートターンオフサイリスタ(以下GTO)
のゲート駆動方式に関する。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a gate turn-off thyristor (hereinafter referred to as GTO).
Regarding the gate driving method.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

GTOは、ゲートで主電流をオン、オフ出来る利点が注
目され近年、著しい進歩をとげている。
GTOs have attracted attention for their advantage of being able to turn on and off the main current at the gate, and have made remarkable progress in recent years.

また、ターンオフ電流容量の拡大や阻止電圧の向上のだ
めの研究も進んでいる。一方、高周波駆動装置への応用
も重要視されている。そこで問題となるのが、電力損失
によるGTOの温度上昇である0 即ち、GTOを稼動する除虫じる電力損失がパッケージ
の熱抵抗等で決まる許容温度以上に素子を熱してしまう
と、定格のターンオフ電流をゲートターンオフ出来ない
ばかりか、素子破壊をまねくという問題があった。
Research is also progressing on ways to expand turn-off current capacity and improve blocking voltage. On the other hand, application to high-frequency drive devices is also considered important. The problem is that the temperature of the GTO rises due to power loss.In other words, if the power loss required to operate the GTO heats up the device beyond the allowable temperature determined by the thermal resistance of the package, etc. There is a problem in that not only the turn-off current cannot be turned off at the gate, but also the device may be destroyed.

GTOの電力損失に関して図を用いて説明する。The power loss of the GTO will be explained using a diagram.

第1図は、電圧、電流及び電力損失の三者の関係を示す
もので電力損失の大部分は同図の領域I。
Figure 1 shows the relationship between voltage, current, and power loss, and most of the power loss is in region I of the figure.

■、■で生じる。但し、ターンオフ、ターンオフ領域の
スイッチング損失QB、qB1は、Qm = f  V
a−1adt   山=−山(2)で与えられる。
Occurs in ■, ■. However, the switching losses QB and qB1 in the turn-off and turn-off regions are Qm = f V
It is given by a-1adt mountain = - mountain (2).

電力損失の総和POと周波数fとの関係は次式で与えら
れる。
The relationship between the total power loss PO and the frequency f is given by the following equation.

Po = (QI+ Q■) f+VTM−IA−D 
山、、、  (3)但し:D−通電率、 (3)式かられかるようにスイッチング損失は、周波数
と線型の関係にあるので駆動周波数fが例えば10” 
(Hz )を超える、いわゆるパワー素子としては高周
波領域では、定常損失(領域■)と比較し極めて重要な
意味をもっている。例えば、2.5 KV、IKA級の
GTOをf = 2KH2で駆動すると、全損失の90
係以上はスイッチング損失で占められる。
Po = (QI+Q■) f+VTM-IA-D
Mountain... (3) However: D - conduction rate As can be seen from equation (3), switching loss has a linear relationship with frequency, so if the driving frequency f is, for example, 10"
(Hz), so-called power elements have extremely important meaning in the high frequency region compared to the steady loss (region 2). For example, when driving a 2.5 KV, IKA class GTO at f = 2KH2, the total loss is 90
Switching loss accounts for more than 30% of the total loss.

第3図で示すように、スイッチング損失の中でも領域■
の時点Ttai1以上の損失が無視できない。
As shown in Figure 3, the area ■
The loss at or above the time Ttai1 cannot be ignored.

時点TLatl以降は、一般にティル時間と呼ばれ、G
TO中の残留電荷の排出に要する時間である。結局、こ
の損失を小さくしないと、高周波駆動が不可能である。
The period after time TLatl is generally called till time, and G
This is the time required to discharge the residual charge in TO. After all, high frequency driving is impossible unless this loss is reduced.

かかる理由から、従来型GTOにおいては、ティルミ流
が大きく、かつ減衰時数が長いことが一般的であって、
高周波駆動をすることが出来ないという問題点があった
。そのため、GTOを高周波駆動するには、ターンオフ
時に限定するとティルミ流初期値を小さくする事と、減
衰時定数を短かくする方法が望まれていた。減衰時定数
を短かくすることは、GTO内部の少数キャリアライフ
タイムを短縮することであり、定常時の電圧降下が異常
に増加したり、ラッチング電流の増大をまねくので、お
のずから限度があった。
For this reason, in conventional GTOs, the Tilmi flow is generally large and the decay time is long.
There was a problem that high frequency driving was not possible. Therefore, in order to drive the GTO at high frequency, it has been desired to reduce the initial value of the Tilmi flow and to shorten the decay time constant, especially during turn-off. Shortening the decay time constant shortens the minority carrier lifetime inside the GTO, which naturally leads to an abnormal increase in the voltage drop during steady state and an increase in the latching current.

〔発明の目的〕[Purpose of the invention]

本発明は上記の点に鑑み、GTOのスイッチング損失の
軽減方法として、ティルミ流初期を減少させることを目
的としている。
In view of the above points, the present invention aims to reduce the initial stage of the Tilmi flow as a method for reducing switching loss of a GTO.

〔発明の概要〕[Summary of the invention]

本発明は、ティルミ流部ちGTOのNベース中に残留し
たホールの排出電流を減少させる方法として、これまで
用すられていたpベースのゲート電極とNエミッタのカ
ソード電極間に負バイアスを印加してNエミッタからの
エレクトロンの注入を停止させる以前にpエミッタのア
ノードと、Nベース層間を低抵抗短絡してホールの注入
を抑制するものである。
The present invention applies a negative bias between the gate electrode of the p-base and the cathode electrode of the n-emitter, which has been used so far, as a method for reducing the discharge current of holes remaining in the N-base of the Tilmi flow section and the N-base of the GTO. Before stopping the injection of electrons from the N emitter, a low resistance short is made between the anode of the P emitter and the N base layer to suppress hole injection.

〔発明の効果〕〔Effect of the invention〕

本発明は、ゲートターンオフ時のみpエミッタとNベー
ス間を低抵抗短絡するので、従来から広く知られている
アノード側にNベースの一部を露出し、アノード電極で
短絡する、いわゆるアノードシ目−ト型GTOのように
、常時シ箇−トしていないので、順方向電圧降下を増加
させず、かつラッチングを増大させずにスイッチング損
失を軽減できるという効果がある。
The present invention short-circuits the p-emitter and the n-base with low resistance only at the time of gate turn-off, so the so-called anode seam, which exposes a part of the n-base on the anode side and shorts it at the anode electrode, is conventionally widely known. Unlike the gate-type GTO, since it is not always switched off, it has the effect of reducing switching loss without increasing forward voltage drop and without increasing latching.

〔□発明の実施例〕[□Examples of the invention]

以下実施例により本発明の詳細な説明する。 The present invention will be explained in detail below with reference to Examples.

本発明と従来例との差を明確にするために、 GTOの
ターンオフ時への電圧、電流、電力波形を両者比較する
In order to clarify the differences between the present invention and the conventional example, the voltage, current, and power waveforms at turn-off of the GTO will be compared between the two.

第2図(a)は従来のGTO駆動法による電圧、電流波
形、同図(b)はターンオフ現象が進行して、いわゆる
スクイズ(電流通電領域の縮少)が完了した時点(Tt
a目)近傍のGTO断面図と、残留電荷であるホールの
流れを示す図である。
Figure 2 (a) shows the voltage and current waveforms according to the conventional GTO driving method, and Figure 2 (b) shows the point at which the turn-off phenomenon progresses and the so-called squeeze (reduction of the current carrying area) is completed (Tt
FIG. 3 is a cross-sectional view of the GTO in the vicinity of eye a) and a diagram showing the flow of holes, which are residual charges.

同図(b)はPNPNの四層構造半導体に、アノード電
極5、カソード電極6、ゲート電極7a、7bを設け、
オフバイアス電源10で、ゲートカソード間に逆電圧を
印加している。同図(b)の如く、Nベース中には、ホ
ールが残留し、この電荷量がItail値を決めている
。、 次に第2図を用いて本発明の駆動方法を説明する0 同図(a)はターンオフ時のGTO断面図および、アノ
ード5とNベース3と低抵抗短絡するMOSFET9と
ゲート7a、7b・カン−ドロ間に負パイアスを与える
電源lO、スイッチ素子11の結線したものを示す。
In the same figure (b), an anode electrode 5, a cathode electrode 6, and gate electrodes 7a and 7b are provided in a PNPN four-layer structure semiconductor,
An off-bias power supply 10 applies a reverse voltage between the gate and cathode. As shown in FIG. 5B, holes remain in the N base, and the amount of charge determines the Itail value. Next, the driving method of the present invention will be explained using FIG. 2. FIG. The connection of a power source lO and a switch element 11 which provides a negative bias between the can and the doro is shown.

同図(b)は、上記(a)図の結線での電圧、電流、電
力損失波形と駆動信号Gl、G2を示す。同図で実線は
本発明の方法を示し、破線は従来の駆動法による例を示
す。
FIG. 5B shows voltage, current, power loss waveforms, and drive signals Gl and G2 in the connection shown in FIG. In the figure, the solid line shows the method of the present invention, and the broken line shows an example using the conventional driving method.

動作は、ターンオフ開始時に先づ信号G1を入力し、P
エミッタとNベースを短絡する。その結果両者間の電位
差が著しく小さくなり、Pエミッタからのホールの注入
が著しく抑制され、アノード電流iaが減少し始める。
The operation is performed by first inputting signal G1 at the start of turn-off, and then inputting signal G1.
Short the emitter and N base. As a result, the potential difference between the two becomes significantly smaller, the injection of holes from the P emitter is significantly suppressed, and the anode current ia begins to decrease.

更にTdの時間遅れで信号G2を入力する。Furthermore, signal G2 is input with a time delay of Td.

その結果、同図の電流波形で示すように、本発明と従来
例との間に大きな差が生じる。この差は直接電力損失の
差となシ、本発明の駆動法が省電力でかつ、高周波駆動
を可能にする。第1図(a)で示したMOSFET9は
外付の例であるがGTOと一体化する方法でもよいこと
は当然である。
As a result, as shown by the current waveform in the figure, a large difference arises between the present invention and the conventional example. This difference is not directly a difference in power loss, and the driving method of the present invention saves power and enables high-frequency driving. The MOSFET 9 shown in FIG. 1(a) is an example of an external device, but it goes without saying that it may be integrated with the GTO.

またMOSFETによる短絡をより一層効果的にするた
めにP工はツタと接する近傍のN層の不純物濃度を他の
部分よりも高くすることが望ましい。
Further, in order to make the short circuit by the MOSFET even more effective, it is desirable that the impurity concentration of the N layer in the vicinity of the P layer in contact with the vine is higher than that in other parts.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のゲート駆動方法による電圧、電流、電
力波形と、スクイズ完了時近傍におけるキャリアの流れ
図、第2図は従来のGTO駆動方法による電圧、電流、
電力波形とスクイズ完了時近傍のキャリアの流れ図、第
3図はGTOの電力損失を説明する為の図である。 5・・・アノード電極、  6・・・カソード電極、7
・・・ゲート電極、  9・・・MOSFET。 10・・・オフバイアス電源、11・・・スイッチ素子
0(7317)弁理士 則近憲佑 (ほか1名) 第2図
FIG. 1 shows the voltage, current, and power waveforms according to the gate driving method of the present invention, and the carrier flow diagram near the time of completion of squeeze, and FIG. 2 shows the voltage, current, and power waveforms according to the conventional GTO driving method.
The power waveform and the flowchart of the carrier near the time of completion of the squeeze are illustrated in FIG. 3 for explaining the power loss of the GTO. 5... Anode electrode, 6... Cathode electrode, 7
...Gate electrode, 9...MOSFET. 10... Off-bias power supply, 11... Switch element 0 (7317) Patent attorney Norichika Kensuke (and 1 other person) Figure 2

Claims (1)

【特許請求の範囲】[Claims]  第1導電型の第1エミッタ層、第2導電型の第1ベー
ス層、第1導電型の第2ベース層、第2導電型の第2エ
ミッタ層がこの順序に積層され、かつ、第1主面に第1
エミッタ層と第1ベース層が露出し、第1エミッタ層に
はアノード電極が設けられ第1ベース層と第1エミッタ
層間はMOSFETで短絡され、該MOSFETのゲー
ト電極が露出されるとともに、第2主面には第2エミッ
タ層、第2ベース層が露出し、それぞれ第2エミッタ層
にはカソード電極、第2ベース層にはゲート電極を設け
る構成のゲートターンオフサイリスタにおいて、ゲート
ターンオフを行なわせる場合、第1エミッタと第1ベー
ス間を短絡する前記MOSFETのゲート・ソース間に
与えるゲート駆動電圧の印加開始時刻を、第2ベースに
設けられたゲート電極と第2エミッタに設けられたカソ
ード電極間に負方向の電圧を印加する時刻よりも早くす
ることを特徴とするゲートターンオフサイリスタの駆動
法。
A first emitter layer of the first conductivity type, a first base layer of the second conductivity type, a second base layer of the first conductivity type, and a second emitter layer of the second conductivity type are laminated in this order, and 1st on main surface
The emitter layer and the first base layer are exposed, the first emitter layer is provided with an anode electrode, the first base layer and the first emitter layer are short-circuited by a MOSFET, the gate electrode of the MOSFET is exposed, and the second When performing gate turn-off in a gate turn-off thyristor in which a second emitter layer and a second base layer are exposed on the main surface, a cathode electrode is provided in the second emitter layer, and a gate electrode is provided in the second base layer, respectively. , the time to start applying the gate drive voltage applied between the gate and source of the MOSFET that short-circuits the first emitter and the first base is set between the gate electrode provided on the second base and the cathode electrode provided on the second emitter. A method for driving a gate turn-off thyristor, characterized in that the gate turn-off is earlier than the time when a negative voltage is applied to the gate.
JP60021888A 1985-02-08 1985-02-08 Driving method of gate turn-off thyristor Pending JPS61182261A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60021888A JPS61182261A (en) 1985-02-08 1985-02-08 Driving method of gate turn-off thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60021888A JPS61182261A (en) 1985-02-08 1985-02-08 Driving method of gate turn-off thyristor

Publications (1)

Publication Number Publication Date
JPS61182261A true JPS61182261A (en) 1986-08-14

Family

ID=12067644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60021888A Pending JPS61182261A (en) 1985-02-08 1985-02-08 Driving method of gate turn-off thyristor

Country Status (1)

Country Link
JP (1) JPS61182261A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0262958A2 (en) * 1986-09-30 1988-04-06 Kabushiki Kaisha Toshiba Thyristor drive system
EP0280536A2 (en) * 1987-02-26 1988-08-31 Kabushiki Kaisha Toshiba Turn-on driving technique for insulated gate thyristor
US5132767A (en) * 1986-09-30 1992-07-21 Kabushiki Kaisha Toshiba Double gate GTO thyristor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0262958A2 (en) * 1986-09-30 1988-04-06 Kabushiki Kaisha Toshiba Thyristor drive system
US5132767A (en) * 1986-09-30 1992-07-21 Kabushiki Kaisha Toshiba Double gate GTO thyristor
EP0280536A2 (en) * 1987-02-26 1988-08-31 Kabushiki Kaisha Toshiba Turn-on driving technique for insulated gate thyristor

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