JPS61182261A - Driving method of gate turn-off thyristor - Google Patents

Abstract

PURPOSE:To reduce switching loss by starting the application of the driving voltage of a gate for a FET short-circuiting PE and NB prior to the application of negative voltage between PB and NE when driving a GTOSCR having PENBPBNE structure. CONSTITUTION:A FET9 short-circuiting at low resistance is formed between an anode 5 and an NB layer 3, and a power supply 10 giving a bias and a switching element 11 are fitted among gates 7a, 7b and a cathode 6 on a PB layer 2. A PE and an NB are short-circuited by a signal G1 first on the starting of a turn-OFF, the injection of holes from a PE layer 4 is inhibited remarkably, anode currents ia are reduced, a signal G2 is added delayed by a time Td, a reverse bias is applied to an NE layer 1 and a PB layer 2, and the injection of electrons from the NE layer 1 is stopped. According to the driving method, the PE and the NB are short-circuited at low resistance only on the turn-OFF, thus minimizing switching loss without a forward voltage drop and the increase of latching.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a gate turn-off thyristor (hereinafter referred to as GTO).
Regarding the gate driving method.

[Technical background of the invention and its problems]

GTOs have attracted attention for their advantage of being able to turn on and off the main current at the gate, and have made remarkable progress in recent years.

Research is also progressing on ways to expand turn-off current capacity and improve blocking voltage. On the other hand, application to high-frequency drive devices is also considered important. The problem is that the temperature of the GTO rises due to power loss.In other words, if the power loss required to operate the GTO heats up the device beyond the allowable temperature determined by the thermal resistance of the package, etc. There is a problem in that not only the turn-off current cannot be turned off at the gate, but also the device may be destroyed.

The power loss of the GTO will be explained using a diagram.

Figure 1 shows the relationship between voltage, current, and power loss, and most of the power loss is in region I of the figure.

Occurs in ■, ■. However, the switching losses QB and qB1 in the turn-off and turn-off regions are Qm = f V
It is given by a-1adt mountain = - mountain (2).

The relationship between the total power loss PO and the frequency f is given by the following equation.

Po = (QI+Q■) f+VTM-IA-D
Mountain... (3) However: D - conduction rate As can be seen from equation (3), switching loss has a linear relationship with frequency, so if the driving frequency f is, for example, 10"
(Hz), so-called power elements have extremely important meaning in the high frequency region compared to the steady loss (region 2). For example, when driving a 2.5 KV, IKA class GTO at f = 2KH2, the total loss is 90
Switching loss accounts for more than 30% of the total loss.

As shown in Figure 3, the area ■
The loss at or above the time Ttai1 cannot be ignored.

The period after time TLatl is generally called till time, and G
This is the time required to discharge the residual charge in TO. After all, high frequency driving is impossible unless this loss is reduced.

For this reason, in conventional GTOs, the Tilmi flow is generally large and the decay time is long.
There was a problem that high frequency driving was not possible. Therefore, in order to drive the GTO at high frequency, it has been desired to reduce the initial value of the Tilmi flow and to shorten the decay time constant, especially during turn-off. Shortening the decay time constant shortens the minority carrier lifetime inside the GTO, which naturally leads to an abnormal increase in the voltage drop during steady state and an increase in the latching current.

[Purpose of the invention]

In view of the above points, the present invention aims to reduce the initial stage of the Tilmi flow as a method for reducing switching loss of a GTO.

[Summary of the invention]

The present invention applies a negative bias between the gate electrode of the p-base and the cathode electrode of the n-emitter, which has been used so far, as a method for reducing the discharge current of holes remaining in the N-base of the Tilmi flow section and the N-base of the GTO. Before stopping the injection of electrons from the N emitter, a low resistance short is made between the anode of the P emitter and the N base layer to suppress hole injection.

〔Effect of the invention〕

The present invention short-circuits the p-emitter and the n-base with low resistance only at the time of gate turn-off, so the so-called anode seam, which exposes a part of the n-base on the anode side and shorts it at the anode electrode, is conventionally widely known. Unlike the gate-type GTO, since it is not always switched off, it has the effect of reducing switching loss without increasing forward voltage drop and without increasing latching.

[□Examples of the invention]

The present invention will be explained in detail below with reference to Examples.

In order to clarify the differences between the present invention and the conventional example, the voltage, current, and power waveforms at turn-off of the GTO will be compared between the two.

Figure 2 (a) shows the voltage and current waveforms according to the conventional GTO driving method, and Figure 2 (b) shows the point at which the turn-off phenomenon progresses and the so-called squeeze (reduction of the current carrying area) is completed (Tt
FIG. 3 is a cross-sectional view of the GTO in the vicinity of eye a) and a diagram showing the flow of holes, which are residual charges.

In the same figure (b), an anode electrode 5, a cathode electrode 6, and gate electrodes 7a and 7b are provided in a PNPN four-layer structure semiconductor,
An off-bias power supply 10 applies a reverse voltage between the gate and cathode. As shown in FIG. 5B, holes remain in the N base, and the amount of charge determines the Itail value. Next, the driving method of the present invention will be explained using FIG. 2. FIG. The connection of a power source lO and a switch element 11 which provides a negative bias between the can and the doro is shown.

FIG. 5B shows voltage, current, power loss waveforms, and drive signals Gl and G2 in the connection shown in FIG. In the figure, the solid line shows the method of the present invention, and the broken line shows an example using the conventional driving method.

The operation is performed by first inputting signal G1 at the start of turn-off, and then inputting signal G1.
Short the emitter and N base. As a result, the potential difference between the two becomes significantly smaller, the injection of holes from the P emitter is significantly suppressed, and the anode current ia begins to decrease.

Furthermore, signal G2 is input with a time delay of Td.

As a result, as shown by the current waveform in the figure, a large difference arises between the present invention and the conventional example. This difference is not directly a difference in power loss, and the driving method of the present invention saves power and enables high-frequency driving. The MOSFET 9 shown in FIG. 1(a) is an example of an external device, but it goes without saying that it may be integrated with the GTO.

Further, in order to make the short circuit by the MOSFET even more effective, it is desirable that the impurity concentration of the N layer in the vicinity of the P layer in contact with the vine is higher than that in other parts.

[Brief explanation of drawings]

FIG. 1 shows the voltage, current, and power waveforms according to the gate driving method of the present invention, and the carrier flow diagram near the time of completion of squeeze, and FIG. 2 shows the voltage, current, and power waveforms according to the conventional GTO driving method.
The power waveform and the flowchart of the carrier near the time of completion of the squeeze are illustrated in FIG. 3 for explaining the power loss of the GTO. 5... Anode electrode, 6... Cathode electrode, 7
...Gate electrode, 9...MOSFET. 10... Off-bias power supply, 11... Switch element 0 (7317) Patent attorney Norichika Kensuke (and 1 other person) Figure 2

Claims (1)

[Claims] A first emitter layer of the first conductivity type, a first base layer of the second conductivity type, a second base layer of the first conductivity type, and a second emitter layer of the second conductivity type are laminated in this order, and 1st on main surface
The emitter layer and the first base layer are exposed, the first emitter layer is provided with an anode electrode, the first base layer and the first emitter layer are short-circuited by a MOSFET, the gate electrode of the MOSFET is exposed, and the second When performing gate turn-off in a gate turn-off thyristor in which a second emitter layer and a second base layer are exposed on the main surface, a cathode electrode is provided in the second emitter layer, and a gate electrode is provided in the second base layer, respectively. , the time to start applying the gate drive voltage applied between the gate and source of the MOSFET that short-circuits the first emitter and the first base is set between the gate electrode provided on the second base and the cathode electrode provided on the second emitter. A method for driving a gate turn-off thyristor, characterized in that the gate turn-off is earlier than the time when a negative voltage is applied to the gate.