JPS6386443A - Mounting of semiconductor chip - Google Patents
Mounting of semiconductor chipInfo
- Publication number
- JPS6386443A JPS6386443A JP61230109A JP23010986A JPS6386443A JP S6386443 A JPS6386443 A JP S6386443A JP 61230109 A JP61230109 A JP 61230109A JP 23010986 A JP23010986 A JP 23010986A JP S6386443 A JPS6386443 A JP S6386443A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- leads
- film carrier
- lead
- electrode pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000010586 diagram Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は、例えばテープキャリア方式による半導体チ
ップの実装法に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a method for mounting semiconductor chips using, for example, a tape carrier method.
（従来の技術）
近年、半導体技術の発展により、電子装置を小型で高機
能にする要求から、半導体チップの薄型高密度実装化が
進んでいる。この薄型高密度実装化を実現するための手
段として、例えば半導体チップをフィルムキャリアに取
付けて実装する所謂テープキャリア方式（ＴＡＢ）があ
る。(Prior Art) In recent years, with the development of semiconductor technology, semiconductor chips have become thinner and more densely packaged due to the demand for smaller and more highly functional electronic devices. As a means for realizing this thin and high-density packaging, there is, for example, the so-called tape carrier method (TAB) in which a semiconductor chip is mounted on a film carrier.
このようなテープキャリア方式に用いられるフィルムキ
ャリアとしては、例えば第６図および第７図に示すもの
がある。すなわち、フィルムキャリア１０１には、半導
体チップ１０３を搭載可能な孔部１０５が形成されてい
る。フィルムキャリア１０１の一面には外部回路に接続
可能なリード１０９が複数段けられ、リード１０９は孔
部１０５に突出している。そして、リード１０９の基部
と先端部とは、フィルムキャリア１０１の一面に形成さ
れたパターンの延長としてフィルムキャリア１０１と略
同−平面上に位置している。Examples of film carriers used in such a tape carrier system include those shown in FIGS. 6 and 7. That is, the film carrier 101 has a hole 105 in which the semiconductor chip 103 can be mounted. A plurality of leads 109 connectable to an external circuit are provided on one surface of the film carrier 101, and the leads 109 protrude into the holes 105. The base and tip of the lead 109 are located substantially on the same plane as the film carrier 101 as an extension of the pattern formed on one surface of the film carrier 101.
なお、テープキャリア方式においては、半導体チップ１
０３の電極パッド１１１とリード１０９との接続を容易
にすると共に、接合時の熱や圧力から半導体素子を保護
するために、電極パッド１１１又はリード１０９に接続
媒体であるバンブ１１３が設けられたものが知られてい
る。そして、リード１０９の基部と先端部とはバンブ１
１３が電極パッド１１１とリード１０９とのいずれに設
けられていようとフィルムキャリア１０１と略同−面上
に位置している。Note that in the tape carrier method, the semiconductor chip 1
In order to facilitate the connection between the electrode pad 111 and the lead 109 of 03 and to protect the semiconductor element from heat and pressure during bonding, a bump 113 as a connection medium is provided on the electrode pad 111 or the lead 109. It has been known. The base and tip of the lead 109 are connected to the bump 1.
13 is located substantially on the same plane as the film carrier 101, regardless of whether it is provided on the electrode pad 111 or the lead 109.
そして、このようなフィルムキャリア１０１のリード１
０９に半導体チップ１０３の電極パッド１１１がボンデ
ィングツール１１５により接続される。And lead 1 of such a film carrier 101
The electrode pads 111 of the semiconductor chip 103 are connected to 09 by a bonding tool 115.
ところで、このような従来のフィルムキャリアにあって
は、リード１０９の基部と先端部とがフィルムキャリア
１０１と略同−平面上に位置しており半導体チップ１０
３のエツジとり−ド１０９との隙間が小さいため、半導
体チップ１０３の接合時に生じる両者の相対的な傾き等
により半導体チップ１０３のエツジが例えば第８図のよ
うにリード１０９に接触しやすく、このような場合、半
導体チップ１０３の表面上に浮遊電位差（所謂エツジシ
ョート）が発生する虞れがある。なお、電極パッド１１
１とリード１０９との間にバンブが設けられたものにお
いても、バンブの高さではエツジショートを抑えるのに
充分な半導体チップ１０３のエツジとリード１０９との
隙間を形成することができずエツジショートする虞れは
ある。By the way, in such a conventional film carrier, the base and the tip of the lead 109 are located approximately on the same plane as the film carrier 101, so that the semiconductor chip 10
Since the gap between the lead 109 and the edge lead 109 of the semiconductor chip 103 is small, the edge of the semiconductor chip 103 tends to come into contact with the lead 109 as shown in FIG. In such a case, a floating potential difference (so-called edge short) may occur on the surface of the semiconductor chip 103. Note that the electrode pad 11
Even in the case where a bump is provided between the semiconductor chip 103 and the lead 109, the height of the bump makes it impossible to form a gap between the edge of the semiconductor chip 103 and the lead 109 that is sufficient to suppress an edge short, resulting in an edge short. There is a possibility that it will.
（発明が解決しようとする問題点）
以上説明したように従来のフィルムキャリアでは、リー
ドがフィルムキャリアと略同−平面上に位置しているた
め、接合時の傾き等により半導体チップのエツジとリー
ドとが接触してエツジショートする虞れがある。(Problems to be Solved by the Invention) As explained above, in conventional film carriers, the leads are located approximately on the same plane as the film carrier. There is a risk of edge shorting due to contact.
この発明は上記問題に着目してなされたもので、フィル
ムキャリアと半導体チップとの接合時に傾き等が生じて
も、半導体チップのエツジとリードとの接触を抑えるこ
とができる半導体チップの実装法の提供を目的とする。This invention was made in view of the above problem, and is a semiconductor chip mounting method that can suppress contact between the edges of the semiconductor chip and the leads even if the film carrier and the semiconductor chip are tilted during bonding. For the purpose of providing.
［発明の構成］
（問題点を達成するための手段）
上記目的を達成するためにこの発明は、フィルムキャリ
アに形成された孔部に半導体チップを配設し、この半導
体チップに配設された複数の電極パッドと、前記フィル
ムキャリアに設けられ先端部が前記孔部に臨む複数のリ
ードとを接続する半導体チップの実装法において、前記
電極パッドとリードとの接続時に前記リードを前記電極
パッドとの接続部が前記半導体チップ側に位置するよう
に変形させることとした。[Structure of the Invention] (Means for Achieving the Problem) In order to achieve the above object, the present invention provides a semiconductor chip disposed in a hole formed in a film carrier, and a semiconductor chip disposed in the semiconductor chip. In a semiconductor chip mounting method that connects a plurality of electrode pads and a plurality of leads provided on the film carrier and whose tips face the hole, when connecting the electrode pads and the leads, the leads are connected to the electrode pads. It was decided to deform the structure so that the connecting portion thereof is located on the semiconductor chip side.
（作用）
上記構成において、半導体チップの電極パッドとフィル
ムキャリアのリードとの接続時に、リードは電極パッド
との接続部が半導体チップ側に位置するように変形され
る。(Function) In the above structure, when the electrode pad of the semiconductor chip and the lead of the film carrier are connected, the lead is deformed so that the connection part with the electrode pad is located on the semiconductor chip side.
（実施例）
以下図面に基づき、この発明の実施例を詳細に説明する
。(Example) Examples of the present invention will be described in detail below based on the drawings.
第１図および第２図は、この発明の一実施例に係わる半
導体チップの実装法を示している。FIGS. 1 and 2 show a method of mounting a semiconductor chip according to an embodiment of the present invention.
第１図および第２図において、ポリイミド等の絶縁性樹
脂テープからなるフィルムキャリア１には半導体チップ
３を搭載する孔部５が形成され、半導体チップ３は孔部
５の図中下方からフィルムキャリア１に搭載される。ま
た、フィルムキャリア１の左右縁部には長さ方向に送り
孔が設けられ、フィルムキャリア１は図外の送り装置に
より孔部５の１コマ毎に移動可能となっている。1 and 2, a hole 5 for mounting a semiconductor chip 3 is formed in a film carrier 1 made of an insulating resin tape such as polyimide, and the semiconductor chip 3 is inserted into the film carrier from the bottom of the hole 5 in the figure. It will be installed on 1. Further, feeding holes are provided in the left and right edges of the film carrier 1 in the length direction, and the film carrier 1 can be moved frame by frame through the holes 5 by a feeding device (not shown).
フィルムキャリア１の一面（図中上面）には銅等の金属
箔からなるリード９が孔部５の各辺に沿い所定のピッチ
を持って複数配設されている。リード９の基部はフィル
ムキャリア１上で回路パターンを構成し、リード９の先
端部は半導体チップ３の電極パッド１１との接続部とし
て孔部５に突出して臨んでいる。A plurality of leads 9 made of metal foil such as copper are arranged on one surface (upper surface in the figure) of the film carrier 1 along each side of the hole 5 at a predetermined pitch. The bases of the leads 9 constitute a circuit pattern on the film carrier 1, and the tips of the leads 9 protrude into the holes 5 as connection parts with the electrode pads 11 of the semiconductor chip 3.
一方、半導体チップ３はステージ１３上に所定間隔を有
して載置されている。半導体チップ３の上面には回路パ
ターン１５および前記電極バッド１１が設けられ、例え
ば電極バッド１１の上部には金等からなる接続媒体とし
てバンブ１７が設けられている。これにより、電極バッ
ド１１とり一ド９との接続を容易にすると共に、接合時
の熱や圧力から半導体素子を保護する。On the other hand, the semiconductor chips 3 are placed on the stage 13 at a predetermined interval. A circuit pattern 15 and the electrode pad 11 are provided on the upper surface of the semiconductor chip 3, and a bump 17 is provided as a connection medium made of gold or the like on the upper part of the electrode pad 11, for example. This facilitates the connection between the electrode pad 11 and the pad 9, and protects the semiconductor element from heat and pressure during bonding.
そして、フィルムキャリア１の移動途中には上下動可能
なボンディングツール１９がフィルムキャリア１の上方
に配設されている。ボンディングツール１９には図外の
ヒータが設けられ、フィルムキャリア１のリード９と半
導体チップ３の電極バッド１１とを熱圧着して接合させ
る構成となっている。A bonding tool 19 that can move up and down is disposed above the film carrier 1 while the film carrier 1 is moving. The bonding tool 19 is provided with a heater (not shown), and is configured to bond the leads 9 of the film carrier 1 and the electrode pads 11 of the semiconductor chip 3 by thermocompression bonding.
このようなフィルムキャリア１への半導体チップ３の接
合は次のようにして行なう。The semiconductor chip 3 is bonded to the film carrier 1 in the following manner.
まず、フィルムキャリア１の孔部５と半導体チップ３と
の位置合わせを行なった後、ボンディングツール１９を
下降させる。このボンディングツール１９がリード９に
接触し、さらにボンディングツール１９が下降すること
により、リード９の先端部がフィルムキャリア１の厚さ
方向すなわち半導体チップ３側に変形する。First, after aligning the hole 5 of the film carrier 1 and the semiconductor chip 3, the bonding tool 19 is lowered. When this bonding tool 19 comes into contact with the lead 9 and further descends, the tip of the lead 9 is deformed in the thickness direction of the film carrier 1, that is, toward the semiconductor chip 3 side.
この結果、リード９の基部はフィルムキャリア１の一面
上にあるが、リード９の先端部は他面側に位置すること
になる。従って、フィルムキャリア１と半導体チップ３
とを接合させるとリード９は先端部のみが電極バッド１
１と接触し、先端部以外の部分である中間部は半導体チ
ップ３との間に隙間を有している。As a result, the base of the lead 9 is located on one side of the film carrier 1, but the tip of the lead 9 is located on the other side. Therefore, the film carrier 1 and the semiconductor chip 3
When these are joined, only the tip of the lead 9 is connected to the electrode pad 1.
1 and has a gap between the intermediate portion, which is a portion other than the tip portion, and the semiconductor chip 3 .
次に作用を説明する。Next, the effect will be explained.
上記構成において、フィルムキャリア１に半導体チップ
３を搭載すると、電極バッド１１にはリード９の先端部
のみが接触し、リード９の中間部と半導体チップ３のエ
ツジとの間には隙間が形成される。このため、第３図に
示すように半導体チップ３のエツジにリード９が接触す
ることを抑えることができ、エツジショートを抑えるこ
とができる。しかも、フィルムキャリア１のリード９と
半導体チップ３の電極バッド１１との接続時に同時にリ
ード９を変形させるので、作業工程を簡略化することが
でき工程管理が煩雑になるのを抑えることができると共
に、実装装置全体の小型化に寄与することができる。In the above configuration, when the semiconductor chip 3 is mounted on the film carrier 1, only the tips of the leads 9 come into contact with the electrode pads 11, and a gap is formed between the middle part of the leads 9 and the edge of the semiconductor chip 3. Ru. Therefore, as shown in FIG. 3, it is possible to prevent the leads 9 from coming into contact with the edges of the semiconductor chip 3, thereby suppressing edge shorts. Moreover, since the leads 9 are deformed at the same time when connecting the leads 9 of the film carrier 1 and the electrode pads 11 of the semiconductor chip 3, the work process can be simplified and process control can be prevented from becoming complicated. , it can contribute to downsizing of the entire mounting device.
なお、この発明は上記実施例のものに限定されず、例え
ばリード９の先端部を電極バッド１１との接続部とせず
に中間部を電極バッド１１との接続部としてもよい。こ
の場合、リード９の先端部は上方に反る形で半導体チッ
プ３との間に隙間を有することになる。Note that the present invention is not limited to the above-mentioned embodiment, and for example, the tip of the lead 9 may not be used as the connection part with the electrode pad 11, but the intermediate part may be used as the connection part with the electrode pad 11. In this case, the leading ends of the leads 9 are curved upward and have a gap between them and the semiconductor chip 3.
また、第４図および第５図に示すようにテーブル１３上
に半導体チップ３を載置せずにバンブ２１を設け、ボン
ディングツール１９の下降によりＢ−ＴＡＢとしてリー
ド９にバンブ２１を転写することができる。Alternatively, as shown in FIGS. 4 and 5, bumps 21 may be provided on the table 13 without placing the semiconductor chip 3 thereon, and the bumps 21 may be transferred to the leads 9 as B-TAB by lowering the bonding tool 19. Can be done.
さらに、リード９が変形するときのピッチ方向への移動
を抑え隣合うリード９が接触するのを抑えるために、例
えばリード９の厚さを先端部に近づくにつれて薄くなる
ように構成してもよく、同様の目的でリード９の曲げ部
分にリード９の長さ方向と直行する方向に溝を形成して
もよい。また、変形後のリード９長を確保するために予
めリード９を長めに設定してもよく、ステージ１３に対
しフィルムキャリア１を高めに設定してもよい。さらに
また、ステージ１３上に半導体チップ３の外周に位置し
半導体チップ３により若干高い案内壁を設けてもよい。Further, in order to suppress movement in the pitch direction when the leads 9 are deformed and to prevent adjacent leads 9 from coming into contact with each other, the thickness of the leads 9 may be configured to become thinner toward the tip, for example. For the same purpose, a groove may be formed in the bent portion of the lead 9 in a direction perpendicular to the length direction of the lead 9. Further, in order to ensure the length of the leads 9 after deformation, the leads 9 may be set longer in advance, and the film carrier 1 may be set higher than the stage 13. Furthermore, a guide wall may be provided on the stage 13, which is located around the outer periphery of the semiconductor chip 3 and is slightly higher than the semiconductor chip 3.
［発明の効果］
以上説明したようにこの発明によれば、電極バッドとの
接続部が半導体チップ側に位置するようにリードを変形
したため１、半導体チップを接合するときに傾き等が生
じても、リードの電極バッドとの接続部以外の部分と半
導体チップのエツジとの間には隙間があり両者が接触す
るのを抑えることができ、エツジショートを抑制するこ
とができる。[Effects of the Invention] As explained above, according to the present invention, since the lead is deformed so that the connection part with the electrode pad is located on the semiconductor chip side, 1. Even if the semiconductor chip is tilted when bonding, There is a gap between the edge of the semiconductor chip and the portion of the lead other than the connection portion with the electrode pad, so that contact between the two can be suppressed, and edge shorting can be suppressed.
しかも、電極バッドとリードとの接続と同時にリードの
電極バッドとの接続部が半導体チップ側に位置するよう
に変形させるので、作業工程を簡略化することができ工
程管理が煩雑になるのを抑えることができると共に、実
装装置全体の小型化に寄与することができる。Moreover, at the same time as the electrode pad is connected to the lead, the connection part of the lead to the electrode pad is deformed so that it is located on the semiconductor chip side, which simplifies the work process and prevents process management from becoming complicated. In addition, it is possible to contribute to miniaturization of the entire mounting apparatus.
第１図および第２図はこの発明の一実施例に係わる半導
体チップの実装法を示す図、第３図は同作用説明図、第
４図および第５図は応用例を示す図、第６図および第７
図は従来例を示す図、第８図は同作用説明図である。
１・・・フィルムキャリア
３・・・半導体チップ
５・・・孔部
９・・・リード
１１・・・電極パッド1 and 2 are diagrams showing a semiconductor chip mounting method according to an embodiment of the present invention, FIG. 3 is a diagram explaining the same operation, FIGS. 4 and 5 are diagrams showing an application example, and FIG. Figure and 7th
The figure shows a conventional example, and FIG. 8 is an explanatory diagram of the same operation. 1... Film carrier 3... Semiconductor chip 5... Hole 9... Lead 11... Electrode pad
Claims (3)
プを搭載し、この半導体チップに配設された複数の電極
パッドと、前記フィルムキャリアに設けられ先端部が前
記孔部に臨む複数のリードとを接続する半導体チップの
実装法において、前記電極パッドとリードとの接続時に
前記リードを前記電極パッドとの接続部が前記半導体チ
ップ側に位置するように変形させる半導体チップの実装
法。(1) A semiconductor chip is mounted in a hole formed in a film carrier, and a plurality of electrode pads are arranged on the semiconductor chip, and a plurality of leads are provided in the film carrier and whose tips face the hole. 1. A semiconductor chip mounting method for connecting a semiconductor chip, wherein the lead is deformed so that the connection part with the electrode pad is located on the semiconductor chip side when the electrode pad and the lead are connected.
を接続させるボンディングツールにより行なうことを特
徴とする特許請求の範囲第１項記載の半導体チップの実
装法(2) The semiconductor chip mounting method according to claim 1, wherein the deformation of the leads is performed using a bonding tool that connects the electrode pads and the leads.
フィルムキャリアの孔部に臨む先端部であることを特徴
とする特許請求の範囲第１項記載の半導体チップの実装
法(3) The method for mounting a semiconductor chip according to claim 1, wherein a contact portion of the lead with the electrode pad is a tip portion facing a hole of the film carrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61230109A JPS6386443A (en) | 1986-09-30 | 1986-09-30 | Mounting of semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61230109A JPS6386443A (en) | 1986-09-30 | 1986-09-30 | Mounting of semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6386443A true JPS6386443A (en) | 1988-04-16 |
Family
ID=16902700
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61230109A Pending JPS6386443A (en) | 1986-09-30 | 1986-09-30 | Mounting of semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6386443A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5686352A (en) * | 1993-07-26 | 1997-11-11 | Motorola Inc. | Method for making a tab semiconductor device with self-aligning cavity and intrinsic standoff |
-
1986
- 1986-09-30 JP JP61230109A patent/JPS6386443A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5686352A (en) * | 1993-07-26 | 1997-11-11 | Motorola Inc. | Method for making a tab semiconductor device with self-aligning cavity and intrinsic standoff |
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