JPS6386334A - Received frequency tracking device of receiver for spread spectrum communication - Google Patents

Abstract

PURPOSE:To improve frequency tracking accuracy by a method wherein a means for oscillating an electric signal of set frequency and a frequency mixing means for mixing a received spread spectrum signal with an electric signal of an oscillation means and generating a spread spectrum signal of a low frequency are provided and oscillation frequency is adjusted after synchronous lead-in is completed. CONSTITUTION:A transceiver system in spread spectrum communication for performing communication with a moving satellite is constituted as follows; that is, correlation circuits on the upper stage are composed of a balancing mixer 2a serving as a first reverse-spreading (i.e., compressing) means, a band filter 3a serving as the first signal extraction means, an amplification circuit 4a, a detection circuit 6a and a low-pass filter 9a etc., for generating correlation output 1. Further, parallely connected delay lock group circuits on the middle stage are also almost similarly constituted for generat ing correlation output 2 through a differential amplification circuit 8 serving as a synthesis means and PN code generation circuits on the lower stage are composed of VCO 12 serving as an energizing means and a PN code generator 13 serving as a false noise generation phase-shifting means. In this way, a reverse-spreading signal due to an envelope-detected reference phase is controlled to the maximum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a reception device for spread spectrum communication, and particularly to tracking of reception frequencies.

(Prior art) Spread spectrum communication (hereinafter referred to as SS communication: Sp
read Spectrum System) is a pseudo noise signal (hereinafter referred to as PN code) of a code sequence determined in advance between transmitting and receiving data.
This is a communication method in which the signal is spread and transmitted using a PN code, and the receiver despreads the signal using a PN code string of the same code sequence.

Here, to briefly explain the code synchronization performed on the receiver side, 1. For example, the first
a correlation circuit, a second correlation circuit that performs despreading with a PN code string that is 172 bits behind the reference phase, a third correlation circuit that performs despreading with a PN code string that is 1/2 bit ahead of the reference phase; It has a synthesis circuit that differentially synthesizes the outputs of the circuit and the third correlation circuit, and first, in initial acquisition, it generates a PN code string at a faster bit rate than the sending side, despreads the received signal, and performs correlation. When the first correlator detects the peak of
Synchronization is performed by adjusting the bit rate so that the output of the synthesis circuit is 0.

This communication method can extract a large amount of energy only when there is a correlation between the code strings between the transmitter and the receiver, so it is resistant to noise and is widely used, for example, in satellite communications that communicate using weak radio waves.

(Problems to be Solved by the Invention) For example, when communicating with a mobile satellite, the frequency of a received signal deviates from the transmission frequency due to Doppler shift. S.S.
In communication, since the communication system is deterministic, a certain degree of Doppler correction is possible, but this shift amount constantly changes.

Conventionally, there is a means to track fluctuating frequencies called an AFC circuit, but in SS communications, in many cases,
Since the signal does not contain a carrier component, this type of AF
Frequency tracking using C circuits is difficult. For this reason,
Conventionally, frequency tracking had to be performed in conjunction with a despreading circuit and a demodulator, which was very complicated.

The present invention provides a reception device for spread spectrum communication, comprising:
The purpose is to track the received frequency with a simple configuration.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention includes an oscillating means for oscillating an electrical signal of a set frequency, and a received spread spectrum signal and an electrical signal oscillated by the oscillating means. frequency mixing means to produce a low frequency spread spectrum signal.

After the synchronization is completed, the oscillation frequency of the five oscillation means is adjusted to maximize the envelope-detected despread signal based on the reference phase.

(Function) The signal obtained by envelope detection of the despread signal using the reference phase when code synchronization is established is the reception level, so by adjusting the oscillation frequency of the oscillation means to maximize this. , it becomes possible for the receiving device to follow the receiving frequency.

Since this only involves comparing the levels and adjusting the oscillation frequency, it can be easily digitized and the receiving device can be miniaturized. Moreover, by making this adjustment period faster and adjusting in small steps, the accuracy of tracking one frequency can be made sufficiently high.

In addition, when an AGC circuit (automatic gain adjustment circuit) is included in the circuit, the oscillation frequency may be adjusted by comparing the levels after fixing the gain.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

(Example) First, the outline of the apparatus of this example will be explained. See Figure 2g. Figure 2g shows SS communication (SpreadSpe
1 is a block diagram schematically showing a transmission/reception system in spread spectrum communication).

The transmitter Trn converts the transmission data into a PN code (P5eudo Noi) with a higher bit rate.
saCode (pseudo noise code), and the spread signal spreads BPSK (Biphase code) on the carrier wave.
Phase Shift Kaying)
Transmit via a tuned circuit. Note that the transmission data of this embodiment includes information indicating a transmission position.

In the receiver Rec, the high frequency signal obtained through the tuning circuit is mixed with the single station oscillation signal, then despread by adding the same PN code as the transmission, and the despread signal is demodulated in the BPSK demodulation circuit. Get received data.

This embodiment relates to the receiver R8e.

This is a signal that spreads 50 b/s (bits per second) transmission data with a 1.023 Mb/s PN code.
Receive radio waves with BPSK applied to a 75 MHz carrier wave.

1a, 1b, 1C, and 1d are circuit diagrams showing the detailed configuration of a part of the device of this embodiment, and the second
FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D are block diagrams showing the schematic configuration of the apparatus of this embodiment. Please refer to these drawings.

a. (Generation of Intermediate Frequency Signal) First, referring to FIG. is mixed with the first local oscillator signal, and the first
It becomes an intermediate frequency signal.

TxC0103 is a temperature compensated crystal oscillator that oscillates a 10MHz signal. In other words, the first
The local oscillator signal is obtained by converting this signal into a 152 multiplier lO5.
It is a signal of 1520 MHz which is doubled, and the first intermediate frequency signal considering Doppler shift etc. is 55.42 MHz ±
It becomes a 5kHz signal. The first intermediate frequency signal is passed through the bandpass filter 107 . After being filtered and amplified in the first intermediate frequency amplifier 108 and the bandpass filter 109, the signal is mixed with the second local oscillation signal to become a second intermediate frequency signal.

SYN is a synthesizer that oscillates a second local oscillator signal, and functions as a second local oscillator. In this case, the 10 MHz signal of the TCXO 103 output given via the buffer 104 is multiplied by 4 to 40 MHz by the quadrupler 113.
) lz) , 1/2 times 5 with the 1/2 multiplier 114
MHz), and these are combined to generate a first signal of 45 MHz. On the other hand, the output of the 1/2 multiplier 114 (5MHz
) is further 1/2 multiplier 115 and 1/25000
It is multiplied by 1150000 in the multiplier 116 and becomes 100H.
This becomes the second signal of z.

44. Considering the case where the VC0122 outputs the second local oscillation signal of 44.72 MHz and the 1/N multiplier 119 is set to 1/2800, the first signal of 45 MHz and the first signal of 45 MHz. 72M)lz and the second local oscillator signal, and the lower signal (
280kHz) and multiplier 119 converts the frequency to 1/
The signal multiplied by 2800 is.

It becomes 100Hz. This signal and the second signal (100
)1z) are mixed, filtered by a low-pass filter 120, and DC amplified by an amplifier 121, resulting in a voltage signal V C01
22. That is, by changing the multiplication rate of the 1/N multiplier 119, the voltage signal applied to the VCO 122 changes.

VC0122 outputs a second local oscillation signal of 44.72M)lz±5kHz based on the deviation of the input voltage signal around Ov. The oscillation frequency control of the second local oscillation signal is performed by the 1/N multiplier 119 in the Doppler correction processing described later.
This is done by setting a multiplication rate of .

In the mixer MIX, the first intermediate frequency signal is 55.42MH
z±5kHz, so this and 44.72MHz±5
A 10.7 MHz second intermediate frequency signal is obtained by mixing the kHz second local oscillator signal (symbols below assume that the deviation between the two is adjusted to be equal) and passing it through the low-pass filter 110. obtain. This second intermediate frequency signal is.

After level adjustment in the AGC amplifier 111, the signal is applied to the next-stage despreading circuit via the low-pass filter 112. The AGC amplifier 111 of this embodiment is an attenuator ATT composed of a diode as shown in FIG. 6a, and the forward resistance is reduced when the potential between the anode and cathode of the diode is large. AGCRI of this example
The IFM device 111 is an attenuator ATT composed of a diode as shown in FIG. 6a.
This utilizes the property that when the anode-cathode potential is large, the forward resistance becomes small, and conversely, when it is small, it becomes large. Figure 6b shows the relationship between the voltage applied to the anode of the diode, that is, AG (1! voltage), and the forward resistance of the diode, that is, the amount of attenuation of the attenuator ATT. Level adjustment is performed using the characteristic of the linearly decreasing portion. Note that the AGC"11 pressure is set by a microcomputer 10, which will be described later.

b. (Despreading) Figures 1a and 1b show details of the despreading circuit of the embodiment device, and Figure 2b is a block diagram showing its schematic configuration. The circuit consists of the correlation circuit in the upper stage, the delay lock loop circuit (hereinafter referred to as DLL circuit) in the center, the PNN code generator in the lower stage (same for 2b and 2c), and the narrowband filter 3a (same as for 2b and 2c) shown in Fig. 1a or 2b. In this example, a crystal filter 10F15C) manufactured by NDK is used: 3b, 3
The same goes for c).

Amplifying circuit 4a, distributor 5 (in this example, 2 manufactured by RaK)
(using a distributor PD-2), a detection circuit 5a, a buffer amplifier 7, and a low-pass filter 9a.

The DLL circuit includes a balanced mixer 2b, a narrowband filter 3b,
A first correlation circuit consisting of an amplifier circuit 4b and a detection circuit 6b, a balanced mixer 2c, a narrowband filter 3c, and an amplifier circuit 4c
and a second correlation circuit consisting of a detection circuit 6C, a differential amplifier circuit 8, and a low-pass filter 9b.

The code generation circuit consists of vC○12 and PN code generator (P
PN code G
enerator) Consists of 13.

The control circuit is a microcomputer 10 (in this example, a Hitachi microcomputer HD 63705Z
It is mainly composed of a D/A converter 11a and 11b (in this embodiment, a D/A converter DA C0800 manufactured by Analog Devices Co., Ltd. is used).

10.7M1 (z second intermediate frequency signal (denoted as IF)
D-4) 1 allows three balanced mixers 2
Evenly distributed among a, 2b and 2c. Balanced mixer 2
The reference phase PN code string from the PN code generator 13 is shown in a.
The balanced mixer 2b is supplied with a PN code string whose phase is shifted by +1/2 bits from the reference phase, and the balanced mixer 2c is supplied with a PN code string whose phase is shifted by -172 bits from the reference phase.

The PN code generator 13 will be described later, but the PN code string used in this embodiment is a 1023-bit gold code string, and this PN code string is used for transmission. equal to what is there. Therefore, when the PN code string generated by the PN code generator 13 and the PN code string included in the received signal are synchronized, the outputs of the balanced mixers 2a, 2b, and 2c become the second intermediate frequency signal of 10.7 MHz. The energy is concentrated by being compressed (despread) around the . At this time, uncorrelated signals, such as interference waves.

Conversely, noise etc. is spread by this PN code, so 1
a narrowband filter 3a with a center frequency of 0.7MHz;
In 3b and 3c, only signals containing transmitted data can be extracted.

Code synchronization will be explained below.

Since the PN code string generated by the PN code generator 13 and the PN code string included in the received signal are equal, even if the PN code generator 13 is started from an arbitrary starting position, the generated PN code string can be converted into one bit. By sequentially shifting the bits by 1023 bits, there will always be a frame in which all bits have the same sign until the 1023 bits have been shifted. Code synchronization is performed by detecting this and eliminating the shift in the code string from that point.

To explain more specifically, the PN code generator 13 is configured as follows: 1.
By turning on the bit rate to 0.024Mb.

Each time the generated code string is in sequence, a one-bit shift occurs with respect to the PN code string included in the received signal. The PN code string generated by the PN code generator 13 is transmitted to the balanced mixers 2a and 2b.
and 2c, so if there is a frame in which all bits match, each output will be compressed around 10.7MHz as described above, but
If even a bit is off, the energy will be diffused and not concentrated.

Therefore, by envelope-detecting the output of the narrowband filter 3a in the detector 6a and filtering it in the low-pass filter 9a, a peak appears when the signs match at the output end A, and a deviation of 1 bit causes a noise level. A correlation output 1 appears that drops to .

Waveform A shown in FIG. 3a shows this correlation output 1. In this case, the period T is further shifted by 1023 bits,
This is the time it takes for the correlation to be established again.

Therefore, the correlation output 1 is monitored, and when the level exceeds the threshold level THI, temporary synchronization is established and the bit rate of the PN code generator 13 is set to 1.023 Mb/s (initial acquisition). In other words, the deviation of the PN code generator 13 is eliminated when both code strings match.

On the other hand, the balanced mixer 2b has P applied to the balanced mixer 2a.
Since a code string advanced by 172 bits is given to the N code string, similarly to the above, in the first correlation circuit of the DLL circuit, the left side of the waveform A as shown in waveform B shown in FIG. An output represented by a correlation waveform shifted by 172 bits (advanced by 172 bits in time) is obtained, and the balanced mixer 2c receives a code string delayed by 172 bits with respect to the PN code string applied to the balanced mixer 2a. is given, so
Similarly to the above, in the second correlation circuit of the DLL circuit, the waveform A is shifted by 172 bits to the right (delayed by 1/2 bit in time) as shown in the waveform C shown in FIG. An output represented by a correlated waveform is obtained.

These outputs are combined in the differential amplifier circuit 8, and the DLL circuit eventually obtains a correlation output 2 having the waveform shown in FIG. 3a.

Referring to FIG. 3a, in the temporary synchronization, the correlation output 2 is a
It changes between l and a2. By adjusting the bit rate of the PN code generator 13 (output frequency of the VCO 12) so that this output becomes O, code synchronization is completed.

This 5I adjustment is, for example, in Figure 3b, the correlation output 2
When the level of is a, increase the output frequency of the VCO,
In case b, the output frequency of VCO is lowered, and since the correlation output 2 cannot actually be O, the level is always controlled to be within the range of ±ε0 (synchronization maintained).

The signal despread by the balanced mixer 2a is not only used for the above-mentioned initial acquisition, but also distributed by the distributor 5 and given to the next-stage Costas loop demodulation circuit. (It is more correct to think that initial acquisition is performed by monitoring the energy distribution of the signal given to the Costas loop demodulation circuit) When the pull-in of 6-code synchronization is completed, the signal given to the Costas loop demodulation circuit is It becomes a modulated wave of 10.7 MHz (BPSKed using 50 b/s data).

Microcomputer (hereinafter referred to as CPU) 10 analog input ports ANO are connected to low-pass filter 9a, ANI
are connected to the low-pass filter 9b, respectively, and the output port A □ -A 7 is connected to the D/A converter lla,
Output port BoNB7 is synthesizer SYN (2nd a
The output port co”cs is D
/A converter llb, respectively.

The D/A converter lla is 8 given by the CPUl0.
A voltage signal (CO control voltage) corresponding to bit digital data is generated and applied to the VCO 12.

D/A converter llb is 7 given by CPU10.
A voltage signal (AGC voltage) corresponding to bit digital data is generated and applied to the AGC amplifier 111.

The operation of CPU10 will be described later, but only briefly.

First, while monitoring the ANO and ANI inputs.

After adjusting the VC○ control voltage and controlling the above-mentioned initial acquisition and synchronization maintenance, the AGC voltage is adjusted and the A
Control the NO input to a predetermined value (TH2).

Thereafter, Doppler correction is performed to maximize the ANO input by controlling the SYN oscillation frequency, and the system initialization is completed. After that, control related to AGC adjustment and synchronization maintenance is repeated, and Doppler correction is performed at a predetermined period. In this repeated control, if synchronization maintenance becomes difficult and the out-of-synchronization state continues for a predetermined period of time, control related to initial acquisition is performed. After resynchronizing, the above repetitive control is performed again.

c. <Demodulation> FIG. 1c shows details of a Costas loop demodulation circuit that performs demodulation, and FIG. 2c is a block diagram showing its schematic configuration. Please refer to these drawings.

A modulated wave of 10.7M)lz that has been baseband modulated (BPSKed using data sent to 50b) is input from the distributor 5 of the despreading circuit to the Costas loop demodulation circuit. This input is connected to a balanced mixer (in this example, a double balanced mixer M-8 manufactured by RaK is used) 14
It is equally distributed between a and 14b.

On the other hand, VCO23 outputs a 10.7M)lz(7) demodulated signal.

The signal is supplied to a phase shifter 25 (in this embodiment, a hybrid divider PDQ3 manufactured by RaK Corporation is used) via an amplifier 24. Phase shifter 25 distributes the demodulated signal with a phase difference of 90° and applies it to balanced mixers 14a and 14b.

The outputs of balanced mixers 14a and 14b are filtered by low-pass filters 15a and 15b, respectively, and are filtered by amplifier 16a.
and 16b, and then multiplied by a 1 multiplier 20 (in this embodiment, a multiplier AD533 manufactured by Analog Devices Co., Ltd. is used). The output of the multiplier 20 is substantially converted into a DC signal in the loop filter 21, passes through the limiter 22, and becomes a control voltage signal for the VCO 23.

A more detailed operation of the Costas loop demodulation circuit will be described below.

The baseband modulated wave of the input signal.

+A cos(ωt+ $) and VCO23 is coS
If the phase shifter 25 outputs a signal COSωt to the balanced mixer 14a, and a signal sinωt to the balanced mixer 14b. therefore.

The output of the balanced mixer 14a is ±A/2 (cosφ+GO3(2(11t+φ))
-...(1), and the output of the balanced mixer 14a is.

±A/2 (sinφ15in (2c, ++φ))
...(2).

When the output of the balanced mixer 14a is filtered by the low-pass filter 15a, it becomes ±A/2 cosφ, and when the output of the balanced mixer 14b is filtered by the low-pass filter 15b, it becomes ±A/2 sinφ.

These two signals contain information about the transmitted data (BP
SK information) and the carrier phase, but the multiplier 2
By multiplying by 0, as its output, A”
/25in2φ is extracted, resulting in a signal containing only the carrier phase. This signal is passed through a loop filter to vC
0, so that the VCO tracks the input carrier (the assumed carrier, since the input does not actually include a carrier).

In other words, in the Costas loop demodulation circuit, the phase difference φ
is set to 0.

Now, let's focus on the output of the low-pass filter 15a.

When the phase difference φ is O (when the Costas loop demodulation circuit is locked), this output is, using the above symbol,
±A/2, resulting in a signal containing only BPSK information (transmitted data to 50b). Therefore, this is extracted via a block 17 consisting of a voltage follower buffer and a low-pass filter, and after level adjustment is performed by a limiter 18, a TT signal is input to a binarization circuit 19.
Binarization is performed at the L level and BPSK information is extracted.

However, this data is not only extracted when the Costas loop demodulation circuit is locked.

This is obvious from the circuit shown in Figure 1c. In other words, it is necessary to determine whether the Costas loop demodulation circuit is locked or unlocked.

Therefore, if we pay attention to the output of the low-pass filter 15b, when the Costas loop demodulation circuit is locked, that is, when the phase difference φ is 0, this output becomes 0, and when φ is O
If it deviates from (unlocked), depending on the value, ±A/2
sinφ is output (using the symbol above)
The waveform of the signal detected at point E in FIG. 1c is shown as E in FIG. 7, where one section e2 is the output when unlocked, and one section e3 is the output when locked. Therefore, when this output signal is full-wave rectified in the full-wave rectifier 26, the F
A signal as shown in (signal at point F in Fig. 10) is obtained.

This is inverted to TTL level in the binarization circuit 27.
The value converted is the signal shown by G in FIG. 7 (signal at point G in FIG. 1C).

It has been found that by monitoring the level of signal G, it is possible to determine whether the Costas loop demodulation circuit is locked or unlocked, but this determination is not perfect; in other words, the despreading circuit (Figure 1a) In this case, since the input of the Costas loop demodulation circuit is almost at the noise level, the amplitude of the output signal of the low-pass filter 15b is very small, and the signal G is at H level (section el). Therefore,
Unless the case in section 81 is discriminated, the determination will not be complete.

Therefore, in the present embodiment, the correlation output 1 of the despreading circuit is used for this discrimination. The correlation output 1 becomes a large value due to concentration of energy when the despreading circuit is synchronized as described above. Therefore, when this correlation output 1 is compared with an appropriate threshold value in the comparator 29 and binarized,
A signal indicated by H in FIG. 7 (signal at point 1c@H) is obtained. By logically multiplying this signal H and the above signal G, a complete lock signal can be obtained. The output waveform of the AND gate 28 (signal at point I in FIG. 10) is indicated by I in FIG.

Incidentally, if we compare the detection of the conventional lock signal with reference to FIG. A signal was detected. This detection will be briefly explained using the above symbols.

In each multiplier, the input signal cos (ω + φ) is
VCO phase shifted +45″ or -45″ respectively
output, i.e. cos (ωt+45°), cos(ω
t-45') signal is multiplied, and ±A/2 (cos (-45°+φ) + cos (2ωt+45'+φ)]...
(3) ±A/2 (cos (+45”+φ) +cos (2ωt, -45”+φ)) ・−・−・
(4) becomes. When these output signals are filtered with low-pass filters and multiplied respectively, A' /4 [cos (0' + 2φ) + cos90
" ) ・"(5), and the lock signal is detected.

As is clear from a comparison between the present embodiment shown in Fig. 2c and the conventional example shown in Fig. 2e, the structure of this embodiment is extremely simple, and is different from that used conventionally. 4
Since there is no 5° phase shifter, there is also the advantage of high reliability at high frequencies.

The data demodulated by the Costas loop demodulation circuit and the detected lock signal are provided to a data processing circuit (not shown).

d, <PN code generation> FIG. 1d shows details of the PN code generator 13 of this embodiment, and FIG. 2d is a block diagram showing its schematic configuration. As described above, this PN code generator 13 generates the gold code string. Simply put, a gold code string is an m sequence (maximal 1inea) of two different code strings.
r codes: longest linear code string) between codes, 2
The 0m sequence, which is generated by the sum modulo , depends on the feedback connection method of the shift register, so it is not possible to obtain as many types of code strings, but the Gold code string, ie.

The sum modulo 2 of m-sequence code strings of different code strings,
In the case of smell, by performing a phase shift, it is possible to obtain Gold code strings that differ by the maximum number of bits (this number + 2 when the two basic m sequences are added).

In other words, in this embodiment, a code string with a length of 1023 bits is used, but when generating m sequences using a 10-stage shift register, only about 10 code strings can be obtained from the feedback connection method. , if Gold code strings are generated using two different m-sequence generators, 1023 Gold code strings can be obtained.

The device of this embodiment generates 45 Gold code strings assigned to the system among these 1023 Gold code strings.

Referring to FIG. 1d and FIG. 2d, the first code generation unit 30 is connected to the third stage and the tenth stage (from the left, the first stage, the second stage, the third stage, ...) of the 10-stage shift register. This is an m-sequence code generator in which the output ends of the 10-stage shift register (the same applies below), that is, the third tap and the 10th tap, are feedback-connected. This is an m-sequence code generator in which the 3rd tap, 6th tap, 8th tap, 9th tap, and 10th tap are connected in feedback.

The clock input terminals C of the shift registers constituting the first code generation section 30 and the second code generation section 32 are commonly
VCO12 via an inverter that functions as a buffer
-The clock from the VCO 12 is applied to the output terminal of the -VCO 12. Further, the six initial set circuits 33, whose reset terminals R are commonly connected to the initial set circuit 33, reset all shift registers in synchronization with the clock when the set signal SET is received.

Note that since the first code generation section 30 and the second code generation section 32 are configured with negative logic, the code shaping section 36. , 36-, and 36o to generate a gold code.6 By the way, since the m-sequence code string is closed in addition modulo 2, the m-series whose phase is shifted by an integer number of bits is different from the original m-series. Adding the m-sequence modulo 2 yields another phase-shifted sequence of the original m-sequence. The tap selection circuit 31 utilizes this.

The tap selection circuit 31 consists of two sets of selectors each consisting of 92 multiplexers (in this embodiment, AS 253 manufactured by TI is used), and the second code generation section 32
Select the specified two taps from the ten taps. In this, the output of the selected tap is sent to the second code synthesizer, ie.

The m-sequence code strings are synthesized (exclusively ORed) in an exclusive-OR gate 34 and subjected to a predetermined phase shift.

The output (m sequence) of the second code synthesis unit is output from the first code synthesis unit,
That is, in the exclusive OR gate 35, it is combined (exclusively ORed) with the output (m sequences) of the first code generation section 31 to generate a gold code string (correctly, an inverted gold code string).

At this time, since the output of the second code synthesis section is accompanied by a delay due to a gate in the middle, a hazard occurs in this gold code string. Therefore, the code shaping units 36+, 36
- and 36o, sign shaping is performed.

Code shaping section 36. , 36- and 36o consist of three D flip-flops. Since 36 and 36- are connected in series and the same clock is applied to each clock terminal C, the 36- output has a one-bit phase lag with respect to the 36 and output.

However, although 36o is connected in series with 36, the clock is inverted and applied to its clock terminal C, so its output has a phase delay of 172 bits with respect to the 36° output. These code shaping units 36+, 36
- and 36o outputs are the inverting output terminals of their respective D flip-flops (shown overlined in Figure 1d).
extracted from.

A tap selection signal specifying one selected tap of the tap selection circuit 31 is given by turning on and off the dip switches 81 to S8.

Table 1 below shows the relationship between the tap selection signal 2 selection taps and the number of bits to be phase shifted.

Table 1 (Part 1) Table 1 (Part 2) However, in Table 1, it 1 n
In the figure, a switch-off is indicated as "0", and a one phase shift is indicated as a delay with respect to the original m sequence (that is, the 10th tap output of the second code generator 32).

Incidentally, when compared with the conventional Gold code generator with reference to Fig. 2f, the conventional example shown in Fig. 2f seems to have a simple configuration; Since the phase shift with respect to the code generating section is provided as first start position data and second start position data, respectively, the number of constituent elements and the number of signal lines are significantly larger than in this embodiment. This corresponds to the first
It may be considered that each shift register of the code generation section 30 and the second code generation section 32 is set/reset one by one. That is, since an initial set circuit is required for each element constituting each shift register, the number of constituent elements and signal lines of the PN code generation circuit becomes extremely large.

e. <Operation> FIGS. 8, 9, 10, 11, 12, and 13 are flowcharts showing an outline of the operation of the CPU10 of the device of this embodiment. With reference to these drawings, CP
The operation of Ul0 will be explained.

First, we will explain the meanings of the main symbols.

Fl is a flag indicating completion of initial acquisition, F2 is a flag indicating completion of synchronization pull-in, and F3 is a flag indicating an increase in the step-down value in Doppler correction.

CN is a counter for measuring out-of-synchronization time.

G is a register that stores data corresponding to the AGC voltage, N is a register that stores data corresponding to the Doppler correction value, and Y is a register that stores data corresponding to the control voltage applied to the VCO 12.

Referring to FIG. 8, when the power is turned on, each memory
Initialize registers and input/output ports and disable interrupts.

Next, flag F1 and flag F2 are reset (0), counter CN is cleared (0), and registers G, N,
Y has initial values Go and No, respectively.

Load YO, and output ports hBo""B from output ports CO to C6 to D/A converter llb.
7 to the 1/N multiplier 119 of the synthesizer SYN shown in FIG. 2a, or output from the output port AO-A7 to the D/A converter lla. These initial values, namely, G.

is the value corresponding to the median value of the linearly decreasing portion of the graph shown in FIG. 6b, and No is the value corresponding to the multiplication rate of the 1/N multiplier 119 of the synthesizer SYN shown in FIG. 2a by 1/2.
800, and YO is a value that sets the oscillation frequency of the VCO 12 shown in FIG. 1a to 1.024 MHz.

The oscillation frequency of the VCO 12 is set to 1.024MHz, and the code string included in the received signal is
Since the bits are shifted, as mentioned above,
While this shift is in order of 1 (during a shift of 1023 bits)
, the correlation peak shown in FIG. 3A appears in the correlation output 1 shown in FIG. 1A. Therefore, the initial acquisition process is repeated in loop processing to detect this peak.

The initial acquisition process will be explained with reference to FIG. In this, the analog port ANO input, ie the correlation output 1 shown in FIG. 1a, is read and loaded into register DO. Compare the value of the register DO with the threshold THI, and if it is less than THI, return as is, and if it is TH
Immediately after exceeding I, the oscillation frequency of VCO12 is changed to 1.02.
Load the value Y1 to be set to 3MHz into register Y,
Set the F1 flag (1) and return. Immediately after the main routine returns, the value of this register Y is output to port A. - Since the output is from A7 to the D/A converter lla, the oscillation frequency of VCO12 is 1.023
MHz, and the temporary synchronization is completed.

In the initial acquisition process, the flag F1 indicating completion is set, so the synchronization maintenance process is executed in a similar loop process.

The synchronization maintenance process will be explained with reference to FIG.

Note that the process up to the completion of synchronization pull-in will be described here, and the explanation regarding the loss of synchronization will be described later.

Read the analog port ANO input again and set the threshold value THI.
Compare with. This is to check whether temporary synchronization has been lost.

In the state of temporary synchronization, the analog port ANI input, ie, the correlation output 2 shown in FIG. 1a, is at a level between al and a2 of the waveform diagram shown in FIG. 3a. First, consider the case where this level is outside the range of ±εa (a value near O) as shown in Figure 3b (actually, when synchronization is achieved or during temporary synchronization, the correlation output 2 is Although the waveform is not as shown in Figure 3a or Figure 3b, this waveform diagram will be used for the convenience of the following explanation).

The AN1 input is read at different times, and the value read earlier is loaded into register Dla, and the value read later is loaded into register Dlb.

When the value of the register Dla is positive, that is, when it corresponds to point a shown in Figure 3b, if the value read later, that is, the value of the register Dlb, is smaller, the synchronization is pulled in and remains at 9, so it remains as it is. Return. At this time, if the value read later, that is, the value in register Dlb, is larger, it means that the synchronization has started to slip, so the value in register Y is increased by 2ΔY and the process returns. The value of register Y is output port A O-A
Since it outputs from 7 to D/A converter lla,
The oscillation frequency of vC○12 becomes slightly higher. For convenience, this will be explained using the waveform diagram in Figure 3b.

As the oscillation frequency of 12 becomes higher, this waveform shifts to the left. Therefore, the ANI input will be low.

When the value of register Dla is negative, that is, when it corresponds to point b shown in Figure 3b, if the value read later, that is, the value of register Dlb, is larger, it means that the synchronization has been pulled in, so continue as is. Return. At this time, if the value read later, that is, the value of the register Dlb, is smaller, it means that the synchronization has shifted to the side where the synchronization is lost, so the value of the register Y is lowered by 2ΔY and the process returns. The value of register Y is output port A. - Since the output is from A7 to the D/A converter lla, the VC
The oscillation frequency of O12 becomes slightly lower. For convenience, this will be explained using the waveform diagram in FIG. 3b. As the oscillation frequency of the VCO 12 becomes lower, this waveform shifts to the right.

Therefore, the ANI input goes high.

By repeating the above in a loop process, synchronization is pulled in and when the ANI input falls within the range of ±ε0, F2
Set the flag (1). The following is the same as above except that the step of updating the oscillation frequency of vC○12 is ΔY, so the explanation will be omitted.

After setting the F2 flag and returning to the main routine, AGC adjustment processing is performed.

The AGC adjustment process will be explained with reference to FIG.

In this case, first, the level of the analog port ANO input, that is, the correlation output 1, is read and loaded into the register DO. The value of DO is a predetermined value TH2±ε2 (
(nearby value), the AGC voltage is changed.

In other words, when the value of DO is smaller than TH2, the AGC
Since the attenuation factor of amplifier 111 (Fig. 2a) is too large,
The value of register G is updated to be higher by ΔG to raise the AGC voltage, and when the value of DO is larger than TH2, the attenuation factor of the AGC amplifier 111 is too small, so the value of register G is updated to be lower by ΔG to raise the AGC voltage. Lower it.

The above process is repeated in a loop, and the value of Do is set to a predetermined value T.
When a value near H2 (in the range of ±ε2) is reached, a reception level calculation (described later) is performed and the process returns to the main routine.

In the main routine, Doppler correction processing is then executed. Correlation output 1 when synchronization is established or during temporary synchronization differs from the waveform shown in Figure 4, but if this waveform diagram is used for convenience of explanation, the transmission frequency may deviate from the set value due to the Doppler effect, etc. , the correlation output 1 will be at the position C or d in Figure 4, which will naturally be lower than the possible value that can be obtained, that is, the apex. to correct. This is Doppler correction processing.

The Doppler correction process will be explained with reference to FIG. In this case, first clear the flag F3, read the level of the analog port ANO input, that is, the correlation output 1, and input it to the register D.

Load into a.

If the value of register N is less than Nmax, that is, 2850, the value of N is incremented by 1 and output.

After this, the value of register DOa is bushed into the DOb register, the analog port ANO input is read again, and it is loaded into register DOa.

At this time, the value of register DOa is the level of correlation output 1 after the change, and the value of register DOb is the level of correlation output 1 before the change, so by comparing the two, it is possible to determine whether the level increases or decreases due to this change. Can be done.

If it is an increase, flag F3 is set (1) and the above steps are repeated. By repeating this, when the level of correlation output 1 decreases beyond the peak, register D.

The value of a becomes smaller than the value of register DOb. In that case, since flag F3 is set, the value of register N is decremented by 1 and output.

In the same way as above, determine whether the level of correlation output 1 increases or decreases due to the change, if it increases, it is determined to be the optimal value and returns as is; if it decreases, the optimal value is registered as the value before this change. Return N to its original value, output it, and return to the main routine.

Initially, as a result of incrementing register N by 1 and outputting it, if the level of correlation output 1 decreases, flag F3 is
remains reset (o), so a loop process is executed to search for the optimal value of register N while sequentially decrementing the value of register N. Since this is a repetition of the above, the explanation will be omitted.

Since the system initialization of the device of this embodiment has been completed above, in the main routine, interrupts are enabled and a constant operation loop is set. In this loop, the AGC adjustment processing and synchronization processing described above are repeatedly executed, and when there is an out-of-synchronization, the initial acquisition processing is executed, and when an interrupt request is made at a predetermined period by the internal timer, Doppler correction processing is executed (see Fig. 11). reference).

Explain about synchronization loss. Please refer to FIG. 10 again.

Consider the case where the ANO input, that is, the correlation output 1, decreases after the synchronization pull-in is completed.

If this gradually decreases, the above pull-in order will be reversed, and first the ANI input (correlation output 2) will deviate from the value near 0, so flag F2 will be reset, and then the ANI input
When the input decreases to below the threshold THI, the flag F2 is reset, so the flag F1 is reset, the register Y is set to YO (initial value: 1.024 MHz compatible), and the process returns.

When returning to the main routine, first, the value of register Y is output to change the oscillation frequency of VCO 12, and then, since flag F1 has been set, initial capture processing is executed by loop processing. The following is the same as above.

For example, when the antenna is temporarily shielded (such a situation can often be expected when the device of this embodiment is installed in a car, due to being behind a building or passing through a tunnel), the correlation output 1 will suddenly decrease. In this case, since the flag F2 remains set, time measurement is started by the counter CN. If synchronization is restored before the counter CN exceeds the predetermined value CNmax.

The process returns to the loop process of maintaining synchronization, but when the predetermined value CNmax is exceeded, the flag Fl, the F2° counter CN, and the register Y are initialized and an initial acquisition process is executed. The following is the same as above.

Generally speaking, if the antenna is temporarily blocked, the synchronization will not be significantly lost, so if the antenna is out of synchronization for a short period of time, if the antenna is kept open, it will be fixed when the antenna returns to normal. Communication can often be resumed immediately. In other words, initial acquisition processing is performed each time a synchronization is lost for a short period of time to prevent communication from being cut off for a long period of time.

Finally, the reception level calculation process, which was omitted in the above description of the AGC adjustment process, will be described.

In this embodiment, a circularly polarized microstrip antenna is used as the receiving antenna Ant.
When fixed to the roof of a vehicle, the output level of Ant fluctuates depending on the attitude (orientation) of the vehicle, regardless of the electric field strength at the reception point, since the unidirectionally polarized microstrip antenna is not omnidirectional. Since this Ant output is further set to a constant value by AGC adjustment, it becomes impossible to correctly evaluate the 5 communication states, and the reliability of communication becomes low. Therefore, in the reception level calculation process, the electric field strength at the reception point is calculated by correcting the level of correlation output 1 using the radiation pattern of the reception antenna Ant and the reverse correction of AGC.

Note that in SS communication, since evaluation of uncorrelated signals is meaningless, the level of correlation output 1 after AGC adjustment is used.

Please refer to FIG. 13 again.

An example of the radiation pattern of the receiving antenna Ant is shown in FIG. 5a. This differs depending on the state in which the receiving antenna Ant is installed, but in this embodiment, when the device is in use, communication is performed with a suitable transmitter facing each other, and while maintaining a certain distance, the transmitter and the receiving antenna The relative phase relationship with Ant is updated sequentially, the reception level at each time (AGC adjustment value is kept constant) is organized as relative data, and it is used as seen from the reception antenna Ant. A table as shown in FIG. 5b is created in association with the position data of the transmitter, that is, azimuth data (Az: azimuth angle data) and elevation data (EQ: elevation/depression angle data), and It is stored in ROM.

In the system using the device of this embodiment, the position information of the transmitting collar is included in the transmitting data, so the ROM
Refer to the table and read the correction value.

Since the amount of attenuation in the AGC amplifier 111 is linear (see FIG. 6b), it can be immediately determined from the value of the register G. Therefore, the ANO input stored in the register DO, that is, the correlation output 1, is subjected to correction by the radiation pattern and AGC.
The electric field strength (relative value) at the receiving point is calculated by performing the inverse correction of .

The electric field strength data at the reception point obtained in the reception level calculation process described above is outputted from the serial output port E to a display processing device (not shown).

The operations of the CPU 10 have been described above, but the operations that characterize this embodiment will now be enumerated.

(1) If the synchronization is lost for a short time, the current state (that is, the oscillation frequency of vC○12) is maintained, so that communication can be resumed immediately when the communication state returns to normal.

(2) Since the received level is monitored and the frequency shift of the second local oscillator is successively corrected, even a received signal without a carrier component can be corrected well.

(3) Since the reception level is monitored and the AGC gain is adjusted, fine adjustments can be made.

(4) The electric field strength at the reception point is calculated by correcting the reception level using the antenna gain and AGC gain. In other words,
It is possible to grasp the exact situation of the receiving point and correctly evaluate the communication.

〔Effect of the invention〕

As explained above, according to the present invention, the oscillation means oscillates an electric signal at a set frequency, and the received spread spectrum signal is mixed with the electric signal oscillated by the oscillation means to generate a low frequency spread spectrum signal. The oscillation frequency of the oscillation means is adjusted so as to maximize the reception level, which is the signal obtained by envelope detection of the despread signal by the reference phase when code synchronization is established. , it becomes possible to track the receiving frequency with a simple configuration.

Further, as described with reference to the embodiment, since the oscillation frequency is simply adjusted by comparing the levels, digitization can be easily performed, and the receiving device can be made smaller.

In addition, this adjustment cycle can be changed quickly.

By adjusting in small steps, the accuracy of frequency tracking can be made sufficiently high.

[Brief explanation of the drawing]

FIGS. 1a, 1b, 1c and 1d are circuit diagrams showing details of an embodiment of the device, and FIG. 2a is a circuit diagram showing details of an embodiment of the device. Figures 2b, 2c and 2d are block diagrams showing the outline thereof, Figure 2g is a block diagram showing the outline of a communication system in which the embodiment device is used, and Figures 2e and 2f.
The figure is a block diagram showing a conventional example. FIG. 3a is a waveform diagram showing the correlation waveform performed by the microcomputer IO shown in FIGS. 1b and 2b, FIG. 3b is a waveform diagram schematically showing the synchronization maintenance process, and FIG. 4 is a waveform diagram showing the Doppler correction process. It is a waveform chart shown typically. Figure 5a is a graph showing the radiation pattern of the receiving antenna;
FIG. 5b is a plan view schematically showing an antenna gain correction data table stored in the microcomputer 10 shown in FIGS. 1b and 2b. FIG. 6a is a circuit diagram showing details of the AGC amplifier circuit shown in FIG. 1a, and FIG. 6b is a graph showing its characteristics. FIG. 7 is a waveform diagram showing an example of output from each part of the Costas loop demodulation circuit shown in FIG. 1c. Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 1
FIG. 3 is a flowchart showing an outline of the control executed by the microcomputer 10 shown in FIGS. 1b and 2b. 1: Distributor (spread signal distribution means) 2a: Balanced mixer (first despreading means) 2b = Balanced mixer (second despreading means) 2c: Balanced mixer (third despreading means) 3a: Bandpass filter (first signal extraction means) 3b-band filter (second signal extraction means) 3c: band filter (third
signal extraction means) 4a, 4b, 4c: amplifier circuit 6a: detection circuit (first detection means) 6b: detection circuit (second detection means) 6c: detection circuit (third detection means) 2a, 3a, 6a: (first detection means) 1 correlation detection means) 2b,
3b, 6b: (second correlation detection means) 2c, 3c,
6c: (Third correlation detection means) 5: Distributor
7: Buffer 8: Differential amplifier circuit (combining means) 9a, 9b: Low-pass filter 10: Microcomputer 11a, llb: D/A converter 10J1a, l
lb: (Reception control means) 12: VCO (energizing means) 13: PN code generator (pseudo noise signal generation means, phase shift means) 14a, 14b: Balanced mixer 15a, 15b: Low pass filter 16a, 16b: Amplifier 17: Batsuhua 1B, 2
2: Limiter 19, 27, 29: Binarization circuit 20: Multiplier 21: Loop filter 23: V
Co 25: Phase shifter 26: Full wave rectifier circuit 30: First signal generating section 32: Second signal generating section 31: Tap selection circuit 33: Initial set circuit 34.35: Exclusive OR gate 36+, 36
−． 36o: Sign shaping circuit 101: High frequency amplifier 102.106, 107, 109.117: Bandpass filter 103: Crystal oscillator 104.123: Buffer 108: Intermediate frequency amplifier 105.113, 114, 115, 116, 119:
Multiplier 110.112.118: Low-pass filter 111
: AGC amplifier (level adjustment means) 122: VCO 5YN : Synthesizer (oscillation means) Aku x: Mixer MIX, 110, 111, 112 : (Frequency mixing means) voice 2d figure voice 21 figure east 29 prisoner voice 58 figure υ Voice 5b Prisoner 6a Ward East 6b Map AGC 9° East 7th Map O

Claims (3)

[Claims] (1) Oscillation means for oscillating an electrical signal at a set frequency; Frequency mixing means for mixing the received spread spectrum signal and the electrical signal oscillated by the oscillation means to generate a spread spectrum signal at a low frequency; Frequency mixing means output spread spectrum signal distributing means for distributing the spread spectrum signal into at least three, a first spread signal, a second spread signal, and a third spread signal substantially equal to the second spread signal; Pseudo-noise signal generating means for generating a pseudo-noise signal having the same code sequence as the noise signal; receiving the pseudo-noise signal generated by the pseudo-noise signal generating means, at least a first pseudo-noise signal, a predetermined code higher than the first pseudo-noise signal; Phase shifting means for outputting a second pseudo-noise signal with a phase lead of the number of bits and a third pseudo-noise signal with a phase lag of a predetermined number of code bits than the first pseudo-noise signal; pseudo-noise signal generation energizing means for energizing the means at a set bit rate; first despreading means for despreading the first spread signal by the first pseudo-noise signal to generate a first despread signal; a first signal extraction means for extracting a signal component; and a first detection means for envelope-detecting the extracted signal component of the first signal extraction means; a second despreading means for despreading the spread signal to generate a second despread signal; a second signal extraction means for extracting a signal component of the second despread signal; and a second despreading means for extracting a signal component of the second despread signal; a second correlation detection means comprising: a second detection means for envelope detection; a third despreading means for despreading the third spread signal using the third pseudo-noise signal to generate a third despread signal; a third signal extraction means for extracting a signal component of the despread signal; and a third detection means for envelope detection of the extracted signal component of the third signal extraction means; synthesis means for generating a signal according to the difference between the output and the output of the third correlation detection means; and a control means for controlling at least the oscillation means and the energizing means; After setting a bit rate that is different from the bit rate of the noise signal by a predetermined value, the output of the first correlation detection means is monitored, and when the output becomes higher than a predetermined level, the pseudo noise signal contained in the received spread spectrum signal is detected. Execute initial acquisition control to update and set a bit rate equal to the bit rate; After updating and setting the bit rate in the initial acquisition control, monitor the output of the first correlation detection means and the output of the synthesis means to adjust the bit rate. Synchronization maintenance control that sequentially updates the frequency of the electrical signal to control the output of the synthesis means to a reference level; and frequency correction control that sequentially updates the frequency of the electrical signal and controls the output of the first correlation detection means to the maximum. A reception frequency tracking device for a reception device for spread spectrum communication, comprising: reception control means; (2) The frequency mixing means includes a level adjustment means, the reception control means further controls the level adjustment means, and after the bit rate is updated and set in the initial acquisition control, the output of the first correlation detection means and the combining means are synchronization maintenance control that monitors the output and sequentially updates the bit rate to control the output of the synthesis means to a reference level; and a level that controls the output of the first correlation detection means to a set level by adjusting the gain of the level adjustment means. According to claim (1), the adjustment control and the frequency correction control for controlling the output of the first correlation detection means to the maximum by sequentially updating and setting the frequency of the electric signal are continuously executed. A receiving frequency tracking device for a receiver for spread spectrum communication. (3) A reception frequency tracking device for a reception device for spread spectrum communication according to claim (2), wherein the reception control means adjusts the gain of the level adjustment means to a constant value in the frequency correction control.