JPS638629B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an ultraviolet erasing MOS type semiconductor nonvolatile memory device [hereinafter referred to as "FAMOS" (Floating
This is related to the manufacturing method of the gate avalanche injection MOS).

FIGS. 1A to 1G are cross-sectional views showing the main stages of an example of a conventional FAMOS manufacturing method.

First, as shown in FIG. 1A, a thick silicon oxide film 2 for device isolation is selectively formed on the main surface of a p-type silicon substrate 1 to surround and isolate the portion where devices are to be formed. Then, a relatively thin silicon oxide film 3 for forming a first gate oxide film is formed on the main surface of the p-type silicon substrate 1 separated by the silicon oxide film 2. Next, as shown in FIG. 1B, the silicon oxide film 2,
A polycrystalline silicon film 4 for forming a floating gate electrode is formed over each surface of the polycrystalline silicon film 3, and then impurities such as phosphorus are implanted or Perform heat diffusion. Next, the surface portion of the polycrystalline silicon film 4 is oxidized to form a second
A silicon oxide film 5 for forming a gate oxide film is formed, a polycrystalline silicon film 6 for forming a control gate electrode is formed on the surface of this silicon oxide film 5, and then a polycrystalline silicon film 6 for forming a control gate electrode is formed. Impurities such as phosphorus are implanted or thermally diffused to adjust the resistivity to a desired value. Thereafter, a photoresist film 7 for use as an etching mask is selectively formed on a portion of the polycrystalline silicon film 6 that is to become a control gate electrode.
Next, as shown in FIG. 1C, polycrystalline silicon film 6 is etched using photoresist film 7 as a mask, leaving control gate electrode 6a under photoresist film 7. Next, as shown in FIG. 1D, a photoresist film 7 and a control gate electrode 6 are formed.
The silicon oxide film 5 is etched using a as a mask.
The second gate oxide film 5a is left under the control gate electrode 6a. Next, as shown in FIG. 1E, etching is performed on the polycrystalline silicon film 4 using the photoresist film 7, the control gate electrode 6a, and the second gate oxide film 5a as masks, and the second gate oxide film 5a is etched. Floating gate electrode 4a is left below.
If an isotropic etching method is used when etching the polycrystalline silicon film 4, the control gate electrode 6a is etched at the same time as the polycrystalline silicon film 4 is etched.
Since the side etching also progresses to the side surfaces of the gate electrode 4a, the gate length of the control gate electrode 6a becomes shorter than the gate length of the floating gate electrode 4a. Furthermore, when an anisotropic etching method is used when etching the polycrystalline silicon film 4, there is almost no side etching to the side surfaces of the control gate electrode 6a, so the gate length of the control gate electrode 6a is equal to that of the floating gate electrode 4a. It is almost the same as the gate length. Next, as shown in FIG. 1F, the photoresist film 7 is removed, and then,
The silicon oxide film 3 is etched using the control gate electrode 6a, the second gate oxide film 5a, and the floating gate electrode 4a as masks to form the floating gate electrode 4.
First gate oxide film 3a is left under a, and a part of the main surface of p-type silicon substrate 1 is exposed.
Note that due to this etching, the size of the second gate oxide film 5a becomes smaller than the size of the control gate electrode 6a. Next, n-type impurities are selectively ion-implanted or thermally diffused into the exposed main surface portion of p-type silicon substrate 1 to form n-type source/drain regions 8a and 8b. Next, as shown in FIG. 1G, the n-type source/drain regions 8a, 8b, the first gate oxide film 3 are
a, floating gate electrode 4a, second gate oxide film 5
A thin silicon oxide film 9 is formed over each surface of the control gate electrode 6a and the control gate electrode 6a, and further,
A silicon oxide film 10 containing phosphorus is formed over each surface of the silicon oxide film 9 and the silicon oxide film 2 by a vapor phase growth method or the like. After that, an aluminum wiring film 11 is formed on the surface of the silicon oxide film 10, and finally, the silicon oxide film 1
By forming a passivation film 12 on the surface of the aluminum wiring film 11 so as to cover the aluminum wiring film 11, a FAMOS according to this conventional method can be obtained.

Next, the FAMOS [1st
The operation shown in Figure G] will be explained.

For example, if a reverse voltage is applied to the pn junction formed between the n-type source/drain region 8a and the p-type silicon substrate 1 to cause avalanche breakdown, high-energy hot electrons (hereinafter referred to as "electrons") ) is generated. When a high positive voltage is applied to the silicon substrate 6a, the generated electrons are injected into the floating gate electrode 4a and accumulated by a tunneling phenomenon. In this way, a logic signal is stored depending on whether or not electrons are accumulated in the floating gate electrode 4a. Furthermore, when erasing a stored logic signal, ultraviolet rays (UV) are irradiated onto the side surface of the floating gate electrode 4a from the direction of the arrow shown by the dashed line to remove the electrons accumulated on the side surface of the floating gate electrode 4a. Release it to the outside.

By the way, in the FAMOS according to this conventional method, if an isotropic etching method is used when forming the floating gate electrode 4a at the stage shown in FIG. The gate length is shorter than that of the control gate electrode 6a even when anisotropic etching is used.
Since the gate length of the floating gate electrode 4a is almost the same as that of the floating gate electrode 4a, when used under fluorescent lamp or sunlight illumination, these illumination lights directly illuminate the sides of the floating gate electrode 4a. do. Therefore, a large amount of electrons accumulated in the floating gate electrode 4a are emitted to the outside by the illumination light, and the storage retention characteristic of the logic signal deteriorates, causing the device to become inoperable in a short period of time. For example, under fluorescent light, it becomes inoperable after 113 hours.
It has been reported that the device became inoperable after 41 hours under sunlight (on cloudy days).

This invention has been made in view of the above points, and by making the gate length of the control gate electrode longer than the gate length of the floating gate electrode, direct irradiation of illumination light onto the side surface of the floating gate electrode is controlled. It is an object of the present invention to provide a method for manufacturing a FAMOS in which memory retention characteristics of logic signals are improved by suppressing the gate electrode.

Figures 2A to 2E are FAMOS of one embodiment of this invention.
FIG. 3 is a cross-sectional view showing the main stages of the manufacturing method.

In the figure, the same reference numerals as those in the conventional example shown in FIG. 1 indicate equivalent parts.

The steps shown in FIG. 2A correspond to the steps in the conventional example shown in FIG. 1D after passing through the same steps as the steps in the conventional example shown in FIGS. 1A to C.

At this stage, as shown in FIG. 2A, the control gate electrode 6a is etched using the photoresist film 7 and the control gate electrode 6a as a mask.
In leaving the second gate oxide film 5a under a,
An etching protection film 13 that is not etched by an etching agent for etching polycrystalline silicon is formed on the side surface of the control gate electrode 6a. For example, when using a dry oxide film etching method using a mixed gas of carbon tetrafluoride (CF ₄ ) and hydrogen (H ₂ ) for etching at this stage, carbon difluoride (CF ₂ ) type polymer is automatically formed. However, when using the wet oxide film etching method, the etching protection film 13 is not automatically formed, so the photoresist film 7 is heated in advance to a temperature of about 100-odd degrees (°C) to make it fluid. The control gate electrode 6 may be made to hang down so that the side surface of the control gate electrode 6a is covered.
A photoresist agent is selectively applied to the side surface of a to form an etching protection film 13.

Next, as shown in FIG. 2B, the photoresist film 7, the control gate electrode 6a with the etching protection film 13 formed on the side surfaces, and the second gate oxide film 5 are etched.
Polycrystalline silicon film 4 is etched using a as a mask.
The floating gate electrode 4a is left under the second gate oxide film 5a. At this time, if the etching time is selected appropriately, the side surfaces of the control electrode 6a are protected by the etching protection film 13, so the control gate electrode 6a will not be side etched and only the floating gate electrode 4a will be side etched. Therefore, the gate length of floating gate electrode 4a is shorter than the gate length of control gate electrode 6a. Next, as shown in FIG. 2C, the photoresist film 7
remove. At this time, if the photoresist film 7 is removed by oxygen plasma, the etching protection film 13 is also removed at the same time. Afterwards,
The silicon oxide film 3 is etched using the control gate electrode 6a, the second gate oxide film 5a, and the floating gate electrode 4a as masks to form the floating gate electrode 4.
The first gate oxide film 3a may be left under the p-type silicon substrate 1, and a part of the main surface of the p-type silicon substrate 1 may be exposed. Note that due to this etching, the size of the second gate oxide film 5a becomes smaller than the size of the floating gate electrode 4a.

Next, on the exposed main surface of the p-type silicon substrate 1, a first gate oxide film 3a, a floating gate electrode 4a, a second gate oxide film 5a, and an antistatic gate electrode 6a are formed.
By ion implantation or thermal diffusion of n-type impurities using the silicon oxide film 2 as a mask,
This is the stage of forming the drain region, but if
When the n-type source/drain regions are formed by ion implantation of n-type impurities, the gate length of the control gate electrode 6a is longer than that of the floating gate electrode 4a and the gate oxide films 3a, 5a. As shown, n-type source/drain regions 14a and 14 formed on the exposed main surface of the p-type silicon substrate 1
Since b does not reach the part directly under the first gate oxide film 3a on the main surface of the p-type silicon substrate 1,
It becomes impossible to operate as FAMOS. Therefore, n
After forming the type source/drain regions 14a and 14b, n type impurity diffusion layers 15a and 15b are further formed on the exposed main surface of the p type silicon substrate 1 by thermal diffusion of an n type impurity such as phosphorus. At this time, in order to make the diffusion depth of the n-type impurity diffusion layers 15a, 15b shallower than the diffusion depth of the n-type source/drain regions 14a, 14b, for example, in the case of thermal diffusion of phosphorus, the n-type impurity diffusion layer It is desirable that the sheet resistance of 15a and 15b is approximately several hundred Ω/□. Note that this step cannot be performed unless the main surface of the p-type silicon substrate 1 is exposed because phosphorus will not be thermally diffused into the silicon substrate 1. Next, as shown in FIG. 2E, the n-type source/drain regions 14a, 14b, the n-type impurity diffusion layers 15a, 15b, the first gate oxide film 3a are ,
A silicon oxide film 9 is formed to cover each surface of the floating gate electrode 4a, the second gate oxide film 5a, and the control gate electrode 6a, and a silicon oxide film 9 is further formed.
A silicon oxide film 10 containing phosphorus is then formed over each surface of the silicon oxide film 2. Thereafter, an aluminum wiring film 11 is formed on the surface of the silicon oxide film 10, and finally, a passivation film 12 is formed on the surface of the silicon oxide film 10 to cover the aluminum wiring film 11, resulting in the method of this embodiment. FAMOS is obtained.

In the FAMOS according to the method of this embodiment, the storage of logic signals is the same as in the case of the FAMOS according to the conventional method shown in FIG.
When erasing the logic signal stored in the floating gate electrode 4a, the side surface of the floating gate electrode 4a is irradiated with ultraviolet rays (UV) from the diagonal direction of the arrow shown by the dashed line, so that the control gate electrode 6a does not interfere. do. Furthermore, FAMOS, which is the method of the embodiment,
Since the gate length of the control gate electrode 6a is longer than the gate length of the floating gate electrode 4a, even if it is used under fluorescent lamp or sunlight illumination, the illumination light will not reach the side of the floating gate electrode 4a. direct irradiation can be suppressed by the control gate electrode 6a. Therefore, the illumination light is reflected by at least the main surface of the p-type silicon substrate 1 and the floating gate electrode 4
Since the side surface of the floating gate electrode 4a is illuminated, the illumination intensity of the illumination light on the side surface of the floating gate electrode 4a is reduced, and the emission of accumulated electrons in the floating gate electrode 4a to the outside due to the illumination light is reduced, which improves memory retention of logic signals. Improved properties and longer time to inoperability. According to the inventors' experimental results, the gate length of the control gate electrode 6a is smaller than the gate length of the floating gate electrode 4a.
When lengthened by 0.7 μm, the time it takes to become inoperable when used under fluorescent light or sunlight is shorter than that of FAMOS using the conventional method shown in Figure 1. It became about 1.5 times longer.

In this embodiment, a p-type silicon substrate 1 is used, but the present invention can also be applied to a case where an n-type silicon substrate is used.

As explained above, in the FAMOS manufacturing method of the present invention, the gate length of the control gate electrode is made longer than the gate length of the floating gate electrode. It can be cured by Therefore, the irradiation intensity of the illumination light on the side surfaces of the floating gate electrode is reduced, and the emission of accumulated electrons in the floating gate electrode to the outside by the illumination light is reduced, improving the memory retention characteristics of the logic signal and making it inoperable. You can lengthen the time it takes.

[Brief explanation of the drawing]

Figures 1 A to G are cross-sectional views showing the main stages of an example of a conventional FAMOS manufacturing method, and Figures 2 A to E
FIG. 2 is a cross-sectional view showing the main stages of a FAMOS manufacturing method according to an embodiment of the present invention. In the figure, 1 is a p-type silicon substrate (first conductivity type silicon substrate), 2 is a silicon oxide film for element isolation, 3 is a silicon oxide film for forming a first gate oxide film, and 3a is a first gate oxide film. , 4 is a polycrystalline silicon film for forming a floating gate electrode, 4a is a floating gate electrode, 5 is a silicon oxide film for forming a second gate oxide film, 5a is a second gate oxide film, and 6 is a polycrystalline silicon film for forming a control gate electrode. A crystalline silicon film, 6a a control gate electrode, 7 a photoresist film for an etching mask, 13 an etching protection film, 14a and 1
4b is an n-type source/drain region (second conductivity type source/drain region), and 15a and 15b are n-type impurity diffusion layers (components of the second conductivity type source/drain region). Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first step of selectively forming a silicon oxide film for element isolation surrounding the element formation portion on the main surface of the silicon substrate of the first conductivity type; A silicon oxide film for forming a first gate oxide film, a polycrystalline silicon film for forming a floating gate electrode, a silicon oxide film for forming a second gate oxide film, and a polycrystalline silicon film for forming a control gate electrode are formed on the separated portions. a second step of sequentially forming a photoresist film for an etching mask on a portion of the polycrystalline silicon film for forming a control gate electrode that is to become a control gate electrode, a third step of forming a photoresist film for an etching mask using the photoresist film as a mask A fourth step in which the polycrystalline silicon film for forming a control gate electrode is etched to leave a control gate electrode under the photoresist film, and the etching is performed using the photoresist film and the control gate electrode as a mask by self-alignment. The second above
an etching protection film that is not etched by an etching agent applied to the silicon oxide film for forming a gate oxide film to leave a second oxide film under the control gate electrode and etching polycrystalline silicon on the side surface of the control gate electrode; In a fifth step, etching is performed using the second gate oxide film as a mask on the polycrystalline silicon film for forming the floating gate electrode and the silicon oxide film for forming the first gate oxide film in a self-aligned manner. a sixth step of sequentially leaving a floating gate electrode and a first gate oxide film under the second gate oxide film and exposing a part of the main surface of the silicon substrate; and an exposed main surface portion of the silicon substrate. A method for manufacturing a MOS type semiconductor nonvolatile memory device, comprising a seventh step of selectively introducing impurities of a second conductivity type into the source/drain regions of the second conductivity type.