JP3183262B2 - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device, and more particularly to a method for manufacturing a flash memory comprising stacked gate type memory cells.

[0002]

2. Description of the Related Art An example of a conventional flash memory is shown in FIG.
This will be described with reference to FIGS. In the figure, an example of a conventional flash memory including stacked gate type memory cells is as follows. That is, (1
00), a field oxide film 202 having a thickness of about 0.5 μm is provided in an element isolation region on the surface of a P-type silicon substrate 201 having a surface impurity concentration of about 2 × 10 17 cm −3. A stacked gate type memory cell is provided in the formation region.

Each memory cell is formed on a surface of a P-type silicon substrate 201 through a gate oxide film 203 and a gate oxide film 203 having a thickness of about 10 nm provided on the surface of a P-type silicon substrate 201. Floating gate electrode 2
04 (N with a thickness of about 150 nm containing impurities)
And a floating gate electrode 2
Gate insulating film 205 (film thickness 1) provided on the surface of
A silicon oxide film having a thickness of about 0 nm, a silicon nitride film having a thickness of about 10 nm, and a silicon oxide film having a thickness of about 6 nm), and a control gate provided on the floating gate electrode 204 via a gate insulating film 205. Electrode 206
a, 206b, 206c, etc. (film thickness 15 also serving as word line)
Of about 0 nm N ⁺ type polycrystalline silicon film) and P
Region 2 provided on the surface of the silicon substrate 201
07ab, 207cd, and the like, and a drain region 208 provided on the surface of the P-type silicon substrate 201.

The drain region 208 is formed of, for example, an N ⁺ type diffusion layer which is self-aligned with the control gate electrode 206b, the control gate electrode 206c, the floating gate electrode 206, and the field oxide film 202. One drain region 208 includes
It is shared by two memory cells. Each drain region is connected to bit lines 211a, 211b, etc. provided on the surface of the interlayer insulating film 209 via bit contact holes 211a, 211b, etc. provided in the interlayer insulating film 209 covering the surface of the memory cell. Have been. Bit line 2
Reference numerals 11a, 211b, and the like are orthogonal to the control gate electrodes 206a, 206b, 206c, and the like via an interlayer insulating film 209.

The source region 207ab is formed in a self-aligned manner with the control gate electrode 206a, the control gate electrode 206b, the floating gate electrode 206 and the field oxide film 202.
It is provided on the surface of the mold silicon substrate 201, and is shared by required memory cells among the memory cells belonging to the control gate electrode 206a and the control gate electrode 206b.
Each source region 207ab is provided on a surface of interlayer insulating film 209 via a contact hole (not shown) provided in interlayer insulating film 209 for every 16 bits, for example, in a wiring provided in parallel with bit line 211a or the like. It is connected to the.

The outline of writing and erasing of the above-mentioned memory cell is as follows: the voltage applied to the drain region 208;
Assuming that the voltage applied to 7ab and the like, the voltage applied to the control gate electrode 206a and the like, and the voltage applied to the P-type silicon substrate 201 are Vd, Vs, Vcg and Vsub, respectively, the following is obtained.

For example, Vs = 0 V, Vsub = 0 V,
Vd = 5.5V only for bit line 211a (Vd = 0V for other bit lines 211 etc.) and control gate electrode 206b
By setting only Vcg = 12 V (Vcg = 0 V for other control gate electrodes 206 a and the like), the bit line 211 a
Writing is performed only on the memory cells belonging to and control gate electrode 206b.

The potential of the floating gate electrode 204 of this memory cell is a value divided by the capacitance ratio between the gate oxide film 203 and the gate insulating film 205. In this memory cell (on state), the drain region 208 and the source Region 20
A current flows between 7ab. If the potential of the floating gate electrode 204 of this memory cell is about (Vd =) 5.5 V, the pinch-off point is near the drain region 208, and the hot electrons generated due to an increase in the electric field intensity near this point. (Electrons having energy exceeding the insulation potential energy of the gate oxide film 203)
Is injected into the floating gate electrode 204.

By the way, as the amount of electrons injected into the floating gate electrode 204 increases, the floating gate electrode 204
Is lowered to a negative level, the threshold voltage of this memory cell (as viewed from the control gate electrode 206b) shifts in the positive direction to about 7V.

[0010] Erasing (writing data) of a memory cell is to extract electrons injected into the floating gate electrode 204 from the floating gate electrode 204. For erasing in the flash memory, for example, the P-type silicon
sub = 5V, (all control gate electrodes 206a, 2
06b, 206c, etc.) Vcg = −12V, (all drain regions 208) Vd; open, (all source regions 207) Vs; open.

The bit line 211a and the control gate electrode 206
When writing is performed only on the memory cell belonging to b, the potential difference applied to the gate oxide film 203 is higher than 8 V in this memory cell as compared with other memory cells, and a strong electric field is applied to the gate oxide film 203. Is done. As a result, a Fowler-Noldheim current (FN current) based on the quantum tunnel effect flows, and electrons are extracted from the floating gate electrode 204 of this memory cell.

In a flash memory, even when erasing is performed under certain conditions, the threshold voltage (erasing threshold voltage) of each erased memory cell varies by about 2V. If at least one memory cell has an erase threshold value of 0 V or more, writing cannot be performed on a memory cell sharing a bit line with the memory cell. Therefore, it is necessary to set the erasing conditions so that the minimum and maximum values of the erase threshold voltage are, for example, 0.5 V and 3 V.

With respect to the above-mentioned flash memory manufacturing method, there is a manufacturing method as shown in, for example, Japanese Patent Application Laid-Open No. 8-191109. Referring to FIGS. 10 to 14, the conventional flash memory is manufactured as follows.

In FIG. 12A, first, a field oxide film 202 is formed as a semiconductor substrate in, for example, an element isolation region on the surface of a P-type silicon substrate 201, and a field oxide film 202 is formed in an element formation region on the surface of the P-type silicon substrate 201. A gate oxide film 203 is formed by oxidation. Polycrystalline silicon film 212 is formed on the entire surface. Next, a photoresist film pattern 213 exposing a part of the polycrystalline silicon film 212 that is on the field oxide film 202 is formed by a known method.

Subsequently, impurity ions 214 are implanted by an ion implantation method. The impurity ions at this time include phosphorus (P), arsenic (As), antimony (Sb) and the like, and arsenic (As) or antimony (Sb) having a small diffusion constant is preferable.

In FIG. 12B, after removing the photoresist film pattern 213, a heat treatment is performed at a predetermined temperature. This heat treatment is performed on the field oxide film 2.
The impurity ions 214 implanted into a part of the polycrystalline silicon film 212 on
The process is performed under such a condition that it is almost diffused into the upper polycrystalline silicon film portion but is not diffused into the polycrystalline silicon film portion above the gate oxide film 203.

As a result, as shown in FIG. 12 (c), the impurity is unevenly distributed in the portion of the polycrystalline silicon film which hits the field oxide film 203, and the polycrystal in a state where the impurity does not exist in the portion which hits the region where the element is to be formed. A silicon film (polycrystalline silicon film in which impurities are unevenly distributed) 212a is obtained.

Next, as shown in FIG. 13D, by using the photoresist film pattern 215 as a mask, a part of the polycrystalline silicon film 212a where the impurity is unevenly distributed, which falls on the field oxide film 202, is removed. FIG. 13 (e)
A polycrystalline silicon film pattern 216 is formed as shown in FIG.

Next, the photoresist film pattern 215
Is removed, a thermal oxidation process at a temperature of, for example, about 1000 degrees is performed to form a thermal oxide film having a thickness of, for example, about 10 nm on the surface of the polycrystalline silicon film pattern 216 (not shown).

This thermal oxide film becomes a first insulating film constituting a part of the gate insulating film 205 between the floating gate electrode and the control gate electrode. By the heat treatment at the time of forming the first insulating film, the impurities 214 unevenly distributed in the polycrystalline silicon film 216 are further diffused and reach the portion on the gate oxide film 203. On the other hand, since the polycrystalline silicon film pattern (especially on the gate oxide film 203) 216 was initially free of impurities, the main portion of the first insulating film and the gate oxide film 203 in the thermal oxidation process were not used. The adverse effects of impurities on silicon have been reduced.

As a result, a first insulating film partially but not including the impurities (not included in the main portion) and a gate oxide film 203 free from the influence of the impurities can be obtained. Next, the first
A silicon nitride film (not shown) having a thickness of, for example, about 10 nm formed by low pressure vapor deposition (LPCVD) and a silicon oxide film having a thickness of, for example, about 6 nm formed by high temperature vapor deposition are formed on the insulating film. Thus, a gate insulating film 205 made of a so-called silicon oxide film, silicon nitride film, and silicon oxide film (ONO film) as shown in FIG.
Is formed.

Next, as shown in FIG. 14G, a second polycrystalline silicon film 217 is grown on the entire surface, for example, to a thickness of about 150 nm. Further, the second polycrystalline silicon film is doped with, for example, phosphorus. Note that a silicide layer (not shown) may be further formed on second polycrystalline silicon film 217 to reduce wiring resistance.

In FIG. 14 (h), a second polysilicon film 217, a gate insulating film 205 and a polysilicon film pattern 216 are sequentially patterned.
Control gate electrode 20 made of polycrystalline silicon film 217
6 and a polycrystalline silicon film pattern 216 are formed. Next, an interlayer insulating film 209 made of a BPSG film is formed on the entire surface. Next, contact holes are formed at predetermined locations in the interlayer insulating film 209 (not shown). For example, an aluminum-based metal film is formed on the entire surface, and this metal film is patterned to form a bit line 211.
Is formed.

When a non-volatile semiconductor memory device having a floating gate electrode made of an impurity-containing polycrystalline silicon film is manufactured by the above-described manufacturing method, a predetermined portion of a portion on a field oxide film as a floating gate electrode is used. A polycrystalline silicon film in which impurities are unevenly distributed is used.
Therefore, even if a high-temperature heat treatment is performed in a subsequent step, the impurity actually floats in the polycrystalline silicon film in which the impurity is unevenly distributed, as compared with the case where the impurity is previously entirely doped. It is difficult to diffuse even to the insulating film above and below the part to be the gate electrode (the gate oxide film and the gate insulating film on the region where the element is to be formed).

On the other hand, in the above-mentioned polycrystalline silicon film in which impurities are unevenly distributed, the impurities are uniformly or non-uniformly in a portion of the polycrystalline silicon film which falls on a region where an element is to be formed (that is, a portion which will later become a floating gate electrode). It spreads anyway. That is, it is possible to obtain a nonvolatile semiconductor memory device in which the impurity doped into the floating gate electrode has little effect on the gate oxide film and the gate insulating film above and below the floating gate electrode on the region where the element is to be formed. Retention)
Can also be guaranteed.

[0026]

However, the above-mentioned conventional manufacturing method has the following problems. That is, lithography for forming a photoresist film pattern for ion-implanting impurities into a polycrystalline silicon film that will later become a floating gate electrode and lithography for patterning the polycrystalline silicon film to form a polycrystalline silicon film pattern are required. And the number of steps and the number of lithography increase.

After the impurity is implanted into the polycrystalline silicon film, a heat treatment is performed to diffuse the impurity ions.
Because the polycrystalline silicon film is not covered with an oxide film,
There is also the problem of outward diffusion.

An object of the present invention is to provide a nonvolatile semiconductor memory device having a floating gate electrode made of an impurity-containing polycrystalline silicon film, the number of steps required for forming the floating gate electrode without impairing the reliability and other functions, and lithography. An object of the present invention is to provide a method for manufacturing a nonvolatile semiconductor memory device that can reduce the number.

[0029]

[0030]

In order to achieve the above object,
The method for manufacturing a nonvolatile semiconductor device according to the present invention includes a film forming step, an N-type ion implantation step, a pattern forming step,
A method for manufacturing a nonvolatile semiconductor device, comprising at least a pattern removing step and a floating gate electrode forming step, wherein the film forming step includes forming a field oxide film in an element isolation region on a surface of a P-type silicon substrate; Forming a gate oxide film by thermal oxidation in the element formation area on the surface of the silicon substrate
This is a step of sequentially forming a polycrystalline silicon film, an oxide film, and a silicon nitride film on the entire surface. The N-type ion implantation step includes patterning the silicon nitride film on at least the element formation region and on the field oxide film to form a predetermined nitrided film. Forming a film pattern and ion-implanting N-type ion species in parallel with a normal to the surface of the P-type silicon substrate using the nitride film pattern as a mask to form an ion-implanted layer in the polycrystalline silicon film The pattern forming step is a step of sequentially patterning the oxide film and the polycrystalline silicon film using the nitride film pattern as a mask to form a predetermined polycrystalline silicon film pattern. This is a step of sequentially removing the film pattern and the oxide film. In the floating gate electrode forming step, a gate insulating film is formed on the entire surface, and a conductor film is formed on the entire surface. Forming the conductive film, the gate insulating film, and the polycrystalline silicon film pattern in order to form a control gate electrode made of the conductive film and a floating gate electrode made of the polycrystalline silicon film. is there.

A method for manufacturing a non-volatile semiconductor memory device further comprising a P-type ion implantation step between a pattern forming step and a pattern removing step, wherein the P-type ion implantation step uses the nitride film pattern as a mask. This is a step of implanting a P-type ion species into a P-type silicon substrate. After the P-type ion implantation step, each step is performed in the order of a pattern removing step and a floating electrode forming step.

A method for manufacturing a non-volatile semiconductor memory device further comprising a heat treatment step between an N-type ion implantation step and a pattern formation step, wherein the heat treatment step includes performing a heat treatment at a predetermined temperature. A step of diffusing an ion-implanted layer formed in the N-type ion implantation step and unevenly distributing N-type impurities in the polycrystalline silicon film; after a heat treatment step, a pattern forming step, a pattern removing step, and a floating electrode forming step Are performed in this order.

In the N-type ion implantation step,
The N-type ion species implanted into the P-type silicon substrate is arsenic (As) or antimony (Sb).

[0034]

Next, an embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention will be described with reference to the drawings.

(Embodiment 1) In FIGS. 1 to 5, a flash memory according to a first embodiment of the present invention includes a film forming step, an N-type ion implantation step, a heat treatment step,
It is manufactured by sequentially performing a pattern forming step, a pattern removing step, and a floating gate electrode forming step.

A, Film Forming Step In FIG. 3A, first, a field oxide film 102 is formed in the element isolation region on the surface of the P-type silicon substrate 101, and is formed in the element formation region on the surface of the P-type silicon substrate 101. A gate oxide film 103 is formed by thermal oxidation. Subsequently, a polycrystalline silicon film 112, an oxide film 113, and a nitride film 114 are sequentially formed on the entire surface.

B, N-type ion implantation step Next, FIG.
As shown in FIG. 5, a photoresist film pattern 115 having an opening at least on a part of the field oxide film 102 is formed.
Is formed. Next, the photoresist film pattern 11
5 is used as a mask to etch nitride film 114 to form nitride film pattern 116. Using the photoresist film pattern 115 as a mask, N-type ion species are ion-implanted substantially in parallel with the normal to the surface of the P-type silicon substrate 101, and impurity ions 117 are introduced into the polycrystalline silicon film 112.

N ions are implanted into this polycrystalline silicon film.
Examples of the type ion species include phosphorus (P), arsenic (As), and antimony (Sb), and arsenic (As) or antimony (Sb) having a small diffusion constant is particularly suitable.

C, Heat Treatment Step Next, after removing the photoresist film pattern 115, heat treatment is performed at a predetermined temperature. The heat treatment at this time is performed by the field oxide film 102.
Impurity ions 117 implanted into a part of the upper polysilicon film 112 substantially diffuse into the polysilicon film 112 on the field oxide film 102, but do not diffuse into the polysilicon film 112 on the gate oxide film 103. This is performed under conditions that do not diffuse into the 112 portion.

By this heat treatment, as shown in FIG.
The impurity ions 117 are diffused, and the impurity ions 117 are present in the portion of the polycrystalline silicon film 112 on the field oxide film 102, but hardly exist in the portion of the polycrystalline silicon film 112 on the gate oxide film 103.
At this time, an oxide film 113 is formed on the polycrystalline silicon film 112.
Exists, there is no possibility that the impurity 117 will diffuse outward. In addition, this heat treatment is not hindered even in a heat treatment in a later step (for example, activation of the source / drain diffusion layer) because the impurity 117 is unevenly distributed.

D, Pattern Forming Step In FIG. 4D, next, using the nitride film pattern 116 as a mask,
Oxide film 113 and polycrystalline silicon film 112 are sequentially etched to form polycrystalline silicon film pattern 118.

E, Pattern Removal Step In FIG. 4E, after the nitride film pattern 116 and the oxide film 113 are sequentially removed, a thermal oxidation process is performed at a temperature of, for example, about 1000 ° C. A thermal oxide film having a thickness of, for example, about 10 nm is formed on the surface of the pattern 118 (not shown). This thermal oxide film becomes a first insulating film that constitutes a part of the gate insulating film 105 between the floating gate electrode and the control gate electrode.

F, Floating Gate Forming Step By the heat treatment at the time of forming the first insulating film, the impurity ions 117 unevenly distributed in the polycrystalline silicon film pattern 118 are further diffused to the portion on the gate oxide film 103. Reach. On the other hand, since the polycrystalline silicon film pattern (especially on the gate oxide film 103) 118 was initially free of impurities, the main portion of the first insulating film and the gate oxide film 103 in the above-described thermal oxidation step were not removed. The adverse effects of impurities are reduced.

Therefore, the first insulating film partially but not containing the impurities (not contained in the above-mentioned main portion) and the gate oxide film 103 free from the influence of the impurities can be obtained. Next, the first
A silicon nitride film (not shown) having a thickness of, for example, about 10 nm formed by low pressure vapor deposition (LPCVD) and a silicon oxide film having a thickness of, for example, about 6 nm formed by high temperature vapor deposition are formed on the insulating film. Thereby, as shown in FIG. 4E, a gate insulating film 105 made of a so-called silicon oxide film, silicon nitride film, and silicon oxide film (ONO film) is formed.

Next, as shown in FIG. 4F, a second polycrystalline silicon film 119 is grown on the entire surface, for example, to a thickness of about 150 nm. Further, the second polycrystalline silicon film is doped with, for example, phosphorus. Note that a silicide layer (not shown) may be further formed on second polycrystalline silicon film 119 to reduce wiring resistance.

Next, a second polycrystalline silicon film 119, a gate insulating film 105 and a polycrystalline silicon film pattern 118 are formed.
Are sequentially patterned to form a second polycrystalline silicon film 11.
9 and a floating gate electrode 104 made of a polycrystalline silicon film pattern 118 are formed. Next, an interlayer insulating film 109 made of a BPSG film is formed on the entire surface. Next, a contact hole is formed in a predetermined place in the interlayer insulating film 109 (not shown). For example, an aluminum-based metal film is formed on the entire surface, and this metal film is patterned to form the bit lines 111 as shown in FIG.

(Embodiment 2) Next, a second embodiment of the present invention will be described with reference to the drawings. In the second embodiment, after forming a polycrystalline silicon film pattern, a process of implanting P-type ion species into a P-type silicon substrate using a nitride film pattern as a mask is performed in order to increase the breakdown voltage between elements. is there. 1 and 6 to 9, the flash memory according to the second embodiment includes a film forming step, an N-type ion implantation step, a pattern formation step, a P-type ion implantation step, a pattern removal step, and a floating gate. It is manufactured by sequentially performing an electrode forming process. Manufactured.

A, Film Forming Step First, in FIG. 7A, a field oxide film 102 is formed in an element isolation region on the surface of a P-type silicon substrate 101, and is formed in an element formation region on the surface of the P-type silicon substrate 101. A gate oxide film 103 is formed by thermal oxidation. Subsequently, a polycrystalline silicon film 112, an oxide film 113,
A nitride film 114 is sequentially formed.

B, N-Type Ion Implantation Step Referring to FIG. 7B, a photoresist film pattern 115 having an opening at least partially on the field oxide film 102 is formed. Next, the nitride film 114 is etched using the photoresist film pattern 115 as a mask to form a nitride film pattern 116. Using the photoresist film pattern 115 as a mask, an N-type ion species is ion-implanted substantially parallel to a normal to the surface of the P-type silicon substrate 101 to introduce impurity ions 117 into the polycrystalline silicon film 112.

The N-type ion species used for ion implantation include:
There are phosphorus (P), arsenic (As), and antimony (Sb), and arsenic (As) or antimony (Sb) having a small diffusion constant is particularly suitable.

C, Heat Treatment Step In FIG. 7C, the photoresist film pattern 115 is removed, and then heat treatment is performed at a predetermined temperature. In the heat treatment at this time, the impurity ions 117 implanted into a part of the polycrystalline silicon film 112 on the field oxide film 102 are almost diffused into the polycrystalline silicon film 112 on the field oxide film 102. This is performed under conditions that do not diffuse into the polycrystalline silicon film 112 on the gate oxide film 103.

By this heat treatment, as shown in FIG.
The impurity ions 117 are diffused, and the impurity ions 117 are present in the portion of the polycrystalline silicon film 112 on the field oxide film 102, but hardly exist in the portion of the polycrystalline silicon film 112 on the gate oxide film 103.

At this time, on the polycrystalline silicon film 112,
Since the oxide film 113 exists, there is no possibility that the impurity 117 will diffuse outward. In addition, this heat treatment is not hindered even in a heat treatment in a later step (for example, activation of the source / drain diffusion layer) because the impurity 117 is unevenly distributed.

D, Pattern Forming Step In FIG. 8D, next, the nitride film pattern 116 is formed.
Film 113, polycrystalline silicon film 11
2 are sequentially etched to form a polycrystalline silicon film pattern 118.

E, P-Type Ion Implantation Step In FIG. 8E, next, using the nitride film pattern 116 as a mask, P-type ion species are implanted into the P-type silicon substrate 101. Thus, a P-type ion implantation layer 120 is formed in the P-type silicon substrate 101.

F, Pattern Removal Step Next, after the nitride film pattern 116 and the oxide film 113 are sequentially removed, a thermal oxidation process is performed at a temperature of, for example, about 1000 ° C., and the surface of the polycrystalline silicon film pattern 118 is, for example, about 10 nm. A thermal oxide film having a film thickness of not shown is formed (not shown). This thermal oxide film becomes a first insulating film that constitutes a part of the gate insulating film 105 between the floating gate electrode and the control gate electrode.

By the heat treatment for forming the first insulating film, the impurity ions 117 unevenly distributed in the polycrystalline silicon film pattern 118 are further diffused, and the gate oxide film 1 is formed.
03 to the upper part. On the other hand, since the polycrystalline silicon film pattern (especially on the gate oxide film 103) 118 was initially free of impurities, the main portion of the first insulating film and the gate oxide film 103 in the thermal oxidation process were not used. The adverse effects of impurities on silicon have been reduced. For this reason, impurities are partially contained but not included (not included in the above main part).
First insulating film and gate oxide film 103 not affected by impurities
Is obtained.

At this time, the P-type ion implantation layer 120 is simultaneously activated by the heat treatment, and the P-type region 121 is formed. By forming the P-type region 121, the breakdown voltage between elements can be increased.

In FIG. 8F, a silicon nitride film (not shown) having a thickness of, for example, about 10 nm by low pressure vapor deposition (LPCVD) is formed on the first insulating film. For example, a silicon oxide film of about 6 nm is formed on the entire surface. Thus, a gate insulating film 105 composed of a so-called silicon oxide film, silicon nitride film, and silicon oxide film (ONO film) is formed.

In FIG. 9G, a second polycrystalline silicon film 119 is grown on the entire surface, for example, to a thickness of about 150 nm. Further, the second polycrystalline silicon film is doped with, for example, phosphorus. Note that a silicide layer (not shown) may be further formed on second polycrystalline silicon film 119 to reduce wiring resistance.

G, Floating Gate Electrode Forming Step In FIG. 9H, next, the second polycrystalline silicon film 1 is formed.
19, the gate insulating film 105 and the polycrystalline silicon film pattern 118 are sequentially patterned, and the control gate electrode 106 composed of the second polycrystalline silicon film 119 and the floating gate electrode 104 composed of the polycrystalline silicon film pattern 118
Are formed. Next, an interlayer insulating film 109 made of a BPSG film is formed on the entire surface. Next, a contact hole is formed in a predetermined place in the interlayer insulating film 109 (not shown).
For example, an aluminum-based metal film is formed on the entire surface, and the metal film is patterned to form the bit lines 111.

As described above, in the above embodiment, an oxide film and a silicon nitride film are further grown on the polycrystalline silicon film, and the nitride silicon film is patterned. Since the implantation of impurities into the film and the patterning of the polycrystalline silicon film are performed, the number of lithography and the number of steps are not increased, and the reliability is not impaired. Further, since the oxide film is provided on the polycrystalline silicon film, there is no possibility that the impurities are diffused outward even in the step of unevenly distributing the impurities implanted in the polycrystalline silicon film.

[0063]

As described above, according to the present invention, when manufacturing a nonvolatile semiconductor memory device having a floating gate electrode made of a polycrystalline silicon film containing impurities, an oxide film and a nitride film are formed on the polycrystalline silicon film. The number of lithography and the number of steps are increased by further growing a silicon film, patterning the silicon nitride film, and implanting impurities into the polycrystalline silicon film and patterning the polycrystalline silicon film using the nitride film pattern. A desired non-volatile semiconductor memory device can be obtained without performing the above process, and since an oxide film is present on the polycrystalline silicon film in the manufacturing process, the impurity is immediately injected into the polycrystalline silicon film (when a nitride film pattern is present). Even if the heat treatment step is performed in the above-described state, there is no fear that impurities are diffused outward, and the obtained nonvolatile semiconductor memory device Dependable and there is no prejudice to the other functions.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a first embodiment of the present invention.

FIG. 2 is a schematic sectional view of the first embodiment,
1A is a schematic cross-sectional view taken along the line XX of FIG. 1, and FIG.
5 is a schematic sectional view taken along line YY of FIG.

FIGS. 3A to 3C are schematic cross-sectional views of a manufacturing process according to the first embodiment of the present invention, and are schematic cross-sectional views of a portion corresponding to line YY in FIG.

FIGS. 4D to 4F are schematic cross-sectional views of the manufacturing process of the first embodiment of the present invention, following FIGS. 3A to 3C, and taken along line YY of FIG. FIG. 3 is a schematic sectional view of a portion corresponding to FIG.

5 (g) is a schematic cross-sectional view of the manufacturing process of the first embodiment of the present invention, following FIG. 4 (d) to (f), and shows a portion corresponding to line YY in FIG. 1; FIG.

FIGS. 6A and 6B are schematic cross-sectional views of a second embodiment of the present invention, in which FIG. 6A is a schematic cross-sectional view taken along line XX of FIG. 1, and FIG.
FIG. 2 is a schematic sectional view taken along line YY of FIG. 1.

FIGS. 7A to 7C are schematic cross-sectional views of a manufacturing process according to a second embodiment of the present invention, and are schematic cross-sectional views of a portion corresponding to line YY in FIG.

FIGS. 8 (d) to (f) are schematic cross-sectional views of the manufacturing process of the second embodiment of the present invention, following FIGS. 7 (a) to 7 (c). It is a cross section of a portion corresponding to a line.

9 (g) to 9 (h) are schematic cross-sectional views of the manufacturing process of the second embodiment of the present invention, following FIGS. 8 (d) to 8 (f), and FIG. It is a cross section of a portion corresponding to a line.

FIG. 10 is a schematic plan view of a conventional flash memory.

11A and 11B are schematic cross-sectional views of a conventional flash memory. FIG. 11A is a schematic cross-sectional view taken along line XX of FIG.
Is a schematic cross-sectional view taken along line YY.

12A to 12C are schematic cross-sectional views of a conventional flash memory manufacturing process, and are cross-sectional schematic views of a portion corresponding to line YY in FIG.

13 (d) to (f) show (a) to (c) in FIG.
FIG. 11 is a schematic cross-sectional view of a manufacturing step of a conventional flash memory, following FIG. 10, which is a schematic cross-sectional view of a portion corresponding to line YY in FIG. 10.

14 (g) to (h) are (d) to (f) in FIG.
FIG. 11 is a schematic cross-sectional view of a manufacturing step of a conventional flash memory, following FIG. 10, which is a schematic cross-sectional view of a portion corresponding to line YY in FIG. 10.

[Explanation of symbols]

101, 201 P-type silicon substrate 102, 202 Field oxide film 103, 203 Gate oxide film 104, 204 Floating gate electrode 105, 205 Gate insulating film 106, 106a to 106c, 206, 206a to 20
6c Control gate electrode 107ab, 107cd, 207ab, 207cd Source region 108, 208 Drain region 109, 209 Interlayer insulating film 110a, 110b, 210a, 210b Bit contact hole 111a, 111b, 211a, 211b Bit line 112 Polycrystalline silicon film 113 Oxidation Film 114 silicon nitride film 115 photoresist film pattern 116 nitride film pattern 117 impurity ions 118 polycrystalline silicon film pattern 119 second polycrystalline silicon film 120 p-type ion implantation layer 121 p-type region

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (4)

(57) [Claims] 1. A film forming step, an N-type ion implantation step,
A method for manufacturing a nonvolatile semiconductor device, comprising at least a pattern forming step, a pattern removing step, and a floating gate electrode forming step, wherein the film forming step includes forming a field oxide film in an element isolation region on a surface of a P-type silicon substrate. Forming a gate oxide film by thermal oxidation in an element formation region on the surface of the P-type silicon substrate, and sequentially forming a polycrystalline silicon film, an oxide film, and a silicon nitride film on the entire surface. A step of patterning a silicon nitride film on at least the element formation region and on the field oxide film to form a predetermined nitride film pattern, and using the nitride film pattern as a mask, a normal line to the surface of the P-type silicon substrate. The step of performing ion implantation of N-type ion species in parallel to form an ion implantation layer in the polycrystalline silicon film. The oxide film and the polycrystalline silicon film are sequentially patterned using the oxide film pattern as a mask to form a predetermined polycrystalline silicon film pattern. The pattern removing step removes the nitride film pattern and the oxide film sequentially. In the floating gate electrode forming step, a gate insulating film is formed on the entire surface, a conductor film is formed on the entire surface, and the conductor film, the gate insulating film, and the polycrystalline silicon film pattern are sequentially patterned. Forming a control gate electrode made of the conductor film and a floating gate electrode made of the polycrystalline silicon film. 2. A method for manufacturing a nonvolatile semiconductor memory device further comprising a P-type ion implantation step between a pattern forming step and a pattern removing step, wherein the P-type ion implantation step includes masking the nitride film pattern. as a step of implanting P-type ion species in P-type silicon substrate, according to claim 1, wherein after the P-type ion implantation step, the pattern removal step, to carry out each step in the order of the floating electrode forming step
3. The method for manufacturing a nonvolatile semiconductor memory device according to 1. 3. A method for manufacturing a nonvolatile semiconductor memory device further comprising a heat treatment step between an N-type ion implantation step and a pattern formation step, wherein the heat treatment step includes performing a heat treatment at a predetermined temperature. N
Is a step of diffusing an ion-implanted layer formed in the step of ion-implanting and unevenly distributing N-type impurities in the polycrystalline silicon film. After the heat treatment step, a pattern forming step, a pattern removing step, and a floating electrode forming step are performed. 3. The method according to claim 1, wherein the steps are sequentially performed. 4. An N-type ion species implanted into a P-type silicon substrate in the N-type ion implantation step is arsenic (A).
3. The method according to claim 1 , wherein the method is s) or antimony (Sb).