JPS6386190A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To make high speed reading possible by simple constitution by delaying successively data read out in parallel at different delay time and cutting off a data line transmitting preceding by one at the time of outputting data. CONSTITUTION:When row/column address is taken in, data are read out from a memory cell array 11 and sent to data lines L1-Ln through an output buffer. Data sent to the data line L1 are outputted through a switch S1 and an output driver 15. Data sent to the data line L2 are delayed by a specified time by a delay circuit D2. Then, a switch controlling circuit C2 controls the switch S1 and cuts off the data line L1 and outputted from a driver 15. Similar operation is made for data lines L3-Ln. Accordingly, efficient reading can be made at high speed setting output time by the delay time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of high-speed reading of stored data.

(Prior Art) With the recent increase in the capacity of semiconductor memory devices, shortening the access time for reading data stored in the semiconductor memory devices has become an important issue. Therefore, various special functions have been considered to shorten access time.For example, in the case of dynamic memory, functions such as page mode, nibble mode, and static column mode are designed to shorten access time. ing.

Among these functions, the one that can be accessed most quickly is the static column mode. In this static load RAM mode, after reading the first bit in normal operation, bits in the same row can be accessed randomly by simply inputting a column address.The second bit can be accessed only by inputting a column address. The subsequent cycle time is approximately 5
It can be about 0 nanoseconds. However, this value is not sufficient in fields where particularly high-speed access is required, such as image processing.

The page mode is the above-mentioned static column mode with a column address capture clock added, and the second and subsequent column addresses are captured at the falling edge of this clock. Therefore, the cycle time of this page mode is slower than that of the static column mode.

Next is the nibble mode. In this nibble mode, after reading the first bit in normal operation, the following three pits are serially accessed, and the cycle time after the third bit is about 20 nanoseconds. It can be done. However, in this nibble mode, a normal read operation is required every four pits, so the overall speed is not so high.

Recently, an image memory capable of high-speed serial access has been developed for image processing (Reference, Nikkei Electronics, May 20, 1985 issue, pages 195 to 219).

The cycle time when such image memory performs serial access is approximately 40 nanoseconds, which is somewhat faster than the static column mode described above.
It cannot be said that it is sufficiently fast. Furthermore, such image memory is far behind in terms of integration compared to the above-mentioned memory having the three special functions.

In addition, in order to reduce the time required for device evaluation, there are methods that output multiple bits only during device evaluation during the development and manufacturing process, and methods that perform a logical OR of multiple pits inside the device and output it externally. However, these are only effective at the wafer stage and do not allow users to perform high-speed testing after packaging. Furthermore, the method of simultaneously accessing multiple pits inside the device and outputting their logical sum to the outside has a drawback in that it is impossible to determine which address actually corresponds to the bit that is faulty.

(Problems to be Solved by the Invention) The present invention has been made in view of the above points, and an object thereof is to improve the problem of data read time in conventional semiconductor memory devices and read data at high speed. The object of the present invention is to provide a semiconductor memory device that can perform high-speed reading with a simple configuration.

[Structure of the Invention] (Means for Solving the Problems) That is, in the semiconductor memory device according to the present invention,
A plurality of delay means are provided for sequentially delaying data read out in parallel from the memory cell array by different delay times, and when data is output from the delay means,
The delay means includes a plurality of switch means for cutting off data lines transmitting data that precedes the data outputted from the delay means.

(Function) In other words, in a semiconductor memory device equipped with the above-mentioned means, the output time of preceding data is regulated by the delay FR of the data to be transmitted next, and the same Data can be output serially to the external output line at high speed.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a semiconductor memory device that enables high-speed data reading. For example, n pieces of data are read in parallel from a memory cell array 11 made up of a plurality of memory cells. , this read data is outputted via the output buffer 12 from n data lines 1 to ln, respectively. These n data lines are connected to a common output driver 15 via a delay circuit section 13 and a switch circuit group 14, respectively.

The delay circuit section 13 is composed of delay circuits D2 to Dn, and the delay circuits D2, D3, ..., Qn are connected in series to the data lines L2, L3, ..., Ln, respectively. It has become. In this case, the data line L1 is not particularly provided with a delay circuit, and the delay time is set to [zero].

Here, the delay times of the delay circuits D2 to [)n are different from each other, and have the following relationship, for example.

D2 <D3 <---<Dn The switch circuit group 14 includes data lines L1 to Ln-
Switches S1 to 3n-1 that set 1 to a conducting state and 4 to a non-conducting state, respectively, and these switches S1 to S
It is composed of switch control circuits C2 to Cn that control the data lines L2, Cn, respectively.
Connected to L3, . . . , In.

A read start signal is commonly supplied to each of the switches S1 to 3 n-1, and when this read start signal is supplied, the switches S1 to S n-1 connect to the data lines L1 to L n-1, respectively. The signal from 1 is output.

Further, the switch control circuits C2 to Cn are connected to the delay circuit section 1.
The switch S is configured to cut off the data lines L1 to 1n, which are respectively transmitting the data that precedes the detected data by one, when the data output from the terminal 3 is detected.
1 to 5n-1, respectively.

Next, the read operation of the semiconductor memory device will be explained with reference to the timing chart of FIG. In this diagram,
[) Outl, [) 0ut2, . . . , □outn correspond to data IIL1, L2 .

When a row address and a column address are taken in by signals RAS and Xl, n-bit data corresponding to the address value is read from memory cell array 11.

These data are sent to data lines L1 to 1-n via output buffers 712, respectively. The data DO1 sent to the data line L1 is directly output to the outside via the switch S1, which is turned on by the read start signal, and the output driver 15. Further, the data 002 sent to the data line L2 is sent to the switch control circuit C2 after being delayed for a predetermined time by the delay circuit D2.

At this time, the switch control circuit C2 controls the switch $1 to cut off the data line L1. Therefore, when the output data DO1 is aborted, the data DO2 is outputted to the outside via the switch S2 and the output driver 15. Furthermore, since similar operations are performed on the data lines L3 to In, the output driver 1
From 5 onwards, [)On is serially output from data DO1.

Therefore, the output time of data DO1 to [)On is
Since the delay time can be set by each of the delay circuits D2 to Dn, the data output time can be matched to a frequently used external system, and data can be read out at high speed and efficiently.

[Effects of the Invention] As described above, according to the present invention, by including a plurality of delay means each having a different delay time, and a switch means for cutting off preceding data output according to the output from the delay means, Data can be read out at high speed, and if the data output time is determined according to the purpose of use, efficient readout operations can be performed.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram illustrating a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a timing chart illustrating the operation of the semiconductor memory device shown in FIG. 1. 11... Memory cell array, 12... Output buffer, 13... Delay circuit section, 14... Switch circuit group,
15...Output driver.

Claims (1)

[Claims] A memory cell array comprising a plurality of memory cells, in which data from each of the memory cells is read out in parallel, and data read out in parallel from the plurality of memory cells in the memory cell array is transmitted. a plurality of data lines, a plurality of delay means provided in series with each of the plurality of data lines and set so that the delay time becomes longer in sequence, and outputs from each of the delay means to each of the data lines. a plurality of switch means provided on each data line that outputs data; and a plurality of switch controls that detect the output from each of the delay means and control the preceding data line to be cut off by the switch means in the output detection state. and output means for supplying each data transmitted via the plurality of switch means to the same external output line.