JPS6385843A - Control circuit for microprocessor - Google Patents

Abstract

PURPOSE:To sharply improve the processing efficiency of a microprocessor by varying the frequency of a reference clock signal based upon the access time of a peripheral element. CONSTITUTION:The titled circuit is provided with a frequency varying means for varying the frequency of a reference clock signal on the basis of the access time of each peripheral element accessed by a processing means. Namely, an FF 6 is set up by a rise signal outputted from a C input terminal immediately after turning a D input terminal of the FF 6 to a low level, so that a Q output of the FF 6 is turned to a low level, the inverse of Q output is turned to a high level, a reset (R) input of an FF 7 is turned to a high level to release the reset of the FF 7, the frequency of a reference clock signal CK generated from an oscillator 2 is started to be divided into 1/2, and a clock signal CK1 obtained by dividing the frequency of the signal CK into 1/2 is inputted to a clock input CLK of an MPU 1. Thereby, the access time to an external I/O port 5 can be expanded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor that processes data of a peripheral device based on a pre-stored program.

[Conventional technology]

In conventional microprocessors, when there is no function to control read/write timing according to the access time of various external elements, the most accessed peripheral elements such as externally connected memory and input/output boards are The frequency of the microprocessor's clock pulses was lowered to ensure reliable read/write operations even with long-duration devices.

[Problem that the invention seeks to solve]

As a result, the microprocessor cannot operate at its maximum speed, resulting in a significant delay in processing efficiency. Additionally, when trying to operate a microprocessor at maximum speed, peripheral elements with long access times cannot be used, and the system must be configured with expensive peripheral elements with fast access times. .

This invention was made to solve the above problems, and the frequency of the basic clock signal input to the microprocessor for arithmetic processing is varied according to the access time of the peripheral equipment accessed by the microprocessor. The purpose of this invention is to obtain a microprocessor control circuit that can significantly improve the processing efficiency of the microprocessor.

[Means for solving problems]

The microprocessor control circuit according to the present invention is provided with frequency variable means for varying the frequency of the basic clock signal based on the access time of each peripheral element accessed by the processing means.

[Effect]

In this invention, when the processing means accesses a peripheral element, the frequency variable means varies the frequency of the basic clock signal input to the processing means based on the access time of the peripheral element.

〔Example〕

FIG. 1 is a block diagram illustrating a control circuit of a microprocessor according to an embodiment of the present invention, in which numeral 1 denotes a microprocessor main unit (MPU), ROM and RA (not shown).
The basic clock signal CK (same frequency as the highest frequency of MPUI) generated from the oscillator 2 is input to the clock input CLK. A selector 3 selects an external input/output port 4.5 based on address data output from the address boat ADDR. The output ports (OUTI) and 0t7T2 of the selector 3 are connected to the chip select terminals C8 of the external input/output ports 4 and 5. Lead terminal RD of external input/output boat 4.5
and write terminal WT are connected to read terminal RD and write terminal WT of MPU1. 6 is a D-type flip-flop (FF), which operates the oscillator 2 based on the output of the gate circuit 8.
The D-type flip-flop (FF) 7 selects either the basic clock signal CK generated from the basic clock signal CK or the clock signal CK1 obtained by dividing the frequency of the basic clock signal CK into 1/2. Note that the access time of the external input/output boat 4 is synchronized with one cycle of the basic clock signal CK to process data read and write, and the access time of the external input/output boat 5 is synchronized with one cycle of the clock signal CKI. It has the ability to process data reads and writes.

Next, the frequency variable control operation according to the present invention will be explained with reference to FIG.

FIG. 2 is a timing chart illustrating the frequency variable control operation according to the present invention. Components that are the same as those in FIG. 1 are given the same reference numerals.

When the MPU 1 accesses its own built-in elements and the external input/output board 4, the address data that selects the external input/output board 4 based on the address data output from the MPU 1's address board (ADDR) is used as a selector. The input is input to the selector input SEL of the selector 3, and the output capo ()OUTl of the selector 3 becomes high level, chip-selecting the external input/output board 4, and the output capo ()OUTl of the selector 3 becomes low level, so that the gate The input on one side of the circuit 8 becomes a high level (negative logic), and the D input terminal of the FF 6 becomes a high level. At this time,
Since a clock pulse is always input to the C input terminal of FF6, the Q output of FF6 becomes high level, and the FF
Since the inverted Q output of 6 becomes low level and resets FF7, the basic clock signal C generated from oscillator 2
K is output to MPU 1's clock CLK.

Input/output data from the external input/output boat 4 is processed based on this basic clock signal CK.

On the other hand, the address data for selecting the external input/output port 5 based on the address data output from the address port (ADDR) of the MPU 1 is input to the selector input SEL of the selector 3.
, the output port 0UTO of the selector 3 becomes high level to chip select the external input/output board 5, and the output port 0UTI of the selector 3 becomes low level. As a result, the output of the gate circuit 8 has MP
Since signals equal to the read signal and write signal of U1 are output, the D input terminal of FF6 becomes low level. FF
Since FF6 is reset by the rising signal of the C input terminal immediately after the D input terminal of FF6 becomes low level,
The Q output of F6 becomes low level, the inverted Q output becomes high level, the R (reset) input of FF7 becomes high level, the reset of FF7 is released, and the frequency of the basic clock signal CK generated from oscillator 2 is set to 1. At the same time as the frequency division by 1/2 starts, a clock signal CKI obtained by dividing the frequency of the basic clock signal CK by 1/2 is input to the clock CLK of the MPUI. For this reason, external input/output board 5
access time is extended. When the access to the external input/output board 5 is completed, the output terminal of the gate circuit 8 becomes high level, FF6 is set by the rise of the clock signal CKI immediately after that, the Q output of FF6 becomes high level, and the inverted Q terminal becomes low. level, FF7 is reset and the basic clock signal C
K is sent to the clock input CLK of MPU1.

In this way, only when the MPU 1 accesses the external input/output port 5 which requires a long access time.

When a clock signal CKI obtained by dividing the highest clock frequency into 1/2 is input to the clock CLK of the MPUI and accessing an element other than the external input/output board 5, the highest clock frequency (basic clock signal GK) of the MPU1 is input. It will be input to clock input CLK.

In the above embodiment, the case where a peripheral element with a long access time is accessed was explained, but this also applies when the board on which the microprocessor is mounted and the board on which the peripheral element is mounted are different, and the distance between the two boards is long. By applying the invention, it is also possible to extend the access time to provide a large timing margin and prevent malfunctions.

〔Effect of the invention〕

As explained above, the present invention is provided with a frequency variable means for varying the frequency of the basic clock signal based on the access time of each peripheral element accessed by the processing means. In the case of processors as well, it is now possible to dynamically change the operating speed of the microprocessor according to the access time of peripheral elements, even when peripheral elements that process data with a slower access time than the microprocessor are connected. , it has the advantage of significantly shortening the total processing time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a control circuit of a microprocessor according to an embodiment of the present invention, and FIG. 2 is a timing chart illustrating a variable frequency control operation according to the present invention. In the figure, 1 is the MPU, 2 is the oscillator, 3 is the selector, 4, 5
is an external input/output port, 6 and 7 are FFs, and 8 is a gate circuit. 4.5. Outboard input/output boat

Claims (1)

[Claims] In a microprocessor having a processing means for reading a program based on an input basic clock signal and processing input/output data of a plurality of peripheral elements, the above processing is performed based on the access time of each peripheral element accessed by the processing means. A control circuit for a microprocessor, comprising a frequency variable means for varying the frequency of a basic clock signal.