JPS6384941U - - Google Patents

Info

Publication number
JPS6384941U
JPS6384941U JP17895786U JP17895786U JPS6384941U JP S6384941 U JPS6384941 U JP S6384941U JP 17895786 U JP17895786 U JP 17895786U JP 17895786 U JP17895786 U JP 17895786U JP S6384941 U JPS6384941 U JP S6384941U
Authority
JP
Japan
Prior art keywords
electrode pad
conductive adhesive
substrate
groove
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17895786U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0440277Y2 (fr
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17895786U priority Critical patent/JPH0440277Y2/ja
Publication of JPS6384941U publication Critical patent/JPS6384941U/ja
Application granted granted Critical
Publication of JPH0440277Y2 publication Critical patent/JPH0440277Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • H01L2224/05557Shape in side view comprising protrusions or indentations

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP17895786U 1986-11-20 1986-11-20 Expired JPH0440277Y2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17895786U JPH0440277Y2 (fr) 1986-11-20 1986-11-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17895786U JPH0440277Y2 (fr) 1986-11-20 1986-11-20

Publications (2)

Publication Number Publication Date
JPS6384941U true JPS6384941U (fr) 1988-06-03
JPH0440277Y2 JPH0440277Y2 (fr) 1992-09-21

Family

ID=31121578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17895786U Expired JPH0440277Y2 (fr) 1986-11-20 1986-11-20

Country Status (1)

Country Link
JP (1) JPH0440277Y2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007103439A (ja) * 2005-09-30 2007-04-19 Optrex Corp 半導体集積回路

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4023089B2 (ja) * 1999-03-31 2007-12-19 セイコーエプソン株式会社 狭ピッチ用コネクタ、静電アクチュエータ、圧電アクチュエータ、インクジェットヘッド、インクジェットプリンタ、マイクロマシン、液晶装置、電子機器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007103439A (ja) * 2005-09-30 2007-04-19 Optrex Corp 半導体集積回路
JP4739895B2 (ja) * 2005-09-30 2011-08-03 オプトレックス株式会社 半導体集積回路

Also Published As

Publication number Publication date
JPH0440277Y2 (fr) 1992-09-21

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