JPS6384325A - Echo eliminating device - Google Patents

Abstract

PURPOSE:To suppress increase of remaining echoes caused by phase jump by adding and actuating a correcting adaptive filter for a fixed period of time form a time point when a phase jump occurs. CONSTITUTION:A correcting adaptor filter 18 works to decrease the number of taps one by one every fixed time from a time point when a phase jump occurs until these taps are cut down just to a single piece. Then the echo replica corresponding to increase of remaining echoes caused by phase jump is produced by the filter 18 and supplied to an adder 19 to be added with the output of an adaptive filter 10. Therefore an echo replica corresponding to a phase jump if occurs is obtained with the output of the adder 19. The output of the adder 19 is supplied to a subtractor 6 via a PCA 11 and subtracted from the output of an LPF 5. Thus it is possible to suppress increase of remaining echoes caused by the phase jump.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an echo cancellation device for realizing two-wire bidirectional digital transmission.

[Conventional technology]

Echo canceller is known as a well-known technology for realizing two-wire bidirectional digital transmission using bare wire as a medium (IEE Transactions on
Acoustisox Speech and Signal Processing (IEEETRANSACTTONS)
ON ACOtlSTIC3,5PEECHAND
5IGNAL PROCESSING) Volume 27, No. 6,
1979. pp. 768-781).

The echo canceller is a 2-wire/4-wire conversion circuit that generates a pseudo echo (echo replica) corresponding to the transmitted data series using an adaptive filter with a tap coefficient equal to the length of the echo impulse response. It operates to suppress echoes leaking from the transmitting circuit to the receiving circuit. At this time, each tap coefficient of the adaptive filter is
It is successively corrected by correlating the difference signal obtained by subtracting the echo replica from the mixed signal in which the echo and the received signal are mixed and the transmitted data. Convergence algorithms for modifying the coefficients of such adaptive filters are described in the above-mentioned literature, and a representative example is the Stochastic Iteration Algorithm (Stoch
astic Iteration Algorithm
) and Sign Algorithm
hm) is known.

FIG. 4 shows a conventional example of an echo canceller employing the stochastic iteration algorithm. Here, it is assumed that the circuits shown in FIG. 4 are connected oppositely via a two-wire transmission line 4. If the target cable is a subscriber cable, one is installed on the central office side and the other on the subscriber side.

Here, baseband transmission is assumed to simplify the explanation.

As shown in FIG. 4, the circuit in FIG.
ADC) 12, a multiplier 13, an adaptive filter 10,
A D/A converter (DAC) 11 is provided.

The adaptive filter 10 operates upon receiving a transmission data sequence, and this adaptive filter 10. D/A converter 1
1. Subtractor 6. The A/D converter 12 and the multiplier 13 form a closed loop, in which echo cancellation is performed as described later.

Further, as shown in FIG. 4, there is provided a circuit 7 to which the output of the subtractor 6 is applied, a clock extraction circuit 14 to which the output of the circuit 7 is supplied, an oscillator 15, and a digital phase lock loop. (DPL L) 16, a timing signal generation circuit 17, and a demodulator 8 to which the output of the output device 7 is supplied.

In FIG. 4, 1 indicates an input terminal and 9 indicates an output terminal.

In FIG. 4, a binary data sequence is supplied to an input terminal 1, and this is input to a transmitter 2 and an adaptive filter 10. After the binary data series is converted into a transmission line code in the transmitter 2, it is sent out to a two-wire transmission line 4 via a hybrid transformer (HYB) 3. On the other hand, a part of the transmission signal generated by the transmitter 2 appears as an echo component at the output of the hybrid transformer 3 and is supplied to the low-pass filter 5. In addition, the received signal sent from the other side opposite to the circuit shown in FIG.
The signal is supplied to a low-pass filter 5 via a transformer 3.

Therefore, the output of the low-pass filter 5 becomes a mixed signal containing a received signal and an echo. Note that the role of the low-pass filter 5 is to suppress frequency components outside the desired signal band. The output of the low pass filter 5 is supplied to a subtracter 6. Here, adaptive filter 10. D/A converter (DAC)11. Subtractor 6. A closed loop circuit consisting of an analog-to-digital converter (ADC) 12 and a multiplier 13 operates to remove echoes in the mixed signal that is the output of the low pass filter 5. This is the adaptive filter 10
is realized by generating echo replicas. Here, the adaptive filter 10 will be explained in detail.

FIG. 5 shows detailed blocks of the adaptive filter 10 of FIG. 4. Input signal S, in FIG. , and S. , are the binary data series supplied from input terminal 1 in Fig. 4 (assumed to take a value of ±1).
and the output of the multiplier 13. Further, the output signal S1°5 in FIG. 5 is output from the adaptive filter 10 in FIG.
It corresponds to the output signal of

The adaptive filter 10 includes a delay element 1 as shown in FIG.
001 to 100N, . . ., the coefficient generation circuit AI-AN, the multipliers 1011 to 101N, and each of the multipliers 101.
It is constituted by an adder 102 to which an output of ~101N is supplied.

The delay time of each of the delay elements 1001 to 100□1 is set to a constant delay time T seconds.

In FIG. 5, the binary data series S1.3 is transmitted through the delay elements 100. , multiplier 101. and is supplied to the coefficient generation circuit A1. Delay element 100+ providing a delay of T seconds.

100g,..., 100. -, are connected in this order, and each of them can be realized by a flip-flop. The section composed of these delay elements is called the input data processing section. Here, N is an integer of 2 or more, and the binary data series SI. , the data rate is 1. /T bits/second. Delay element 100i (+=
1. ..., N-1) are respectively output from the multiplier 101.
．． . , and coefficient generation circuit A. 1. In the multiplier 101J (j=1...,N), the coefficient generation circuit A
After the input data is multiplied by the tap coefficient that is the output of J, all the multiplication results are input to the adder 102 and added, and an echo replica 3105 is output. Note that the input signal S
1 degree, N coefficient generation circuits A + , A 2.・
..., is supplied to AN.

Next, the coefficient generation circuit will be explained in detail.

FIG. 6 shows the coefficient generation circuit A+ (i=1°2, . . .
. , N). The input signal szoo in FIG. 6 is the binary data series S1°3 or the delay element 1001.100□ in FIG.

..., corresponds to an output signal of 100N-1. Furthermore, the input signal S2° in FIG. 6 corresponds to the input signal S1°4 in FIG. Furthermore, the output signal S2°2 in FIG. 6 is generated by the coefficient generation circuit A in FIG.

It corresponds to the exit no j.

The coefficient generation circuit A1 includes a multiplier 203 as shown in FIG.
, an adder 204, and a delay element 205,
The delay time of delay element 205 is set to T seconds.

In FIG. 6, the input signal S2°. and S2°1 are supplied to a multiplier 203, and the multiplication result becomes one input of an adder 204. The output of adder 204 is T seconds delay element 2.
The coefficients are updated every T seconds through the input signal S2° that is fed back to the multiplier 203. This is realized by adding the correlation value of S2°1 and the coefficient value of 1 second ago. The output signal S2°2 of the delay element 205 becomes a coefficient.

The echo replica generated by the adaptive filter 10 of FIG. 4, which has been explained above with reference to FIGS. 5 and 6, is
The signal is supplied to the A converter 11, where it is converted from a digital signal to an analog signal, and becomes one input of the subtracter 6. The subtracter 6 subtracts the echo replica from the mixed signal (-[echo] + [received signal]), which is the output signal of the low-pass filter 5, and produces a difference signal (-[residual echo] + [received signal],
However [? echo] = (echo) - [echo replica]
) is obtained and supplied to the equalization layer 7 and the A/D converter 12. The A/D converter 12 converts the difference signal output from the subtracter 6 from an analog signal to a digital signal. Furthermore, the output of the A/D converter 12 is
After being multiplied by 2α (α is a constant) in Step 3, the signal is supplied to the adaptive filter 10 as an error signal. Note that the input signal S1° in FIG. 5 corresponds to the error signal.

In FIG. 4, after the line characteristics are equalized by the equalization layer 7, the signal is returned to a binary data series by the demodulator 8 and supplied to the output terminal 9. On the other hand, the output signal of the equalization layer 7 is supplied to a clock extraction circuit 14, and a clock component is extracted from the received signal.

The clock extracted by the clock extraction circuit I4 is connected to a digital phase lock loop (DPLL) 16.
supplied to The output of the oscillator 15 is also supplied to the DPLL 16, and the phase of the clock obtained by appropriately dividing this output and the clock extracted by the clock extraction circuit 14 is compared. For the output clock of the oscillator 15, so as to follow the clock phase extracted from the received signal,
Insertion and omission of pulses for one clock are performed. DPL
The output of L16 is supplied to a timing signal generation circuit 17, which generates various timing signals required by each section in FIG.

[Problem that the invention seeks to solve]

Here, when the circuit of FIG. 4 is installed on the station side, the output of the timing generation circuit 17 is only supplied to the demodulator 8, and the output of the timing generation circuit 17 is only supplied to the transmitter 2. The adaptive filter 10° D/A converter 11 and A/D converter 12 are supplied with various timing signals generated by a highly accurate clock.

On the other hand, if the circuit shown in FIG. 4 is installed on the subscriber side, it is necessary to send data in synchronization with the clock system extracted from the received signal, so the timing signal generation circuit 17 Not only the demodulator 8 but also the transmitter 2.
Adaptive filter 10. D/A converter 11 and A/
Necessary timing signals must also be supplied to the D converter 12. However, since it is necessary for the DPLL 16 to follow the timing phase of the received signal, the various timing signals output from the timing signal generation circuit 17 cause a phase jump corresponding to one clock of the oscillator 15. When the adaptive filter 10 is operated using a timing signal that causes such a phase jump, there is a drawback that when a phase jump occurs, residual echo increases, resulting in a short transmission distance. Also,
As a conventional technique to solve this drawback, a method of suppressing clock jitter using an analog PLL is known, but it requires a VCXO (voltage controlled oscillator) and an analog circuit, which increases the hardware. However, there has been a problem that it is not suitable for LSI integration.

SUMMARY OF THE INVENTION An object of the present invention is to provide an echo cancellation device that can suppress an increase in residual echo caused by timing phase jumps.

Another object of the present invention is to provide an echo canceling device that has a small hardware scale and is suitable for LSI implementation.

[Means for solving problems]

The present invention provides an echo removal device for removing echoes leaking from a transmitting circuit to a receiving circuit, including: a first adaptive filter that operates upon receiving a transmitted data sequence; An adaptive filter is supplied with an operating clock from a clock generation source together with an adaptive filter, and if a phase jump occurs in the clock, the number of taps is increased by one tap at a fixed time interval from the time the phase jump occurs. while decreasing 1
It is characterized by comprising: a second adaptive filter that operates until a tap is reached; and means for adding the outputs of the first and second adaptive filters to obtain an echo replica.

[Effect]

In the present invention, an adaptive filter for correction is separately prepared to generate an echo replica corresponding to the increase in residual echo caused by the jump in the clock phase, and the adaptive filter is used for a certain period of time from the time when the jump in the phase occurs. By operating the adaptive filter for correction, an increase in residual echo is prevented.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, functional blocks given the same reference numbers as in FIG. 4 have the same functions as in FIG. 4.

As shown in FIG. 1, this circuit also includes a transmitter 2, a hybrid transformer (HYB) 3 connected to a two-wire transmission line 4,
Low-pass filter 5, subtracter 6, A/D converter 12
, multiplier 13, adaptive filter 10, D/A converter 1
1, an equalization layer 7, a demodulator 8, a clock extraction circuit 14, an oscillator 15, and a timing signal generation circuit 17, which are similar to those shown in FIG.

The difference between FIG. 1 and FIG. 4 is that a correction adaptive filter 18 and an adder 19 are added, and with these additional functions, the DPLL 16 allows a clock phase jump. A phase jump occurrence display signal Sho indicating the time at which the phase jump occurred and a phase lag/advance display signal S2+ indicating whether the phase jump corresponding thereto is delayed or advanced are supplied to the correction adaptive filter 18. Further, the output of the multiplier 13 is supplied not only to the adaptive filter 10 but also to the correction adaptive filter 18, and is used to update the tap coefficients.

The adder 19 adds the outputs of the adaptive filter 10 and the adaptive filter for correction 18 to obtain an echo replica, and the adaptive filter 10 and the adaptive filter for correction 18 operate upon receiving the transmission data sequence from the input terminal 1. However, regarding the adaptive filter 10 and the correction adaptive filter 18, when a phase jump occurs in the clock that operates these adaptive filters 10.18, the adaptive filter 10 is completely different from when no phase jump occurs. In contrast, the correction adaptive filter 18 operates by decreasing the number of taps by 1 tap at fixed time intervals from the time when the phase jump occurs until the number of taps becomes 1 tap.

That is, the adaptive filter 10 shown in FIG. 1 can be realized with exactly the same configuration as the adaptive filter 10 shown in FIG. 4, which shows a conventional example. On the other hand, the correction adaptive filter 18 shown in FIG. 1 has the role of generating an echo replica corresponding to the increase in the residual echo generated due to the clock phase jump. The internal configuration is slightly different from that of the adaptive filter 10, which always operates regardless of the filter.

FIG. 2 shows an example of the input data processing section of the correction adaptive filter 18 shown in FIG. 1, and the other parts are completely the same as the configuration shown in FIG. 5. In FIG. 2, functional blocks or signals given the same reference numbers as in FIG. 5 have the same meanings. In FIG. 2, the phase jump occurrence display signal SZO is transmitted through the delay element 10
6. , OR element 1071.1.07□,..., 1
07N-+ and is input to AND element 1091. Delay element 106, providing a delay of T seconds.

106□, 106:,..., 106N-z and 106N- are the OR elements 1071 in this order, respectively.
．． 107□, 1073. ....

Each delay element 106 is connected via 107N-□.
The outputs of i (i=1.2..., N-1) are each input to one of the OR elements 107□, and the output of the delay element 106N-1 is also input to the OR element 107N-1. On the other hand, it is supplied as human power. Each logical sum element 107
4 (t = 1. 2. . . , N-1), a phase jump occurrence display signal 320 is commonly input as the other input. Furthermore, the phase jump occurrence display signal S
2° is supplied as one input of the AND element 1091, and at the same time, each OR element 1.07+ (i-1, 2
, . . . , N-1) are respectively output from AND elements 109.
4. , is supplied as one input of . On the other hand, the binary data series S1° has a delay element of 100° and a multiplier of 1
081 is input. Delay element 10 providing a delay of T seconds
01.1002.100i,..., 100N-+
are connected in this order, and each output is multiplier 1
0 days. , 1083.1084. ..., 108N is supplied.

Here, multiplier 108+, 1.08□, ..., 10
This is a multiplier that multiplies by +1 or -1, and whether to multiply by +1 or -1 is determined by the phase delay/lead display signal 321 input manually as a common control signal. Note that since it is assumed that the binary data series S+o3 takes a value of +1 or -1, the multiplier 108+ (i =
1. 2. . . , N) can be realized simply by an exclusive OR element. Multiplier 108+ (i
= 1. 2. ..., N) is output from the AND element 10
91 will become the other human power. Multiplier 108i (i=1.2
．． ..., N) and the output of the AND element 109□ are combined as 2-bit data indicating three values.
data D.

Here, it is assumed that the N pieces of output data D correspond to the N pieces of output data outputted in FIG. 5 in order from the left side of the figure.

Next, the operation of the circuit shown in FIG. 2 will be explained in detail with reference to the timing chart shown in FIG.

FIGS. 3(a) and 3(b) show the timing of the phase jump occurrence display signal S2° and the phase delay/advance display signal Sol, which are the input signals shown in FIG. 2, respectively.

FIG. 3(a) shows that a jump in the clock phase occurs when the signal is "1". Correspondingly, Figure 3 (b
). Therefore, the change point in Fig. 3(b) is the change point in Fig. 3(a).
) coincides with the rising edge of the pulse shown in ( ). On the other hand, FIGS. 3(c), (d), (e) and (f) show the OR element 107. , 107□, 107N-2 and 107N
−.

This figure shows a timing chart of the output signal of .

All of these become "1" at the rising edge of the pulse shown in FIG. 3(a), each for 2T seconds.

3T seconds, (N-1) ・Between T seconds and NT seconds"
After holding "1", it becomes "0". Therefore, in FIG. 2, AND elements 109+, 109□, 109.,
....

The outputs of 109N-+ and 109N are T seconds and 2T seconds after the clock phase jump occurs, respectively.

3T seconds, ..., (N-1) ・Since "1" is held for T seconds and NT seconds and becomes "0" except during this period, the correction adaptive filter 18 in FIG. From the time when the clock phase jump occurs, it operates as an N-tap adaptive filter for T seconds, and as an (N-1) tap adaptive filter for the next T seconds, and further increases the number of taps by 1 tap every T seconds. decreases, and after N·T seconds, the correction adaptive filter 1
8 stops its operation. The cessation of filter operation lasts until the next clock phase jump occurs.

The reason why the correction adaptive filter 18 operates while changing the number of taps is as follows. Assuming that the time at which the clock phase jump occurs is t-1o, in FIG. 1, t≧1. The echo being output from the low-pass filter 5 for the time 1<1 at the transmitter 2
It is divided into a first echo component resulting from the transmission signal generated at time 0 and a second echo component resulting from the transmission signal generated at time t>to. On the other hand, since the echo replica generated by the adaptive filter 10 operates at a timing after the clock phase jumps at time t≧t0, the first echo component is suppressed as desired, whereas the first echo component is suppressed as desired. The echo component No. 2 has a phase difference of one clock with the echo replica, making it impossible to obtain the desired degree of echo suppression. The correction adaptive filter 1B plays the role of compensating for this increase in residual echo, and the time t is 1
=10, the data related to the second echo component decreases by one every T seconds, so the number of taps of the correction adaptive filter 18 decreases every T seconds from the time 1=10. It is necessary to do so.

In this way, when a phase jump occurs in the clock that operates the adaptive filter 10.18, the echo replica corresponding to the increase in residual echo generated due to the clock phase jump is generated by the correction adaptive filter 18. is generated and supplied to an adder 19, where it is added to the output of the adaptive filter 10. Therefore, even when a clock phase jump occurs, an echo replica corresponding to the jump in the clock phase is obtained at the output of the adder 19, and the output of the adder 19 is sent to the subtracter 6 via the D/A converter 11. The echo is removed by subtracting it from the output of the low-pass filter 5.

In this way, according to the configuration shown in FIGS. 1 and 2, when removing echoes leaking from the transmitting circuit to the receiving circuit on the 4-wire side of the 2-wire/4-wire conversion circuit, the transmitted data series The adaptive filter 10 and the adaptive filter for correction 18 are operated by the adaptive filter 10 and the adaptive filter for correction 18, and the adaptive filter 10 and the adaptive filter for correction 18 are operated. When a phase jump occurs in the clock to be used, the adaptive filter 10 performs exactly the same operation as when no phase jump occurs, whereas the correction adaptive filter 18 operates from the time when the phase jump occurs. - By configuring the device to operate while decreasing the number of taps by one tap at regular intervals until the number of taps reaches one, it is possible to prevent an increase in residual echo caused by jumps in the clock phase. Therefore, there is no problem with the increase in residual echo when a jump in the clock phase occurs as in the conventional case, and the adder 19 outputs an echo corresponding to the increase in residual echo caused by the jump in the clock phase. Since the output containing the replica is taken out and fed to the subtracter 6 to remove the echo, the DPL
Even if the echo canceller is operated with various timing signals generated by the clock generated in L16, a desired degree of echo suppression can be ensured.

In addition, a jump in clock phase is caused by clock insertion and drop of one clock, resulting in a phase delay and lead of one clock, respectively. In this case, the clock phase is caused by a delay jump and a lead jump. Since each increase in the residual echo has approximately the same absolute value and opposite polarity, by utilizing this fact, it is possible to halve the capacity of the coefficient memory of the correction adaptive filter 18.

Furthermore, there is no need to use an analog PLL as in the past, and the correction adaptive filter 18 can be constructed from a digital circuit like the adaptive filter 10, and the hardware is small in scale. It's over.

Although the number of taps of the adaptive filter [O] and the maximum number of taps of the correction adaptive filter 18 have been described as N, they may be different. Generally, the latter value is much smaller than the former.

It is also possible to insert an A/D converter between the low-pass filter 5 and the subtracter 6 in FIG. 1, and to implement all subsequent processing by digital processing. At this time, D/A
Converter 11 and A/D converter 12 become unnecessary.

〔Effect of the invention〕

As described in detail above, according to the present invention, an adaptive filter for correction is added to generate an echo replica corresponding to an increase in residual echo caused by a clock phase jump, thereby preventing an increase in residual echo. Therefore, even if the echo canceller is operated with a timing signal that causes a jump in the clock phase, it is possible to ensure the same degree of echo suppression as when the jitter of the timing signal is sufficiently suppressed.
It becomes possible to extend the transmission distance. Furthermore, since the adaptive filter for correction can be realized entirely by digital circuits, it also has the advantage of being suitable for LSI integration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a detailed block diagram of an example of the input data processing section of the adaptive filter for correction shown in FIG. 1, and FIG. 3 is a block diagram for explaining the operation. FIG. 4 is a block diagram showing a conventional example; FIG. 5 is a detailed block diagram of the adaptive filter shown in FIG. 4; and FIG. 6 is a diagram showing the coefficient generation circuit shown in FIG. 1...Input terminal 2...Transmitter section 3...Hybrid transformer 4...
・・2-wire transmission line 5・・・・・Low pass filter 6・・・・・Subtractor 7・・・Others 8・・・Demodulator 9 ......Output terminal 10...Adaptive filter 11...D/A converter 12...A/D converter 13.101. ~101N, 108. ~108N,
203... Multiplier 14... Clock extraction circuit 15... Oscillator 16... Digital phase lock loop 17...・Timing signal generation circuit 18...
...Correction adaptive filters 19, 102, 204...
・Adder 100I to 100N-1, 106, to 106N-+,
205...Delay element

Claims (1)

[Claims] (1) An echo canceling device for removing echo leaking from a transmitting circuit to a receiving circuit, comprising: a first adaptive filter that operates upon receiving a transmitted data sequence; It is an adaptive filter in which an operating clock is supplied from a clock generation source along with the filter, and if a phase jump occurs in the clock, the number of taps is decreased by one tap at a fixed time interval from the time the phase jump occurs. while letting 1
An echo removal device comprising: a second adaptive filter that operates until a tap is reached; and means for adding the outputs of the first and second adaptive filters to obtain an echo replica.