GB2102255A

GB2102255A - Two-wire line for digital communication

Info

Publication number: GB2102255A
Application number: GB08214410A
Authority: GB
Inventors: Peter Wildenauer; Siegbert Hentschke
Original assignee: International Standard Electric Corp
Current assignee: International Standard Electric Corp
Priority date: 1981-05-22
Filing date: 1982-05-18
Publication date: 1983-01-26
Also published as: BE893274A; DE3120434A1; AU8381682A; SE8203102L; SE447619B; CH657241A5; GB2102255B; AU549938B2

Abstract

In duplex digital communication over a two-wire line 9, the signal components in the received signal due to crosstalk and echoes of the signal from one's own transmitter 1 are compensated by an adaptive digital filter (10) which includes the parallel arrangement of an adaptive digital transversal filter (11) and an adaptive recursive filter (12), the sum of their output signals (A, B) being the compensating signal. The setting of the recursive filter is decoupled from the setting of the transversal filter, and steps are taken to reduce the extent to which compensation is affected by a counter-signal. In one embodiment a TDM circuit enables the transversal filter to be operated in sections, the sections operating at a reduced rate. <IMAGE>

Description

SPECIFICATION Two-wire line for digital communication The invention relates to an arrangement for connecting a data source (transmitter) and a data sink (receiver) to a two-wire line, in which echo cancellation is needed. One such arrangement is known from Frequenz 34 (1980) No. 2, pp. 40 to 45. The adaptive digital filter described therein consists of an adaptive transversal filter. In this arrangement, the adaptation may sometimes be affected by a signal received by the distant station, so that compensation is insufficient. Moreover, for a transversal filter, the length of the echo which can be compensated, depends on the number of coefficients, and is thus much restricted. Longer echos, therefore, can only be completely compensated when the number of filter coefficients is considerably increased.

It is an object of the invention to provide a facility of the above kind, which permits an' improved compensation of the interfering signal caused by the own source signal, by providing a quick as possible adaptation.

According to the invention there is provided an arrangement for connecting a source and a sink to a two-wire line for digital communication using duplex operation, with a hybrid circuit and an adaptive digital filter which, from the source signal, derives a compensating signal to suppress the interference signal which, due to the own source signal, is caused in the sync signal, with the adaptive digital-filter coefficients being iteratively adjusted in dependence upon an error signal representing the non-suppressed interference-signal component, the adjusting values for adjusting the individual filter' coefficients equalling a function of a sum of correlation products formed over a defined number of clock intervals, in which the adjusting values are formed by the multiplication of signals derived from tapped signals of the digital filter, by a function of the error signal, and in which the adaptive digital filter includes the parallel arrangement of an adaptive digital transversal filter and of an adaptive ditigal recursive filter, with the sum of the output signals thereof, representing the compensating signal.

Embodiments of the invention will now be described with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of an arrangement embodying the invention; Fig. 2 is one example of the compensation circuit 4, of Fig. 1; Fig. 3 is a second example of the compensation circuit 4, of Fig. 1, in which an error difference correlation is performed; Fig. 4 shows an advantageous example of transversal filter usable in Fig. 1, in which an error difference correlation is performed; Fig. 5 shows the transversal filter of Fig. 4, with one time-division multiplex circuit each being provided for the error signal function and for the compensating signal, and Fig. 6 shows an example of the adjusting circuits of Figs. 2, 3, 4 and 5.

The arrangement as shown in Fig. 1, for connecting a source 1 and a sink 2 to a two-wire line, consists essentially of a hybrid 3 and of a compensation circuit 4. The source 1 may be a data source or a source for digitized speech signals, such as a PCM coder. The same applies to the sink 2. The source 1 is connected via a send filter 6 to the hybrid 3. This send filter 6 restricts the band-width of the transmitter signal in the upward direction, and thus brings the digital source signals into a form suitable for transmission over the two-wire line. The hybrid 3 is connected to the two-wire line 9 over which the single-frequency duplex transmission of messages is effected between the terminal shown and the distant terminal station (not shown).

The sink branch of the hybrid 3 feeds a sampleand-hold device 8, whose output is coupled to the non-inverting input of a subtractor 7 implemented with an operational amplifier. The sample-andhold device includes a receive filter (not shown) which suppresses the high-frequency components incorporated into the receiver signal. The output of the source 1 is coupled to the input of a digital filter 10 having an adaptive co-efficient adjustment and which, according to the invention, consists of the parallel arrangement of an adaptive transversal filter 11 and of an adaptive recursive filter 12. The arrangement of a recursive filter in parallel with the transversal filter serves to enlarge the length of the echo which is capable of being compensated, with respect to the length as restricted by the transversal filter.

The second input signal to the digital filter 10 which, like the first input signal, is applied in parallel to the inputs of both the filters 11 and 12, is the output signal of an analog-to-digital converter 13, which, at its input, receives the analog-compensated sink signal from the output of the subtractor 7. The converter 1 3, in the most simple case may be a one bit A/D converter, i.e., a comparator. The output signals A and B of both the filters 11 and 12 is combined by a digital adder 14 to form the compensating signal. This compensating signal controls a digital-to-analog converter 1 5 whose output is coupled to the noninverting input of the subtracter 7.Thus from the sum signal in the sink branch, which contains the unwanted interfering signal, the subtracter 7 subtracts the output signal of the digital filter 1 0.

The latter is assumed to be a simulation of the interfering signal to be compensated, so that when full compensation has been achieved, only the desired receive signal is left over.

The interfering signal is composed of the crosstalk components of the terminal's own send signal, which, via the hybrid circuit 3 reaches the receive path, and of delayed echos due to reflections of the send signal, from the more distant line impedance mismatches. If incomplete compensation is achieved, the receive signal or intelligence signal as appearing at the output of the subtracter 7, has superimposed on an error signal which, as it originated with the source signal, is correlated therewith. This error signal serves to adjust the filter coefficients of the filter 10.

For the adaptive recursive filter, hereinafter briefly referred to as the recursive filter, two different types are shown in Figs. 2 and 3. The modules shown in addition to the dashline-framed recursive filter 12, are essentially already contained in Fig. 1, and thus do not need any separate explanation in connection with Figs. 2 and 3.

In both arrangements, the recursive filter consists of two filter sections of which the one contains a recursive loop 21, 22, 23, and of which the other one contains a multiplier 24. In Fig. 2, the recursive loop is ahead of the multiplier while in Fig. 3 this sequence has been reversed. A further, essential difference is still to be described.

At first we describe the recursive filter of Fig. 2.

The reference signal, which is identical to the source signal, is applied within the recursive filter 12 to an adder 21 whose output is connected to a delay element 22. The output signal of the adder 21 which, in the delay element 22, is delayed by one clock period, is multiplied by a filter coefficient a in a multiplier 23 whose output is connected to a second input of the adder 21, the adjustment of the filter coefficient a being described below.

Thus, the first filter section contains a recursive filter loop consisting of the adder 21, the delay element 22 and the multiplier 23.

The output signal of the first filter section is applied from the adder 21 to the one input of a multiplier 24 forming part of the second filter section. The output of this multiplier 24 supplies the recursive filter's contribution B to the compensating signal. To the other input of the multiplier there is applied the filter coefficient b of the second filter section, by which the input signal to be filtered, is multiplied. In adjusting circuits 25 still to be described hereinafter with reference to Fig. 6, the values of both filter coefficients are changed each time after a preset number of clock periods. For this purpose, the adjusting circuits use correlation products formed in accordance with the clock timing of the recursive filter, in multipliers 26 and 27.For this, the multipliers 26 and 27 multiply one function of the error signal (superimposed on the intelligence signal) by a signal derived from the output signal of the recursive filter or else from the output signal of the first filter section.

In the filter of Fig. 2, the function of the error signal is the error signal as digitized in the analogto-digital converter 1 3. Relative thereto, it should be noted that the receive signal is each time one sampling value of the digital signal as sampled in the sample-and-hold device 8 (Fig. 1) as received from the two-wire line.

The signal which, to adjust the coefficient a, is to be multiplied by the function of the error signal in the multiplier 26, is derived from the output of the recursive filter and passed through a delay element 28 effecting a time delay byj clock periods of the transversal filter 11, withj indicating the filter degree of the transversal filter 11. Moreover, this signal passes through a recursive loop consisting of an adder 29, a delay element 30 with a one clock period delay time, and a multiplier 31. The output signal of the adder 29 which is delayed by one clock period in the delay element 30, and multiplied by a variable coefficient in the multiplier 31, is added to its input signal, and the adder output signal as delayed by one clock period in the delay element 30, is the input signal of the multiplier 26, which is multiplied by the function of the error signal.The variable coefficient as used in the multiplier 31, is the respective available filter coefficient a of the first filter section.

The signal which, for adjusting the coefficient b of the second filter section, is to be multiplied by the function of the error signal in the multiplier 27, is the output signal of the first filter section.

This is delayed byj clock periods of the transversal filter 11 in a delay element 32,jays mentioned above, being the filter degree of the transversal filter 11.

The delay elements 28 and 32 decouple the setting of the recursive filter 1 2 from the setting of the transversal filter 11. The setting of the filter 11, however, depends on the setting of the filter 12, which is of advantage with respect to the setting of the entire digital filter.

To decouple the setting of the recursive filter 12 from that of the transversal filter 11, the tapped signals of the recursive filter are so delayed in the delay elements 28 and 32, that they appear outside the "window" covered by the transversal filter. For this purpose, the delay time must be equal toj clock periods of the transversal filter, with one clock period meaning the delay between two successively-following tapped signals of the transversal filter.

With respect to the length of the clock period, one must distinguish between two cases. In the normal case, the transversal filter 11 is operated in the same timing as the recursive filter 12, i.e., in the sampling cycle of the sample-and-hold device 8 (Fig. 1), so that one clock period of the transversal filter equals one sampling cycle period.

Hence, the delay of the delay elements 28 and 32 is indicated by Z-i, as Z-' means a delay by one sampling-cycle period.

However, if the filter 11 differs from conventional transversal filters by a multiplex arrangement still as in Fig. 5, then the delay between two successively-following tapped signals equals one bit period. Thus it is equal to n sampling-cycle periods, where n indicates the number of sampling operations per bit. A delay by j clock periods of the transversal filter which, as already mentioned, is necessary, is indicated in this case in the drawings by Z-nj, as Z-1 implies a delay by one sampling period.

A recursive filter and a transversal filter in which one does not do an error correlation as described above, but an error difference correlation, are shown in Figs. 3 and 4. These arrangements are of particular advantage for binary-coded digital signals, since especially for binary-coded signals, the compensation by a countersignal is affected to a particularly strong extent, and because this disadvantage can be overcome by an error-difference correlation.

Next, we describe the recursive filter of Fig. 3.

As already mentioned, with the recursive filter 12 of Fig. 3, the filter section containing the multiplier 24, is ahead of the filter section containing the recursive loop 21,22,23. Compared with Fig. 2, this change simplifies the circuit for processing binary-coded signals. An explanation of the processing of the reference signal in the filter sections may be omitted at this point, as such an explanation has already been given for Fig. 2.

The filter coefficients a and b, in this case also, and again each time after a preset number of clock periods, have their values changed in adjusting circuits 25 to be described later, see Fig. 6. To make available the correlation products needed, there are multipliers 40 and 41 which multiply a function of the error signal by a signal derived from a filter tapping signal. In this recursive filter the signal to be multiplied by the function of the error signal, comes for both multipliers 40 and 41, from the same tapped signal, i.e., from the filter output signal (or the output signal of the filter section including the recursive loop). This tapped signal is again delayed in a delay element 42 byj clock periods of the transversal filter, so that the setting of the recursive filter 12, as explained in connection with Fig. 2, is decoupled from that of the transversal filter 11.

From the delay element 42, the tapped signal passes through a difference former consisting of an adder 43 and of a one clock period delay element 44. The adder subtracts from each value of the tapped signal the value preceding in the delay element 44 by one clock period. This difference forming from successive tapped signal values is of great importance to the error difference correlation.

The output signal of the difference former 43, 44 is the signal to be multiplied in the multiplier 40, by the function of the error signal, and from which there is derived the signal to be multiplied in the multiplier 41 by the function of the error signal. The derivation is so effected that the outpu signal of the difference former 43, 44 passes through a recursive filter loop 45, 46, 47 corresponding to the filter loop 29, 30, 31 of Fig.

2, and whose filter coefficient again is the filter coefficient a of the filter section including the recursive loop 21, 22, 23.

Since the signal to be multiplied by the errorsignal function, as explained above, is produced in this recursive filter by difference forming, the error-signal function, must be a function due to a difference forming process. The forming of this difference and the generation of the function of the error signal are taken care of by a special analog-to-digital converter 13' consisting of a differentiating element 48 with a subsequently arranged comparator 49. This comparator 49 determines the sign of the error signal difference as formed in the differentiating element 48, so that the error-signal function which is also fed to the transversal filter 11, is equal to the sign of the time derivative of the error signal.

According to this error-signal function also, the transversal filter 11 has been changed in a way now explained with reference to Fig. 4. In the transversal filter according to Fig. 4, the tapped signals which, in the delay elements 50, are delayed by one clock period with respect to one another, are multiplied in the usual way in multipliers 51, by variable filter coefficients, and the products are combined in adders 52 to form the output signal A of the transversal filter 52. The variable filter coefficients are provided by adjusting circuits 25 whose input signals are the respective correlation products as formed in the associated multipliers 53.

The adjusting circuits 25 will now be explained with reference to Fig. 6. The multipliers 53 multiply the error-signal function, not as in known transversal filters, by the tapped signals, but by the differences of two successively following tapped signals. The latter are formed in subtractors 54 which, from the tapped signal as associated with the respective multipler 53, subtract the preceding tapped signal which then appears at the output of the respective next delay element 50.

The clock frequency at which this transversal filter is operated, is the frequency at which the values of the function of the error signal appear, i.e., the sampling clock frequency of the sampleand-hold device 8 (Fig. 1). This can mean that the computing operations in the transversal filter 1 2 have to be carried out at a considerably high speed.

One form of transversal filter overcoming this deficiency, is shown in Fig. 5, which transversal filter chiefly differs that of Fig. 4 in that not all of the filter sections process the error-signal function simultaneously and supply their contribution to the filter output signal at the same time, but that this is done in groups one at a time in turn. This is taken care of by two time-division multiplex (TDM) circuits operating in clock-controlled synchronism, and which feed the error signal function in each time slot always only to one group of filter sections, or always only connect one group to the filter output and, during the next time slot, correspondingly serve another group. The filter sections are divided into n groups, with n indicating the ratio of the sampling frequency to the bit repetition rate.

Accordingly, the TDM circuits which, for simplicity, are shown as rotary switches 55 and 56, have n different switch states and are stepped on in accordance with the sampling-cycle periods.

Considering that the word repetition rate of the error signal function, as mentioned above, is identical to the sampling cycle frequency, this means that each filter section is operated not, as usual in a sampling cycle, but in a bit timing. Thus to perform their computing operations, the individual filter sections can dispose of n-times the time, i.e., one clock period of the transversal filter is identical to one bit period and not to one sampling cycle period. Accordingly, the time delay of the delay elements 50 is so chosen as to equal one bit period, and is indicated by Z-".

The clock frequency of the recursive filter is not affected by the reduction of the clock frequency in the transversal filter. This frequency is in any case equal to the sampling cycle frequency.

Note that the TDM mode of operation of the transversal filter is independent of whether or not one uses the difference forming of the tapped signals as described above. These TDM circuits 55 and 56, may therefore, also be used with prior art transversal filters where an operation-saving kind of working is desired.

We now explain, with reference to Fig. 6, an example of the adjusting circuits 25 as shown in the drawings described above.

As mentioned, the adjusting circuits process the correlation products Xn~j . yen, wherein en indicates the value of the error signal function, and XnH indicates the value of the signal to be multiplied thereby. These correlation products Xn~j . en are summated in an accumulator 60 throughout G clock intervals, G being a suitable, preset number. After this number of clock intervals, the accummulator 60 is reset to zero, and its previously calculated result, referred to as the correlation sum, is taken over by a multiplier 61. This multiplier multiplies the correlation sum by a factor 2-, ss being a natural number. The multiplication which is actually a division, can be done by a simple shifting operation of the correlation sum by /3 positions, as that sum is in binary notation. Thus, we obtain the adjusting value Aq of the filter coefficient, which is added in an accummulator 62, to the current value qj of the coefficient, so that there is formed the successively following value qj+, according to ql+, = q, + .Eq. The accummulator 62 has a further input to which the initial value q0 is applied. Thus, in the adjusting circuits, the coefficients are iteratively adjusted in intervals of G clock periods.

Claims

1. An arrangement for connecting a source and a sink to a two-wire line for digital communication using duplex operation, with a hybrid circuit and an adaptive digital filter which, from the source signal, derives a compensating signal to suppress the interference signal which, due to the own source signal, is caused in the sync signal, with the adaptive digital-filter coefficients being iteratively adjusted in dependence upon an error signal representing the non-suppressed interference-signal component, the adjusting values for adjusting the individual filter coefricients equalling a function of a sum of correlation products formed over a defined number of clock intervals, in which the adjusting values are formed by the multiplication of signals derived from tapped signals of the digital filter, by a function of the error signal, and in which the adaptive digital filter includes the parallel arrangement of an adaptive digital transversal filter and of an adaptive digital recursive filter, with the sum of the output signals thereof, representing the compensating signal.

2. An arrangement as claimed in claim 1, in which the recursive filter includes two filter sections, one of which contains recursive loop delaying its output signal by one clock period, multiplies it by a first variable coefficient (a) and adds it to its input signal, in which the other filter section contains a multiplier multiplying its input signal by a second coefficient (b), in which the signal for forming the adjusting value of the first coefficient (a) and to be multiplied by the function of the error signal, is derived from the output signal of the recursive filter, in which the signal for forming the adjusting value of the second filter coefficient (b), to be multiplied by the function of the error signal, is derived from the output signal of the one filter section, and in which both the transversal filter and the recursive filter the function of the sum of correlation products (XX~j . en) is this sum multiplied by 2-, with /3 being a natural number.

3. An arrangement as claimed in claim 2, in which in the recursive filter, the tapped signals used to form the coefficient adjusting values, are each delayed in delay circuits byj clock periods of said transversal filter withjbeing the filter degree of the transversal filter.

4. An arrangement as claimed in claim 2 or 3, in which in the recursive filter, the filter section including the recursive loop precedes the filter section containing the multiplier, and in which the function of the error signal is the error signal as digitized in an analog-to-digital converter.

5. An arrangement as claimed in claim 2 or 3, in which in the recursive filter, the tapped signals used to form the coefficient adjusting values, pass through a difference-forming circuit which, from each of the successive digital values, subtracts the preceding digital value which has been delayed by one clock period.

6. An arrangement as claimed in claim 5 in which the function of the error signal is the sign of the time derivative of the error signal.

7. An arrangement as claimed in claim 5 or 6, in which in the recursive filter the filter section including the recursive loop follow the filter section including the multiplier, in which the difference-forming circuit, as the tapped signal of the recursive filter, processes the output signal thereof, and in which the difference between two successive digital values is the signal which, for forming the adjusting value of the second coefficient (b), is to be multiplied by the function of the error signal, and from which there is derived the signal which, to form the adjusting value of the first coefficient, is to be multiplied by the function of the error signal.

8. An arrangement as claimed in claim 3 or 7, in which the signal as derived from the output of the recursive filter, passes through a recursive filter loop whose output signal is the signal which, to form the adjusting value of the first coefficient (a), is to be multiplied by the function of the error signal, and in which as the filter coefficient of the recursive filter loop there is used the value of the first filter coefficient (a).

9. An arrangement as claimed in claim 5, 6 or 7, in which the transversal filter the signals as derived from the tapped signals, each represent the differences between two tapped signals appearing at neighbouring tapping points.

10. An arrangement as claimed in any one of the preceding claims, in which in said transversal filter there is used the same error-signal function as in said recursive filter.

11. An arrangement as claimed in any one of the preceding claims, in which the transversal filter and the recursive filter are operated in the clock timing of a sample-and-hold device inserted into said sink branch.

12. An arrangement as claimed in any one of claims 1 to 10, in which the transversal filter is operated in the bit timing of the source and the sink, whereas the recursive filter is operated in the clock timing of a sample-and-hold device inserted into said sink branch.

13. An arrangement as claimed in claim 12, in which in the transversal filter, the filter sections are divided into n different groups, n being indicative of the number of samplings per bit, in which there is a first time-division multiplex circuit which, in the sampling cycle, connects the function of the error signal each time to another one of said n groups, in which there is a second time-division multiplex circuit which, in the sampling cycle, connects each time another one of said n groups to the output of said transversal filter, and in which said two time-division multiplex circuits are operated in clock-controlled synchronism.

14. An arrangement for connecting a source and a sink to a two-wire communication line, substantially as described with reference to the accompanying drawings.