JP3110091B2 - Jitter Compensator Training Method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission apparatus provided with an echo canceller for removing an echo component circulating from a transmission side to a reception side, and more particularly to a digital phase locked loop circuit (DPLL). ) Is used to recover the timing from the received signal, and the DPLL
The present invention relates to a transmission device provided with a jitter compensating device for compensating for the effect of a phase jump (jitter) occurring in a signal on an echo canceller.

[0002]

2. Description of the Related Art One example of a digital subscriber line transmission apparatus is a two-wire digital subscriber line transmission apparatus using a hybrid circuit.

FIG. 3 shows an example of a configuration in which the digital subscriber line transmission device is provided on the station side. Transmitter (T
X) 301 converts binary digital transmission data into a transmission code (for example, 2B1Q code), drives line 304, and transmits the transmission code. In this case, the transmission unit 301 performs a transmission operation in synchronization with a transmission clock from a local oscillator (not shown) in the station.

The hybrid circuit (HYB) 303 has two
Two-to-four-wire conversion is performed between a line line (subscriber line) 304, two transmission lines 302, and two reception lines 305.
The A / D converter (ADC) 306 is a hybrid circuit 3
A signal obtained by mixing an echo of a transmission signal from the own device that wraps around via 03 and a reception signal (analog signal) transmitted from the other device and attenuated on the line 304 is converted into a digital signal.

[0005] An echo canceller (EC) 308 and a subtractor 307 cancel the echo. Equalizer (E
QL) 310 equalizes the received signal transmitted from the partner device and attenuated on the line 304.

The timing recovery circuit (TIM) 311
The optimum sampling phase in the A / D converter 306 is extracted from the received signal. The DPLL 312 generates a sampling clock synchronized with the sampling phase,
The signal is supplied to the A / D converter 306.

The jitter compensation circuit (JTC) 309 has a DP
When the LL 312 generates a phase jump in the sampling clock, that is, generates a jitter, the LL 312 performs compensation corresponding to the generation of the jitter on the echo canceller 308.

In a two-wire digital subscriber line transmission apparatus using a hybrid circuit having the above configuration,
The echo leaks from the transmission side to the reception side via the hybrid circuit 303, while the reception signal transmitted on the line 304 is considerably attenuated. For this reason, the intensity ratio between the echo and the received signal may reach several tens of decibels. Therefore, in the above-described transmission device, the echo cancellation processing by the echo canceller 308 and the jitter compensation circuit 309 is indispensable.

Here, the impulse response waveform of the echo included in the received signal has, for example, a shape as shown in FIG. Therefore, the echo canceller 308 outputs C ₁ , C ₂ , C ₃ ,... In FIG.
What is necessary is just to comprise as a filter which has an impulse response which consists of a tap coefficient shown by this. Then, the echo canceller 308 convolves the signal obtained by sequentially delaying the transmission symbol a _j at each transmission timing with the above tap coefficients C ₁ , C ₂ , C ₃ ,.
Output echo replica ER _j . And the subtractor 30
7 is the echo replica E from the output of the A / D converter 306.
By subtracting R _j , it is possible to cancel the echo that wraps around to the receiving side at each transmission timing.

Here, when a sampling clock synchronized with the sampling phase extracted by the timing recovery circuit 311 is generated, the DPLL 312 jumps the phase of the clock in the process of controlling the phase of the clock to generate jitter. obtain.

Here, when the DPLL 312 jumps the phase of the sampling clock by ± Δθ as shown in FIG. 5 at an arbitrary sampling timing, at an arbitrary timing after that timing, the timing from the echo canceller 308 at each arbitrary timing is set. The echo component can be canceled by the value C _n ′ or C _n ″ obtained by correcting the value of the tap coefficient C _n by ± J _n as shown in FIG.

Therefore, the jitter compensation circuit 309 of FIG.
By generating the above-described jitter compensation value ± J _n and adding this compensation value to each tap coefficient C _n in the echo canceller 308, the jitter generated by the DPLL 312 can be compensated.

FIG. 6 shows an echo canceller (EC) 308.
FIG. 3 is a configuration diagram of a jitter compensation circuit (JTC) 309. In FIG. 6, ER _j is an echo replica generated at an arbitrary time j, a _j is a transmission symbol at the time j, C ₀ to
C _N is a tap coefficient in the echo canceller 308, ε
_j is the equalizer 310 at time j in the normal case where no jitter occurs in the DPLL 312 (FIG. 3).
Input echo and echo replica ER obtained from Fig. 3
error signal between _j, epsilon _j 'is an error signal when the jitter occurs in DPLL312.

[0014] First of all, the echo replica ER _j, the signal 1
Each delay circuit 6 that delays by the sampling timing T
A transmitted symbol a _jN from 01 and the tap coefficients C ₀ -C _N from the memory 604 is multiplied by the respective multipliers 602, by respective multiplication results are added by the adder 603, the following equation The operation is performed as shown. Note that “*” represents multiplication.

[0015]

(Equation 1) Here, when no jitter occurs in the DPLL 312 (FIG. 3), each of the tap coefficients C _{0 to} C _N stored in each of the memories 604 is updated according to an algorithm expressed by the following equation.

[0016]

(Equation 2) That is, in each multiplier 605, the constant α and each delay circuit 60
A transmitted symbol a _jN and the error signal epsilon _j from 1 are multiplied, the multiplication result is the adders through each selector 606 6
07. Each adder 607 converts the multiplication result into each of the tap coefficients C ₀ -C stored in each memory 604.
Add to _N. Then, the contents of each memory 604 are updated with new tap coefficients C _{0 to} C _N obtained as the respective addition results. In this way, the tap coefficients C _{0 to} C _N stored in the memories 604 are updated so that the error signal ε _j decreases.

On the other hand, when jitter occurs in the DPLL 312 (FIG. 3), each of the tap coefficients C _{0 to} C _N stored in each of the memories 604 is updated in accordance with the following equation.

[0018]

(Equation 3) That is, in each multiplier 609, the jitter compensation values J _{0 to} J _N stored in each memory 608 are multiplied by the jitter direction data D from the DPLL 312, and each multiplication result is input to each adder 607 via each selector 606. I do. Here, the jitter direction data D is obtained by the DPLL 312 by the A / D converter 3.
06 is data indicating whether the phase of the sampling clock output is jumped forward or backward (see FIG. 5), and has a value of +1 or -1. Each adder 607 is
Each jitter compensation value to which the direction of the jitter is added is added to each of the tap coefficients C _{0 to} C _N stored in each memory 604. Then, the contents of each memory 604 are updated with new tap coefficients C _{0 to} C _N obtained as respective addition results. In this way, each tap coefficient C _{0 to} C _N stored in each memory 604 is updated by each jitter compensation value to which the direction of the jitter is added.

Here, when jitter occurs in the DPLL 312 (FIG. 3), the jitter compensation values J ₀ to J ₀ stored in the memories 608 are used together with the above-described jitter compensation operation.
J _N is updated according to the algorithm shown in the following equation.

[0020]

(Equation 4) That is, in each multiplier 610, the constant β and each delay circuit 60
1 is multiplied by the jitter direction data D from the _DPLL 312 and the error signal ε _j ′, and the result of each multiplication is calculated in each adder 607 by each jitter compensation value J _0- stored in each memory 608. Add to J _N. Then, a new jitter compensation value J ₀ obtained as a result of each addition.
The through J _N, the content of each memory 608 is updated.
Thus, the jitter compensation values J _{0 to} J _N stored in the memories 608 are updated so that the error signal ε _j ′ decreases.

[0021]

Here, as described above, each of the tap coefficients C _{0 to} C _N stored in each of the memories 604 in the echo canceller 308 and the jitter compensation circuit 30
9, each jitter compensation value J ₀ stored in each memory 608.
ＪJ _N are updated so as to converge from an appropriate initial value to an optimum value.

In this case, each of the tap coefficients C _{0 to} C _N in the echo canceller 308 is an error signal ε obtained from the equalizer 310 (FIG. 3) at each sampling timing.
Updated at each sampling timing based on _j ,
The optimum value is converged after a reasonable short time has elapsed from the start of the operation of the digital transmission apparatus of FIG.

On the other hand, each of the jitter compensation values J _{0 to} J _N in the jitter compensation circuit 309 is determined by the equalizer 310 (FIG. 3) only when jitter occurs in the DPLL 312 (FIG. 3).
Is updated based on the error signal ε _j ′ obtained from The time interval at which jitter occurs in the sampling clock output from the DPLL 312 to the A / D converter 306 (FIG. 3) is much longer than the time interval of each sampling timing.

Here, during the training period at the start of operation of the digital transmission apparatus of FIG.
If the phase of the sampling clock output to the D converter 306 (FIG. 3) is accidentally pulled into the optimum value by accident, each memory 608 stores each jitter compensation value J ₀ that has not converged to the optimum value. ~ J _N will be stored. At the time of actual operation after the end of the training period, as described above, the time interval at which each of the jitter compensation values J _{0 to} J _N is updated is long, so that it takes a very long time until they converge to the optimum value. I need it. As a result, the optimum jitter compensation operation is not performed for a long time until each of the jitter compensation values J _{0 to} J _N converges to the optimal value, and the echo component cannot be appropriately removed from the received data. There is a problem that it is.

An object of the present invention is to make it possible to shorten the convergence time of the jitter compensation value to the optimum value in the jitter compensation device.

[0026]

FIG. 1 is a block diagram of the present invention. The present invention relates to transmission signal 1 on line 110.
Signal converter 1 for mixing and separating received signal 102 and received signal 102
03 and A / D for A / D converting the separated signal therefrom
A conversion device 104, an echo canceller 105 for removing an echo from the output signal, a timing reproduction device 106 for reproducing a sampling timing phase in the A / D conversion device 104 from a received signal, and a digital phase for controlling the sampling timing phase A transmission device such as a digital subscriber line transmission device including a locked loop circuit (DPLL) 107 and a jitter compensating device 108 for compensating jitter generated in the process of controlling the sampling timing phase by the circuit is assumed. .

The digital phase locked loop circuit 107 has a dummy jitter generation control means 109 composed of a counter circuit or the like for forcibly generating dummy jitter at appropriate time intervals.

[0028]

The dummy jitter generation control means 109 forcibly causes the digital phase locked loop circuit 107 to generate, for example, dummy jitter in which the jitter direction changes alternately back and forth at regular time intervals, for example.

Based on this operation, the jitter compensator 10
In step 8, each jitter compensation value in the device 108 is updated, for example, at the above-mentioned fixed time. Therefore, after the operation of the transmission apparatus in FIG. 1 starts, the jitter compensation values in the jitter compensator 108 can be quickly converged to the optimum values before the true jitter occurs in the digital phase locked loop circuit 107. It becomes possible.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is an overall configuration diagram of a digital subscriber line transmission apparatus according to an embodiment of the present invention. In FIG. 2, portions denoted by the same reference numerals as those of the conventional example in FIG. 3 have the same functions. The echo canceller 308 and the jitter compensation circuit 309 have the same configuration as the configuration shown in FIG.

The configuration of the embodiment of FIG. 2 differs from the configuration of the conventional example of FIG. 3 in that a counter circuit (CNT) 201 for forcibly causing a dummy jitter in the DPLL 312 is provided.

As a configuration, a simple counter circuit 201 is added as compared with the conventional example, but the effect is great. That is, the counter circuit 201 sends an instruction signal to the DPLL 312 at regular time intervals by repeatedly counting a predetermined count value.

As a result, the DPLL 312 forcibly generates dummy jitter in which the direction of the jitter alternately changes back and forth. Here, in order to alternately change the jitter direction back and forth, a flag memory for storing jitter direction data that can take a value of ± 1 is provided in the DPLL 312, and every time a dummy jitter is generated, the flag memory is stored in the flag memory. Value +1
Alternatively, it may be rewritten alternately to -1.

The above counter circuit 201 and DPLL3
By the operation of No. 12, jitter occurs at regular intervals.
Accordingly, the jitter compensation circuit 309, every predetermined time, equalizer 310 each jitter compensation value J stored in the memory 608 ₀ in FIG. 6 by the error signal epsilon _j 'generated from ~J
_N will be updated.

Therefore, after the operation of the digital subscriber line transmission apparatus of FIG. 2 is started, the respective jitter compensation values J _{0 to} J _N in the jitter compensation circuit 309 are promptly adjusted to the optimum values until the true jitter occurs in the DPLL 312. It is possible to converge.

The DPLL 312 is connected to the A / D converter 30
Even if the above-described dummy jitter is generated with respect to the sampling clock output to the counter 6, the received data is adversely affected because the phase jumps one unit alternately back and forth around the normal phase. It does not appear.

[0037]

According to the present invention, each jitter compensation value in the jitter compensator is quickly set to an optimum value after the operation of the transmission apparatus is started and before the true jitter occurs in the digital phase locked loop circuit. It is possible to converge.

[Brief description of the drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of a digital subscriber line transmission apparatus according to the present invention.

FIG. 3 is a configuration diagram of a conventional digital subscriber line transmission device.

FIG. 4 is a diagram showing a relationship between an impulse response waveform of an echo and a tap coefficient of an echo canceller.

FIG. 5 is a diagram for explaining a change in a tap coefficient based on a change in a sampling phase.

FIG. 6 is a configuration diagram of an echo canceller and a jitter compensation circuit.

[Explanation of symbols]

REFERENCE SIGNS LIST 101 transmission signal 102 reception signal 103 signal conversion device 104 A / D conversion device 105 echo canceller 106 timing recovery device 107 digital phase locked loop circuit (DPLL) 108 jitter compensation device 109 dummy jitter generation control means 110 line

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04B 3/20-3/23 H04B 7/015

Claims (1)

(57) [Claims] 1. A transmission signal (101) and a reception signal (10)
2) a signal converter (103) for mixing and separating the signals, an A / D converter (104) for A / D converting the signal separated by the signal converter, and an echo canceller for removing echoes from the output signal (105) and the A
A timing recovery device (106) for recovering the sampling timing phase in the / D conversion device (104), a digital phase locked loop circuit (107) for controlling the sampling timing phase, and the digital phase locked loop A jitter compensator (108) for compensating jitter generated in a process of controlling the sampling timing phase by the circuit, wherein the digital phase locked loop circuit (1)
07), further comprising dummy jitter generation control means (109) for forcibly generating dummy jitter at appropriate time intervals.