KR20000045143A - Echo removing system - Google Patents

Abstract

PURPOSE: An echo removing system is provided to be easy to realize the system as a single chip by realizing a transmission filter with a digital filter. CONSTITUTION: An echo removing system comprises a jitter compensation part(302) which stores a time difference between quantized symbols and multiplies and sums a coefficient corresponding to the time difference. An echo removing part(304) presumes a signal that a transmission symbol is echoed toward a reception part through a hybrid(308), and the presumed signal is subtracted from a reception signal at a subtracter(314) so as to remove an echo component comprised in the reception signal. An output of the jitter compensation part(302) is supplied to a second subtracter(316) so that an echo component not removed at the echo removing part(304) and the subtracter(314) is again removed. The hybrid(308) transfers a four-watt transmission signal into a two-watt side, and transfers a signal supplied through the two-watt side into a four-watt reception part. A reception filter(310) filters a signal received through the hybrid(308), and a symbol timing restoring part(318) reproduces a reception clock(CLK) from received symbols to provide the reproduced reception clock to a digital transmission filter(306) and the jitter compensation part(302) of a transmission stage and a sampler(312) of a reception stage.

Description

Echo canseller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an echo canceller, and more particularly, to an echo canceller system that enables digital implementation of an entire circuit in a communication system in which a transmission clock and a reception clock are to be synchronized.

In general, echo is a phenomenon in which part of an input signal is returned to a far-end speaker by impedance mismatch of a hybrid circuit existing at a subscriber end of a communication network, and this echo is modeled by echo path. It can be removed by estimating a signal such as echo and subtracting it from the original signal. That is, the long-distance telephone system has a hybrid circuit that converts two-wire (2W) transmission into four-wire (4W) transmission. Since the number of subscriber lines and the length of each two wires are different, the voice signal input through four wires is completely converted into two wires. It is impossible to transmit, causing the delay component of the voice signal of the caller to be returned to the caller. In order to eliminate such echoes, an echo canceller usually composed of an FIR or IIR filter is used.

On the other hand, when the transceivers share lines with each other through a wired communication channel of the same band, such as a digital subscriber network (DSL), the interval between symbols transmitted when the operation clock of the transmitter is synchronized with the reception clock is used. Inconsistency degrades the performance of the echo canceller. In other words, when the clock of the transmitting side does not need to be synchronized with the clock of the receiving side, the clock of the echo canceller can be used as a free oscillation clock. Therefore, the time interval between the output symbols is constant. There is no degradation of the eliminator. However, when several users are connected to one base station, such as a digital subscriber network (DSL), the transmitter of each user side must synchronize its clock with the base clock of the base station called the network clock. At this time, since the clock information is extracted by the receiving unit of each user receiving data from the base station, it is necessary to synchronize the clocks of the receiving unit and the transmitting unit of each user.

In this case, when the transmission and reception clocks need to be synchronized, the structure of the echo canceller uses an analog PLL or an analog filter on the transmitting side while additionally using a jitter compensator, as shown in FIG. It is. In other words, the jitter compensator stores the time difference between quantized symbols and multiplies the coefficients corresponding to the difference between them to sum the outputs.The output filter of the transmitting end is time-invariant regardless of the phase change of the symbol clock. Because an invariance property must be used, an analog filter is used at the transmitting end.

Referring to FIG. 1, the conventional echo canceling system includes a jitter compensator 102, an echo canceller 104, an analog transmission filter 108, a hybrid 110, a reception filter 112, a sampler 114, and a first echo cancellation system. The first subtractor 116, the second subtractor 118, and the symbol timing recovery unit 120 transmit and receive the subscriber side 4W transmission / reception signal to the 2W side via the hybrid 110.

However, when the analog filter is used in the transmission stage as a whole, the life of the echo cancellation system is shortened, and it is difficult to implement the semiconductor chip (ASIC). When a digital filter is used in the transmitter to solve this problem, there is a problem in that the characteristics of the echo canceller deteriorate as shown in FIG. 2. Referring to Figure 2, the horizontal axis represents the time axis (Time: ms) and the vertical axis represents the echo suppression level (Echo Suppression Level (dB)), it can be seen that the echo is suppressed from about 30 to 80msec, the echo is not sufficiently suppressed from about 90msec Can be.

Accordingly, the present invention has been proposed to solve the above problems, and an object of the present invention is to provide an echo cancellation system that can be implemented as a fully digital circuit by using a digital filter in a transmitter even when a transmission / reception clock needs to be synchronized. .

In order to achieve the above object, the present invention recovers the symbol clocks from the symbols received from the network side to synchronize the transmission and reception clocks, and transmits the transmission symbol to the network side through a hybrid through a digital transmission filter, and from the network side. In the echo cancellation system for receiving a signal received through the hybrid through the reception filter, the jitter compensator and the echo canceller connected between the 4W transmitter and the receiver,

Input switching means for outputting the digital transmission filter by switching the signal input values Xn and 0 according to a control signal; A first sampling switch transferring an input value according to the first switch control signal; A second sampling switch transferring an input value according to the second switch control signal; A first filter unit configured to receive and filter the output of the first sampling switch; A second filter unit configured to receive and filter the output of the second sampling switch; A third sampling switch transferring an input value according to the third switch control signal; A fourth sampling switch transferring an input value according to a fourth switch control signal; A first sink function interpolation filter configured to interpolate the output of the third sampling switch; A second sink function interpolation filter configured to interpolate an output of the fourth sampling switch; An adder for adding the output of the first sink function interpolation filter and the output of the second sink function interpolation filter; And controlling the input switching means to transmit a signal input value Xn to the filter unit operating in an activation state, and to pass 0 to a filter unit operating in an inactive state, and receiving a phase control signal from the first and third sampling switches and the second and A control signal generator for controlling the fourth sampling switch to synchronize the sampling period of the filter unit operating in the inactive state according to the changed phase, and then operating the activated sampling unit. It is characterized by including.

1 is a block diagram showing a conventional echo cancellation system;

2 is a characteristic graph when converting an analog filter into a digital filter in the configuration as shown in FIG. 1;

3 is a block diagram illustrating an echo cancellation system according to the present invention;

4 is a detailed block diagram of the digital filter shown in FIG.

FIG. 5 is a view illustrating the digital filter shown in FIG. 3;

FIG. 6 illustrates a first embodiment of the sink function interpolation filter illustrated in FIG. 5;

FIG. 7 illustrates a second embodiment of the sink function interpolation filter illustrated in FIG. 5;

8 is a characteristic graph of a digitally implemented echo cancellation system in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

302: jitter compensator 304: echo canceller

306: digital transmission filter 308: hybrid

310: Receive filter 312: Sampler

314, 316: subtractor 318: symbol timing recovery unit

410: input switching unit 420a, 420b: FIR filter unit

430a, 430b: Sink function interpolation filter 440: Adder

450: control signal generator

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating an echo cancellation system according to the present invention, wherein the echo cancellation system includes a jitter compensator 302, an echo canceller 304, a digital transmission filter 306, a hybrid 308, and a reception filter ( 310, a sampler 312, a first subtractor 314, a second subtractor 316, and a symbol timing recovery unit 318.

Referring to FIG. 3, the jitter compensator 302 stores a time difference between quantized symbols and multiplies a coefficient corresponding to the difference between the quantized symbols and outputs the sum. That is, the jitter compensator 302 removes the echo component that the echo canceller 304 cannot remove due to jitter. The echo canceller 304 is a kind of FIR filter, which estimates a signal in which a transmission symbol is echoed to the receiver through the hybrid 308, and then subtracts from the received signal by the subtractor 314 to remove an echo component included in the received signal. . The output of the jitter compensator 302 is input to the second subtractor 316 to remove the echo component that was not removed by the echo canceller 304 and the first subtractor 314. The hybrid 308 transmits the 4W side transmission signal only to the 2W side, and the signal received through the 2W side is transmitted only to the 4W side receiving end, thereby connecting the 2W and 4W. The reception filter 310 filters the signal received through the hybrid 308, and the symbol timing recovery unit 318 is implemented as a kind of digital PLL to reproduce the reception clock CLK from the received symbols to obtain a sampler of the receiver. 312) and the digital transmission filter 306 and jitter compensator 302 of the transmitting end. In this case, the digital transmission filter 306 is provided with a high speed clock and a low speed clock synchronized with the reception clock, and a phase control signal for changing the phase.

On the other hand, the digital transmission filter according to the present invention, as shown in Figure 4, the input switching unit 410, the first switch (S1a), the second switch (S1b), the first FIR filter (420a), the second An FIR filter 420b, a third switch S2a, a fourth switch S2b, a first sink function interpolation filter 430a, and a second sink function interpolation filter 430b. In FIG. 4, the first FIR filter 420a and the first sink function interpolation filter 430a constitute a first filter part a and are simultaneously activated or deactivated in pairs, and the second FIR filter 420b and the second sink are simultaneously. The function interpolation filter 430b constitutes a second filter part b and is activated or deactivated simultaneously in a pair. When the first FIR filter 420a and the first sink function interpolation filter 430a are activated, the second FIR filter 420b and the second sink function interpolation filter 430b are deactivated and, conversely, the first FIR filter 420a. When the first sink function interpolation filter 430a is deactivated, the second FIR filter 420b and the second sink function interpolation filter 430b are activated.

As described above, when the output filter is implemented as a digital filter, a multi-stage is mostly used (a two-stage filter in the embodiment of the present invention). In particular, as the manufacturing technology of the VLSI advances, since the oversampling technique is generally used when implementing a D / A converter, the output filter has a function of shaping and simultaneously filtering the waveform of the output symbol. Therefore, in the embodiment of the present invention, the final stage is composed of a sink function interpolation filter having a relatively simple structure, and the front stage is composed of an FIR filter operating at a relatively low speed. That is, the operation speed of the FIR filter 420a or 420b operates according to a low speed clock provided from the symbol timing recovery unit 318, and the sink function interpolation filter 430a or 430b is provided from the symbol timing recovery unit 318. It operates according to a high speed clock.

Referring back to FIG. 4, the input switching unit 410 receives the signal input values Xn and 0, and signals the filter unit a or b which is activated according to a control signal input from the control signal generator 450. The input value Xn is passed 0 to the filter part b or a which operates by deactivation.

The first switch S1a is turned on / off according to the control signal transmitted from the control signal generator 450 to transfer the output of the input switching unit 410 to the first FIR filter 420a, and the second switch S1b. Is turned on / off according to the control signal transmitted from the control signal generator 450 to transfer the output of the input switching unit 410 to the second FIR filter 420b.

The first and second FIR filters 420a and 420b are conventional FIR filters and filter input signals according to predetermined coefficients.

The third switch S2a is turned on / off according to the control signal transmitted from the control signal generator 450 to transfer the output of the first FIR filter 420a to the first sink function interpolation filter 430a, and the fourth switch. S2b is turned on / off according to the control signal transmitted from the control signal generator 450 to transfer the output of the second FIR filter 420b to the second sink function interpolation filter 430b.

The adder 410 adds the output of the first sink function interpolation filter 430a and the output of the second sink function interpolation filter 430b. Since one of the two outputs is almost 0, one of the two outputs is transferred as it is. It plays a role.

The control signal generator 450 controls the filter units (a, b) connected in parallel to be activated and deactivated. The filter unit operating in the active state is provided with a signal input value Xn and 0 is inputted into the inactive filter unit. To be. When the phase control signal is received, the sampling time of the filter unit operating in the inactive state is synchronized to a new phase, and when the synchronization is completed, the input value is switched to activate the filter unit in the inactive state, and the filter unit operating in the inactive state. At this time, the filter unit, which was operated by activation, continues to operate at a conventional timing without changing the phase.

As described above, an operation of the present invention in which the phase is changed in accordance with the phase control signal will be described with reference to FIG. 5.

4 and 5, input signals are input at regular sample periods as inputs of the first FIR filter 420a and the second FIR filter 420b. The black dot (●) indicates that the signal input value Xn is input, and the white point (○) indicates that 0 is input. Initially, the first FIR filter 420a is activated and the second FIR filter 420b is operated inactive. When the phase control signal is received after 4 clocks, the first FIR filter 420a continues to process and output a signal input value at the timing of the previous clock, and the second FIR filter 420b is newly synchronized according to the phase control signal to sample the period. Change Subsequently, when the second FIR filter 420b is synchronized to a new sampling period, the input is changed so that the second FIR filter 420b is activated and the first FIR filter 420a is inactive. At this time, the first FIR filter 420a maintains the previous phase without continuously changing the sampling phase. When the phase control signal is received again while the second FIR filter 420b is activated, the first FIR filter 420a, which has been inactive, changes the phase to newly synchronize the sampling period, and the first FIR filter 420b is activated. When the synchronization of the FIR filter 420a is completed, the input is changed so that the first FIR filter 420a is activated and the second FIR filter 420b is deactivated.

In this way, when the phase change is required, by changing the phase of the filter portion to which 0 is input (that is, deactivating), the value input at the time of phase change becomes 0 so that an error does not accumulate.

FIG. 6 is a first embodiment of the sink function interpolation filter shown in FIG. 4, wherein the sink function interpolation filter 430a or 430b includes a subtractor 602, a subtractor 604, a sample and hold switch 606, and 1 / R. Constant Multiplier 608, Adder 610, 1 / R Constant Multiplier 612, Adder 614, Delay 616, Sample Switch 618, Adder 620, 1/2 Constant Multiplier 622 , A delay 624, a sample switch 626, an adder 628, a sample switch 630, and a delay 632. Here, the two subtractors 602, 604 in front of the switch 606 function as differentiators, the two adders 610, 614 at the rear end of the switch 606 function as integrators, and the three switches 618, 626, 630 are negative feedbacks. Form a loop.

Referring to FIG. 6, the output integrator operates at R times higher speed than the input side integrator based on the switch 606. The switch for transferring the signal from the low speed unit to the high speed unit receives a signal from the high speed unit to the low speed unit. The switch to pass is called the sample switch. The input signal is output through the first subtractor 602, the second subtractor 604, the sample-and-hold switch 606, the multiplier 608, the adder 610, the multiplier 612, and the adder 614. It is negative feedback by each feedback loop. That is, the output of the adder 610 is delayed by the delayer 616 and then provided to the adder 610, and is also transmitted to the subtractor 604 and the adder 620 through the sample switch 618.

The output of the adder 614 is provided to the adder 614 after being delayed by the delayer 632 and to the adder 628 through the sample switch 630, and the output of the delayer 632 is delayed ( Delayed again at 624 and then provided to adder 620 via sample switch 626. The adder 620 adds the output of the sample switch 630 and the output of the sample switch 626 to the adder 620, and the adder 620 outputs the sample switch 618 and the output of the adder 628. Is added and output to the constant multiplier 622. The constant multiplier 622 multiplies the output of the adder 620 by 1/2 and outputs the result to the subtractor 602. 6, multipliers 608 and 612 are constant multipliers that multiply by 1 / R.

Such a sink function interpolation filter has an advantage that the error is not always zero but at least the error does not accumulate and has a much faster response speed to the phase control signal. In particular, when the loop filter used for the symbol timing recovery unit 318 is 0 order, the maximum frequency shift that can be tracked by the timing recovery circuit of the receiver is increased.

As described above, one of two FIR filter branches is inputted with a symbol value to be output, and 0 is input to the remaining FIR filter. In this case, the activated FIR filter accepts the input symbol and the deactivated FIR filter accepts zero. At this time, the internal delay elements of the deactivated FIR filter have all zeros. Therefore, even if you change the phase of the filter that has been inactive at the time of phase control, the output remains 0, so that no error is transmitted to the next stage. Thereafter, the activation / deactivation state of the two filters is changed. The phase of the newly activated FIR filter is not changed with respect to the current phase signal. Thereafter, when it is confirmed that the internal values of the inactive FIR filter are all 0 after a predetermined time and 0 is continuously input to the interpolation filter of the next stage, a new phase control can be applied.

If the order of the loop filter of the symbol timing recovery unit 318 is 0 in the phase control scheme as described above, the traceable frequency shift is as follows.

In Equation 1, N _FIR is the number of taps of the FIR filter, and N _SIC3 is the number of taps of the sink function interpolation filter.

In the present invention, the sink function interpolation filter with negative feedback does not calculate and store the value stored in the delay element required in the differentiator portion from the input symbol as in the conventional differentiator structure, but rather the output value and the internal value of the integrator. Properly combined values are produced without any additional delay elements. By implementing the differentiator without delay elements, the error that had to be accumulated previously can always be converged to zero through negative feedback. That is, x [n-1] and (x [n-1] -x [n-2]) are the following Equations 2 and 3 when the symbol interval of the input symbol is always constant.

x [n-1] -x [n-2] = l ₁ (n)

x [n-1] = 1 / 2⋅ (l ₁ (n) + (l ₂ (n) + l ₂ (n-1)))

If the interval between input symbols is not constant, the negative feedback signal has a different value from the original x [n-1] and (x [n-1] -x [n-2]), respectively. As a result, the difference is the error propagated through the negative feedback path, and this error is subtracted so that the output finally converges to zero.

In this way, the negative feedback sync function interpolation filter always makes zero when the components of these errors are below a certain level, whether they are cumulative errors or errors caused by not satisfying time invariance. That is, even if the internal values of the delay element of any one FIR filter are not zero, the negative feedback sync function interpolation filter converges the error to 0 even when the output clock phase is not completely zero. The level of echo suppression of the removal system can be suppressed below the desired level. Therefore, the echo cancellation system employing the sink function interpolation filter according to the present invention can apply another phase change after a much shorter stabilization time. This may in turn reduce the initial acquisition rate of symbol timing synchronization. For example, when the proposed negative feedback sync function interpolation filter is used while maintaining the echo suppression level at 70 dB, the maximum traceable frequency shift can be increased as shown in Equation 4 below.

When the interpolation rate is high, Equation 3 can be simplified, and thus, a simplified equation as shown in Equation 5 can be obtained.

x [n-1] = 1 / 2⋅ (2⋅l ₁ (n) + l ₂ (n))

The simplified circuit as shown in Equation 5 may be implemented as a circuit in which the block 640 made of a dotted line is deleted from the circuit of FIG. 6 and the output of the switch 630 is connected by a dotted line.

On the other hand, when implemented in hardware, the sink function interpolation filter including the negative feedback increases the number of adders used for the negative feedback, thereby increasing the delay time of the critical path, thereby limiting the maximum operation speed. In order to solve this problem, as shown in FIG. 7, the sink function interpolation filter is divided into two parts, and the adder of the front end 710 is implemented as a carry save adder, so that the intermediate result of the loop is two. A partial sum is obtained and the rear end 720 is implemented as a pipelined ripple carry adder to add two partial sums to increase the operation speed.

As described above, the echo cancellation system using the digital filter according to the present invention provides an advantage that the echo cancellation characteristic is maintained well as shown in FIG. 8 even when the entire system is digitally implemented. That is, referring to FIG. 8, the horizontal axis represents the time axis (Time: ms) and the vertical axis represents the echo suppression level (dB). Comparing the graph of FIG. 2 showing the conventional characteristics with the graph of FIG. 8 showing the characteristics according to the present invention, it can be seen that the echo cancellation characteristics are maintained well even when the transmitter filter is digitally implemented.

As described above, the present invention enables the transmission filter to be implemented as a digital filter in a communication system that needs to synchronize the transmission and reception clocks so that all of the echo cancellation part can be implemented as a digital circuit. Therefore, the echo cancellation system of the present invention is easy to implement with one chip (ASIC), and provides the effect that the performance of the echo canceller is no longer degraded by the clock jitter of the receiver.

Claims (3)

It recovers the symbol clocks from the symbols received from the network side to synchronize the transmit and receive clocks, transmits the transmission symbol to the network side through the hybrid through the digital transmission filter, receives the reception symbol from the network side through the hybrid and the reception filter, In an echo cancellation system in which a jitter compensator and an echo canceller are connected between a 4W transmitter and a receiver, The digital transmission filter Input switching means for switching and outputting signal input values Xn and 0 according to a control signal; A first filter unit filtering the signal input value when the signal is activated according to a control signal, and outputting 0 by filtering the zero value when the signal is deactivated; A second filter unit filtering a zero value when the signal is deactivated and outputting a zero value, and filtering the signal input value when the signal is activated; An adder for adding the output of the first filter portion and the output of the second filter portion; And The input switching means is controlled to transmit the signal input value Xn to the filter unit operating in the active state and 0 to the filter unit operating in the inactive state, and when a phase control signal is received, synchronize the sampling cycle of the deactivated filter unit to the changed phase. And a control signal generator for controlling the operation of the filter unit to be activated after activation and to maintain the sampling cycle of the filter unit operating as the activation. The method of claim 1, wherein the first and second filter unit A first sampling switch transferring an input value according to a switch control signal of the control signal generator; A FIR filter unit configured to receive and filter the output of the first sampling switch; A second sampling switch transferring an input value according to a switch control signal of the control signal generator; And a sink function interpolation filter for interpolating the output of the second sampling switch. The method of claim 2, wherein the sink function interpolation filter comprises a differential means for differentiating an input, an integration means including a sample and hold switch and a delay unit, and a negative feedback for negative feedback of the output of the integration means to the differential means through switching. Echo cancellation system, characterized in that consisting of means.