JPS6381530A - Data processor - Google Patents

Abstract

PURPOSE:To contrive to decrease chip size and to simplify a logic design by using a control section of an execution unit and a control section of a data storage section of a first-in first-out (FIFO) system in common and constituting the common control section by a read only memory storing a microprogram. CONSTITUTION:A control section CNTt consists of a micro ROM in which a microprogram controlling an adder AUt and a temporary register group TPRt and a microprogram controlling FIFO registers FRt1-FRt3 and a transmission shift register TSR. On the other hand, a reception section 1b consists of an adder AUr, a temporary register group TPRr, FIFO registers FRr1, FRr2...FRrn, a reception shift register RSR, an internal bus BUSn connecting them, a microprogram control section CNTr and a FIFO state designation section STSr. Thus, the exclusive control logic circuit controlling the FIFO is not required to reduce the occupied area.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to data processing technology and to a control method for a FIFO (first-in, first-out) type memory or register (hereinafter referred to as FIFO). The present invention relates to a particularly effective technique, for example, to a technique that is effective when used in a communication LSI equipped with a FIFO.

[Prior Art] Conventionally, a FIFO consists of a plurality of continuously connected registers and a control circuit that transfers data between the registers in each stage and controls data input and output. It was generally constructed from a random logic circuit (see "Integrated Circuit Technical Data IEP599 ``Explanation of FIFO Operation'' published by NEC Corporation in March 1981).

[Problems to be solved by the invention] Since the control circuit in the conventional FIFO was composed of a random logic circuit, the occupied area became large and the FIFO
There is a problem in that as the chip size of an LSI having an FO increases, the number of man-hours required for designing logic also increases.

An object of the present invention is to reduce the chip size of an LSI having a FIFO and to simplify logic design.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, the registers constituting the FIFO are controlled by a control section using a microprogram control method, and
The FIFO control section and the microprogram control section that controls circuits such as the execution unit inside the LSI are made common.

[Operation] According to the above-described means, a dedicated control logic for controlling the FIFO is no longer required, and the above objectives of reducing the occupied area and chip size and simplifying the logic design are achieved. be able to.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a communication LSI.

Although not particularly limited, each circuit block surrounded by a chain line A in FIG. 1 is formed on one semiconductor chip such as a single crystal silicon substrate.

The communication LSI of this embodiment is composed of a transmitter (left side) 1a and a receiver (right side) lb.
and receiving section 1b are each configured with similar architecture.

That is, the transmitter 1a includes an adder AUt, a temporary register group TPRt, and an n-stage FIFo register FRt.
1. FRt 2" FRt n, a transmission shift register TSR, a control unit CNTt that controls these operation timings, and a FIFO register FRt 1 to FR
The FIF state designation section STS t indicates the internal state such as the number of data in t n. Then, the adder AUt, temporary register group TPRt, FI
The FO registers FRt 1 to FRt n and the transmission shift register TSR are connected to each other by an internal bus Bust. Of these, the adder AUt and the temporary register group TPRt are used to perform simple calculations to obtain data necessary for transmission and to count the number of bits of data being transmitted. In addition, the control unit CNT
t is a microprogram that controls the adder AUt and the temporary register group TPRt, and the FIFO register FR.
It is constituted by a micro ROM (read only memory) in which a micro program for controlling tl to FRt3 and the transmission shift register TSR is commonly stored.

On the other hand, the receiving unit 1b includes an adder A U r, a temporary register group TPRr, FIFO registers FRrl, F
Rr2...F Rr n, reception shift register R
8R, an internal bus BUSn connecting these, and a microprogram control unit CNTr.

It is composed of a FIFO status specifying section STSr.

Furthermore, in this embodiment, the internal buses BUSt and B
Either one of U S n can be connected to the common bus BUSc by a changeover switch S, and the common bus B
USc is connectable to an external system bus 5-BUS via an interface circuit ITF.

In the communication LSI mentioned above, when there is data to be transmitted, the CPU outputs a transmit command and the data to be transmitted one after another on the system bus 5-BUS.The command activates the transmitting side control unit CNTt, and first , switch the changeover switch S to connect the common bus B
c and the internal bus BUS t on the transmitting side. Then, the transmission data output from the CPU is supplied from the interface circuit ITF to the internal bus BUSt through the common bus BUSc. Then, the first byte of data is transferred to the first FIFO register and FRtl, and when the next data enters the first FIFO register and FRtl, the data is transferred to the second FIFO register. Transferred to FRt 2. In this way, multiple pieces of data are taken in one after another and stored in the FIFO register.
When 1 to F Rt n become full, an interrupt is applied to the CPU and output of transmission data is interrupted.

Then, when a transmission clock (transmission request signal) CLKt is sent from the transmission receiving side to the transmission unit 1a, another microinstruction is read from the control unit CNTt, and the final stage (nth stage) The data in the FIFO register FRtn is transferred to the transmission shift register TSR, the shift operation of the shift register TSR is started, the parallel data is converted to serial data, and the data in the above clock CL is transferred to the transmission shift register TSR.
It is output to the outside in synchronization with Kt. The number of transferred bits at this time is counted by an adder AUt, and when it reaches 8 bits, the next data is transferred from the FIFO register FRtn to the shift register TSR, converted to serial data, and outputted one after another.

The above operation is performed by the microprogram control unit CNTt.
It is designed to be executed by control signals from.

On the other hand, in the receiving section 1b, the transfer lock C is transferred from the outside.
When LKr comes in, the reception side control unit CNTr is activated, the reception shift register R8R is shifted, and the serial data transferred from the outside is successively taken in. When the reception shift register R8R is filled with 1 byte of data, the FIFO register FRrl
will be forwarded to. This is repeated until all FIFO registers FRn1 to FRrn are filled with received data, and an interrupt is issued to the CPU. Then, the CPU gives a reception command via the interface circuit ITF, which activates the control unit CNTr, switches the changeover switch S, and changes the FIFO register F Rn.
1 to F Rr n are operated and the received data is sequentially supplied to the CPU via the common bus BUSc and the system bus 5-BUS. When the transfer of all the received data is completed, the CPU is interrupted again and the CPU is ready to receive the first received data.

In the embodiment described above, since the transmitting section 1a and the receiving section 1b having the same architecture are provided separately, the transmitting operation and the receiving operation described above can proceed in parallel.

In the above embodiment, the FIFO register FRtl~
FRtn, FRrl to FRrn are connected to the same buses BUSt and BUSr as the temporary register and adder, respectively, but the FIFO cash register and temporary register bus are separated and only the control section is shared. You can.

However, in the above embodiment, if the FIFO cash register is connected to the same internal bus as the polar register, if it is not connected to the FIFO cash register, it can be used as a temporary register. When the registers are not used, they can be used as FIFO registers. Moreover, the conventional F
The IFO register was a static type register consisting of a flip-flop register, but by providing it in the execution unit consisting of a temporary register, an adder, etc., a dynamic type register using a transfer gate as a FIFO register was created. This can also reduce the area occupied by the FIFO.

Even if it is stored in the FIFO register unit, in a communication LSI like the one in the above embodiment, data only comes in once every few machine cycles, which is the operating period of the execution unit. Therefore, it is possible to sufficiently deal with this problem by using a register for FIFO while the execution unit is at rest.

As explained above, in the above embodiment, the registers constituting the PIFO are controlled by a microprogram control control unit, and the microprogram control unit controls the FIFO control unit and circuits such as the execution unit inside the LSI. Since the FIFO is standardized, there is no need for dedicated control logic to control the FIFO.
This is compared to a case where the FO control section is separate from the execution unit control section consisting of an adder, a temporary register, etc., and this is constructed from a random logic circuit.

This has the effect of reducing the area occupied by the control section and, in turn, reducing the chip size of an LSI having a FIFO.

In addition, the registers constituting the FIFO are controlled by a control section using a microprogram control system, and the FIFO
The O control unit and the microprogram control unit that controls circuits such as the execution unit inside the LSI are shared, and they are connected to the same internal bus as the FIFO register, polar register, and adder. Therefore, FIF
Due to the ability to treat the O cash register register in the same way as the polar register, when it is not used as a FIFO cash register register, it can be used as a temporary register.
In addition, when the temporary register is not in use, it can be used as a FIFO cash register, and by configuring it as a FIFO cash register dynamic type, the occupied area can be further reduced. .

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above example,
Although the execution unit containing the FIFO register is shown as consisting of a temporary register and an adder, it may also include general-purpose registers in a microprocessor, ALU (logic unit), etc. Of course.

In the above explanation, the invention made by the present inventor was mainly applied to communication LSI, which is the background field of application. A data processing device having the following functions can be generally used.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, it is possible to reduce the chip size of an LSI having a FIFO and to simplify the logic design.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a communication LSI. 1a... transmitter, 1b... receiver, CNTt. CNTr”=control unit (micro ROM), FRt 1-
FRtn, FRrl ~ FRrn..."FIFO register register R...Transmission shift register, R8R...
...Receiving shift register, BUSt...Sending side internal bus, B U Sr...Receiving side internal bus, B
US c...Common bus, 5-BUS...System bus.

Claims (1)

[Claims] 1. A data processing device comprising an execution unit having various registers and an arithmetic unit, a control section for controlling the execution unit, and a first-in, first-out data storage section. , characterized in that the control section of the execution unit and the control section of the first-in, first-out type data storage section are shared, and the common control section is constituted by a read-only memory in which a microprogram is stored. data processing equipment. 2. A patent claim characterized in that the first-in, first-out type data storage section is constituted by a plurality of registers, and the registers are connected to a common internal bus with the registers in the execution unit. The data processing device according to item 1. 3. The data processing according to claim 1 or 2, wherein the first-in, first-out type data storage section is provided separately for data transmission and data reception. Device.