JPS6381478U - - Google Patents
Info
- Publication number
- JPS6381478U JPS6381478U JP17460686U JP17460686U JPS6381478U JP S6381478 U JPS6381478 U JP S6381478U JP 17460686 U JP17460686 U JP 17460686U JP 17460686 U JP17460686 U JP 17460686U JP S6381478 U JPS6381478 U JP S6381478U
- Authority
- JP
- Japan
- Prior art keywords
- field
- composite video
- video signal
- display memory
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 12
- 239000002131 composite material Substances 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Image Input (AREA)
Description
第１図は本考案の一実施例のメモリ切換え回路
１０の構成を示すブロツク図、第２図はフイール
ド判別部１７の構成を示す回路図、第３図はメモ
リ選択部１８の構成を示す回路図、第４図および
第５図はフイールド判別部１７およびメモリ制御
部１８の動作をそれぞれ説明するタイミングチヤ
ート、第６図は従来技術のメモリ切換え回路１の
構成を示すブロツク図である。
１０……メモリ切換え回路、１３，１４……表
示用メモリ、１５……同期分離部、１６……同期
信号発生部、１７……フイールド判別部、１８…
…メモリ選択部。
FIG. 1 is a block diagram showing the configuration of a memory switching circuit 10 according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of the field discrimination section 17, and FIG. 3 is a circuit diagram showing the configuration of the memory selection section 18. 4 and 5 are timing charts illustrating the operations of the field discrimination section 17 and the memory control section 18, respectively, and FIG. 6 is a block diagram showing the configuration of the memory switching circuit 1 of the prior art. 10...Memory switching circuit, 13, 14...Display memory, 15...Synchronization separation section, 16...Synchronization signal generation section, 17...Field discrimination section, 18...
...Memory selection section.
Claims (1)
の表示用メモリと、 複合映像信号中の同期信号によつて、複合映像
信号の隅数フイールドと奇数フイールドとを判別
するフイールド判別部と、 フイールド判別部からの判別信号によつて、か
つ垂直同期信号に同期して、入力／出力対象の表
示用メモリを選択する表示用メモリ選択部とを含
み、 上記表示用メモリの選択は、複合映像信号の偶
数フイールドと奇数フイールドとを奇数番目また
は偶数番目の表示用メモリに順次記憶させるよう
に行なわれることを特徴とする表示用メモリの切
換え回路。[Claims for Utility Model Registration] A plurality of display memories in which the composite video signal is stored and ordered, and a synchronization signal in the composite video signal to determine the corner number field and the odd number field of the composite video signal. a field discriminator; and a display memory selector that selects a display memory to be input/output in accordance with a discrimination signal from the field discriminator and in synchronization with a vertical synchronization signal; 1. A display memory switching circuit, wherein the selection is performed so that an even field and an odd field of a composite video signal are sequentially stored in an odd or even display memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17460686U JPS6381478U (en) | 1986-11-12 | 1986-11-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17460686U JPS6381478U (en) | 1986-11-12 | 1986-11-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6381478U true JPS6381478U (en) | 1988-05-28 |
Family
ID=31113149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17460686U Pending JPS6381478U (en) | 1986-11-12 | 1986-11-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6381478U (en) |
-
1986
- 1986-11-12 JP JP17460686U patent/JPS6381478U/ja active Pending
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