JPS6380873U - - Google Patents
Info
- Publication number
- JPS6380873U JPS6380873U JP17400686U JP17400686U JPS6380873U JP S6380873 U JPS6380873 U JP S6380873U JP 17400686 U JP17400686 U JP 17400686U JP 17400686 U JP17400686 U JP 17400686U JP S6380873 U JPS6380873 U JP S6380873U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- dielectric substrate
- printed circuit
- components
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims 2
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structure Of Printed Boards (AREA)
Description
図は本考案の一実施例の斜視図である。
１……プリント基板、２……誘電体基板、３…
…回路パターン、４……実装部品、５……グラン
ドパターン、６……スルーホール。
…回路パターン、４……実装部品、５……グラン
ドパターン、６……スルーホール。
Claims (1)
- 誘電体基板の表面に導電膜で回路パターン及び
グランドパターンを形成し、互いにアイソレーシ
ヨンが必要とされる部品を実装するプリント基板
において、前記各実装部品間の位置に、前記誘電
体基板の全厚さに亘つて開設した多数のスルーホ
ールを互いに接触した状態で直列配置し、かつこ
のスルーホールを所定の電位に保持したことを特
徴とする高アイソレーシヨンプリント基板。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17400686U JPS6380873U (ja) | 1986-11-14 | 1986-11-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17400686U JPS6380873U (ja) | 1986-11-14 | 1986-11-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6380873U true JPS6380873U (ja) | 1988-05-27 |
Family
ID=31112001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17400686U Pending JPS6380873U (ja) | 1986-11-14 | 1986-11-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6380873U (ja) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07170090A (ja) * | 1993-12-15 | 1995-07-04 | Nec Corp | 混成集積回路装置 |
| JP2012150062A (ja) * | 2011-01-21 | 2012-08-09 | Secure Design Solutions Inc | 静電気容量検知型指紋読取りセンサ |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS497453B1 (ja) * | 1968-07-02 | 1974-02-20 |
-
1986
- 1986-11-14 JP JP17400686U patent/JPS6380873U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS497453B1 (ja) * | 1968-07-02 | 1974-02-20 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07170090A (ja) * | 1993-12-15 | 1995-07-04 | Nec Corp | 混成集積回路装置 |
| JP2012150062A (ja) * | 2011-01-21 | 2012-08-09 | Secure Design Solutions Inc | 静電気容量検知型指紋読取りセンサ |