JPS6380580A - Manufacture of josephson junction device - Google Patents
Manufacture of josephson junction deviceInfo
- Publication number
- JPS6380580A JPS6380580A JP61224794A JP22479486A JPS6380580A JP S6380580 A JPS6380580 A JP S6380580A JP 61224794 A JP61224794 A JP 61224794A JP 22479486 A JP22479486 A JP 22479486A JP S6380580 A JPS6380580 A JP S6380580A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode
- junction
- wirings
- vacuum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000002161 passivation Methods 0.000 claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 21
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 11
- 238000005530 etching Methods 0.000 abstract description 11
- 239000001301 oxygen Substances 0.000 abstract description 11
- 229910052760 oxygen Inorganic materials 0.000 abstract description 11
- 125000006850 spacer group Chemical group 0.000 abstract description 5
- 238000004544 sputter deposition Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 2
- 239000000356 contaminant Substances 0.000 abstract 1
- 238000009751 slip forming Methods 0.000 abstract 1
- 238000011109 contamination Methods 0.000 description 16
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 239000010955 niobium Substances 0.000 description 6
- ZKATWMILCYLAPD-UHFFFAOYSA-N niobium pentoxide Chemical compound O=[Nb](=O)O[Nb](=O)=O ZKATWMILCYLAPD-UHFFFAOYSA-N 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 239000002887 superconductor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- HFLAMWCKUFHSAZ-UHFFFAOYSA-N niobium dioxide Inorganic materials O=[Nb]=O HFLAMWCKUFHSAZ-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001420 photoelectron spectroscopy Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はジョセフソン接合素子の製造方法に関し、特に
パシベーションを施したジョセフソン接合素子の製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a Josephson junction element, and more particularly to a method for manufacturing a passivated Josephson junction element.
（従来の技術）
一般に、集積回路チップの表面は、大気中の水蒸気や酸
素、各プロセスの雰囲気によって引き起こされる素子特
性の劣化を防ぐために、パシベーション層で被覆される
。特に、ジョセフソン集積回路では、その基本要素であ
るジョセフソン接合素子が数人〜数１０人の非常に薄い
トンネル障壁層を数１００ＯＡの多結晶金属でなる上下
電極ではさんだ構造であるため外部雰囲気の影響を受は
易く、パシベーションが不可欠である。(Prior Art) Generally, the surface of an integrated circuit chip is coated with a passivation layer in order to prevent deterioration of device characteristics caused by water vapor and oxygen in the atmosphere and the atmosphere of various processes. In particular, in Josephson integrated circuits, the Josephson junction element, which is its basic element, has a structure in which a very thin tunnel barrier layer of several to several tens of layers is sandwiched between upper and lower electrodes made of polycrystalline metal of several hundred OA, so the external atmosphere is passivation is essential.
従来例を第４図（ａ）〜（Ｏを用いて工程順に説明する
。まず、第４図（ａ）に示すように、基板４１上に下部
電極及び下部配線４２、トンネル障壁層４３、上部電極
４４の３層膜を形成する。下部電極及び下部配線４２、
上部電極４４は蒸着法やスパッタ法で被着した超伝導体
膜である。トンネル障壁層４３は下部電極及び下部配線
４２表面を熱やプラズマにより酸化するか、絶縁膜など
を被着して形成する。上記３層膜４２、４３．４４のパ
ターニングは通常のりソグラフィ技術とエツチング法や
リフトオフ法などの加工技術を用いて行う。次に第４図
（ｂ）に示すように、上部電極４４上の接合部となる場
所にエツチングマスク４５を形成し、反応性イオンエツ
チング法やイオンミリング法により上部電極４４をパタ
ーニングして接合部を規定する。次に第４図（ｃ）に示
すように、エツチングマスク４５を残したままスペーサ
層を蒸着する。エツチングマスクをリフトオフして第４
図（ｄ）に示すような構造を得た後、上部電極４４表面
をスパッタクリーニングし、第４図（ｅ）に示すように
上部電極４４と同様な方法で上部配線４７を被着、パタ
ーニングする。このパターニングの際、上部配線４７は
大気にさらされたり、リソグラフィの各処を追加する場
合にはパシベーション層４９はスペーサ層となる。ここ
では、従来例として接合部の規定にエツチング法を用い
たジョセフソン接合素子の製造方法を述べたが、リフト
オフ法を用いた場合についても本発明の利用分野である
パシベーション技術に関しては同様である。A conventional example will be explained in the order of steps using FIGS. 4(a) to 4(O). First, as shown in FIG. Form a three-layer film of electrode 44. Lower electrode and lower wiring 42,
The upper electrode 44 is a superconductor film deposited by vapor deposition or sputtering. The tunnel barrier layer 43 is formed by oxidizing the surfaces of the lower electrode and lower wiring 42 by heat or plasma, or by covering them with an insulating film or the like. The three-layer films 42, 43, and 44 are patterned using ordinary lithography and processing techniques such as etching and lift-off. Next, as shown in FIG. 4(b), an etching mask 45 is formed on the upper electrode 44 at a location where the joint will be formed, and the upper electrode 44 is patterned by reactive ion etching or ion milling to form the joint. stipulates. Next, as shown in FIG. 4(c), a spacer layer is deposited with the etching mask 45 left in place. Lift off the etching mask and
After obtaining the structure shown in FIG. 4(d), the surface of the upper electrode 44 is sputter-cleaned, and the upper wiring 47 is deposited and patterned in the same manner as the upper electrode 44, as shown in FIG. 4(e). . During this patterning, the upper wiring 47 may be exposed to the atmosphere, or the passivation layer 49 will serve as a spacer layer if various lithographic areas are added. Here, as a conventional example, a method for manufacturing a Josephson junction element using an etching method to define a junction has been described, but the passivation technology, which is the field of application of the present invention, is the same even when a lift-off method is used. .
（発明が解決しようとする間赳点）
従来の方法では、第４図（ｆ）に示したようにパシベー
ション層４９は上部配線４７表面に大気への露出やりソ
ゲラフイエ程で形成された汚染層４８を残したまま形成
される。そのため、汚染層を構成している酸素や水分が
経時的に、あるいは比較的高温を必要とする後工程で上
部配線４７や上部電極４４を通ってトンネル障壁層４３
の近傍まで拡散し、その結果接合特性が劣化したり、接
合電流が低下するという問題を生じる。特に、ジョセフ
ソン接合素子の上部電極４４や上部配線４７は室温程度
の低い基板温度で形成された多結晶金属であるため、上
部配線４７表面の不純物が結晶粒界を通して拡散し易く
、しかもトンネル障壁層は数人〜数１０人と非常に薄い
ためその接合特性に及ぼす影響は深刻である。(Problems to be Solved by the Invention) In the conventional method, as shown in FIG. 4(f), the passivation layer 49 is a contamination layer 48 formed on the surface of the upper wiring 47 by exposure to the atmosphere or by a drying process. It is formed with . Therefore, oxygen and moisture constituting the contamination layer pass through the upper wiring 47 and the upper electrode 44 over time or in a post process that requires relatively high temperatures to the tunnel barrier layer 43.
This causes problems such as deterioration of junction characteristics and reduction of junction current. In particular, since the upper electrode 44 and the upper wiring 47 of the Josephson junction element are made of polycrystalline metal formed at a low substrate temperature of about room temperature, impurities on the surface of the upper wiring 47 are likely to diffuse through the grain boundaries, and the tunnel barrier Since the layers are very thin, ranging from a few to several tens of layers, the effect on the bonding properties is serious.
本発明の目的は、このような従来の欠点を取り除いたジ
ョセフソン接合素子の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a Josephson junction device that eliminates such conventional drawbacks.
（問題点を解決するための手段）
本発明によれば、下部電極と、この下部電極上に形成さ
れたトンネル障壁層と、このトンネル障壁層を介して前
記下部電極と対向して形成された上部電極とこの上部電
極上に電気接触を伴って形成された上部配線とを有する
ジョセフソン接合素子の製造方法において、真空中で前
記上部配線をか得られる。(Means for Solving the Problems) According to the present invention, a lower electrode, a tunnel barrier layer formed on the lower electrode, and a tunnel barrier layer formed opposite to the lower electrode with the tunnel barrier layer interposed therebetween. In a method for manufacturing a Josephson junction element having an upper electrode and an upper wiring formed on the upper electrode with electrical contact, the upper wiring can be obtained in a vacuum.
（作用）
本発明では、上部配線とその上のパシベーション層が真
空中で連続被着される。そのため、従来例のように、上
部配線表面に、大気への露出やパターニング工程で形成
される汚染層がなく、経時的に、あるいは後工程の加熱
プロセスで汚染層を構成している酸素や水分がトンネル
障壁層近傍まで拡散し、接合特性を劣化させるという間
圧がない。(Function) In the present invention, the upper wiring and the passivation layer thereon are continuously deposited in a vacuum. Therefore, unlike conventional examples, there is no contamination layer on the upper wiring surface that is formed during exposure to the atmosphere or during the patterning process. There is no pressure that would diffuse into the vicinity of the tunnel barrier layer and deteriorate the junction characteristics.
（実施例） 本発明の実施例を図面を参照して詳細に説明する。(Example) Embodiments of the present invention will be described in detail with reference to the drawings.
まず、第１図（ａ）に示すように基板１１上に下部電極
及び下部配線１２、トンネル障壁層１３、上部電極１４
の３層膜を形成する。下部電極及び下部配線１２、上部
電極１４は蒸着法やスパッタ法で被着されたニオブ（Ｎ
ｂ）や鉛（Ｐｂ）など超伝導体膜である。トンネル障壁
層１３は下部電極及び下部配線１２表面を熱やプラズマ
により酸化するか、アルミニウム（ＡＩ）やシリコン（
Ｓｉ）などでなる厚さ数１０人の金属膜や半導体膜を被
着した後、表面を酸化して形成する。上記３層膜のパタ
ーニングは通常のりソグラフィ技術と加工技術を用いて
行う５次に、第１図（ｂ）に示すように、上部電極１４
上の接合部となる場所にエツチングマスク１５を形成し
、反応性イオンエツチング法やイオンミリング法により
上部電極１４をパターニングして接合部を規定する。次
に、第１図（Ｃ）に示すように、エツチングマスク１５
を残したまま一酸化硅素（Ｓｉｎ）などでなるスペーサ
層１６を蒸着する。エツチングマスク１５をリフトオフ
して第１図（ｄ）に示すような構造を形成した後、上部
電極１４表面をスパツベーション層１８はスパッタ法や
蒸着法で被着された二酸化硅素（ＳｉＯ２）などの絶縁
膜や半導体膜である。本実施例では、上部配線１７表面
が直接大気にさらされたり、リソグラフィ工程を経るこ
とがなく、この表面には酸素や水分などに依る汚染層は
形成されない。次に、第１図（Ｏに示すように通常のり
ソグラフイ技術と反応性イオンエツチングやイオンミリ
ングなどの加工技術を用いて、上部配線１７とパシベー
ション層１８をパターニングする。First, as shown in FIG.
A three-layer film is formed. The lower electrode, lower wiring 12, and upper electrode 14 are made of niobium (N) deposited by vapor deposition or sputtering.
b) or a superconductor film such as lead (Pb). The tunnel barrier layer 13 is formed by oxidizing the surface of the lower electrode and the lower wiring 12 by heat or plasma, or by oxidizing the surface of the lower electrode and lower wiring 12 with aluminum (AI) or silicon (
After depositing a metal film or semiconductor film made of Si) or the like to a thickness of several tens of layers, the surface is oxidized to form the film. The above-mentioned three-layer film is patterned in the fifth step using ordinary lithography technology and processing technology.As shown in FIG.
An etching mask 15 is formed at the location where the upper joint will be formed, and the upper electrode 14 is patterned by reactive ion etching or ion milling to define the joint. Next, as shown in FIG. 1(C), an etching mask 15 is formed.
A spacer layer 16 made of silicon monoxide (Sin) or the like is evaporated while leaving the . After lifting off the etching mask 15 to form a structure as shown in FIG. 1(d), a sputtering layer 18 is formed of silicon dioxide (SiO2) or the like deposited by sputtering or vapor deposition on the surface of the upper electrode 14. These are insulating films and semiconductor films. In this embodiment, the surface of the upper wiring 17 is not directly exposed to the atmosphere or undergoes a lithography process, and no contamination layer due to oxygen, moisture, etc. is formed on this surface. Next, as shown in FIG. 1(O), the upper wiring 17 and the passivation layer 18 are patterned using ordinary lamination techniques and processing techniques such as reactive ion etching and ion milling.
上部配線１７表面に従来例のように汚染層が存在する場
合と、本実施例のように存在しない場合とで接合界面に
与える影響がどうであるかを調べたもので、以下にその
結果を示す。−例として、Ｎｂ（２０００人）／Ｎｂ２
０５（〜２０人）／Ｐｂ（１５００人）接合における熱
処理前後のオージェ深さ方向プロフィルを第２図（ａ）
、 （ｂ）、第３図（ａ）、 （ｂ）に示す。第２図（
ａ）、 （ｂ）は接合を形成した後、−度大気に露出し
てＰｂ表面に汚染層を形成してから、２Ｘ１０−８Ｔｏ
ｒｒ以上の高真空中での熱処理の効果を調べた結果であ
り、第３図（ａ）、 （ｂ）は加速試験する目的で行っ
た。ここでは、鎗スパッタクリーニングで上部電極とな
るｐｂ裏表面汚染層を除去して熱処理しているが、上部
電極を形成した後真空を保ったまま熱処理しても汚染層
が存在しない状態で熱処理している点では同じであるの
で本実験から本発明の効果を推測できる。熱処理条件は
２１０°Ｃ１１時間である。第２図（ａ）に示すように
ｐｂ裏表面酸素を主とする汚染層が存在する場合には、
第２図（ｂ）に示すように熱処理によって酸素が接合界
面まで拡散しトンネル障壁層の膜厚を増加させる。また
、Ｘ線励起光電子分光測定からＮｂ／Ｎｂ２Ｏ５界面で
は、ＮｂＯ，ＮｂＯ２といった低級酸化′１層が存在し
ない場合には、第３図（ｂ）に示すように、Σ
トンネル障壁層の膜厚の増加はない。また、Ｎｂ／Ｎｂ
２Ｏ５界面でも低級酸化物の増加は第２図（ｂ）の場合
はど著しくはない。以上の結果から明らかなように、上
部配線の表面に汚染がない場合には、トンネル障壁層の
膜厚の増加による接合電流の減少や、遷移領域の増加、
による接合特性の劣化という問題がない。ここでは、Ｎ
ｂ／Ｎｂ２Ｏ５／Ｐｂ接合について述べたが、他の接合
に対しても同様な結果が得られる。また、パシベーショ
ン層１８に金属や半導体を用いる場合は、これらの金属
や半導体の方が上部配線を構成する金属よりもパシベー
ション層１８表面に形成される酸化物などの汚染層に対
して酸素など一原子当たりの生成エネルギーが小さいパ
シベーション層１８を選べば、パシベーション層１８表
面からトンネル障壁層への酸素などの汚染層を形成する
不純物の拡散が防止される。さらに、パシベーション層
１８に金属や半導体の酸化物や窒化物などの化合物を用
いる場合には、酸素や窒素などの一原子当たりの生成エ
ネルギーが上部配線を構成する金属の同反応に対する生
成エネルギーより小さいパシベーション層を選択すれば
、パシベーション層１８自体からトンネル障壁層への酸
素や窒素などの拡散を防ぐのに有効である。This study investigated the effect on the bonding interface when a contamination layer exists on the surface of the upper wiring 17 as in the conventional example, and when it does not exist as in this example. The results are shown below. show. - For example, Nb (2000 people)/Nb2
Fig. 2(a) shows the Auger depth profile before and after heat treatment for 05 (~20 people)/Pb (1500 people) bonding.
, (b), as shown in Figures 3 (a) and (b). Figure 2 (
a) and (b) after forming the bond, exposing it to the atmosphere for -degrees to form a contamination layer on the Pb surface, and then applying 2X10-8To
These are the results of investigating the effect of heat treatment in a high vacuum of rr or higher, and Figures 3(a) and 3(b) were conducted for the purpose of accelerated testing. Here, the PB back surface contamination layer that will become the upper electrode is removed by sputter cleaning and heat treatment is performed, but even if the heat treatment is performed while maintaining a vacuum after forming the upper electrode, no contamination layer is present. The effects of the present invention can be inferred from this experiment. The heat treatment conditions were 210°C and 11 hours. As shown in Figure 2(a), if there is a contamination layer mainly composed of oxygen on the back surface of PB,
As shown in FIG. 2(b), the heat treatment causes oxygen to diffuse to the junction interface, increasing the thickness of the tunnel barrier layer. Furthermore, X-ray excited photoelectron spectroscopy shows that at the Nb/Nb2O5 interface, if there is no lower oxidation '1 layer such as NbO or NbO2, the film thickness of the Σ tunnel barrier layer decreases as shown in Figure 3(b). There is no increase. Also, Nb/Nb
Even at the 2O5 interface, the increase in lower oxides is not as significant as in the case of FIG. 2(b). As is clear from the above results, when there is no contamination on the surface of the upper wiring, the junction current decreases due to the increase in the thickness of the tunnel barrier layer, the transition region increases,
There is no problem of deterioration of bonding characteristics due to Here, N
Although the b/Nb2O5/Pb junction has been described, similar results can be obtained for other junctions. Furthermore, when a metal or a semiconductor is used for the passivation layer 18, these metals or semiconductors are more sensitive to oxygen and other contamination layers such as oxides formed on the surface of the passivation layer 18 than the metal constituting the upper wiring. By selecting a passivation layer 18 with a low generation energy per atom, diffusion of impurities such as oxygen that forms a contamination layer from the surface of the passivation layer 18 to the tunnel barrier layer is prevented. Furthermore, when a compound such as a metal or semiconductor oxide or nitride is used for the passivation layer 18, the production energy per atom of oxygen, nitrogen, etc. is smaller than the production energy for the same reaction of the metal constituting the upper wiring. Selecting a passivation layer is effective in preventing diffusion of oxygen, nitrogen, etc. from the passivation layer 18 itself to the tunnel barrier layer.
本実施例では接合部の規定にエツチング法を用いたジョ
セフソン接合素子の製造方法を述べたが、リフトオフ法
を用いた場合についてもパシベーション技術は同じであ
り、同様な効果が得られる。In this embodiment, a method of manufacturing a Josephson junction element using an etching method to define the joint portion has been described, but the passivation technique is the same when the lift-off method is used, and the same effect can be obtained.
（発明の効果）
以上説明したように本発明によれば、上部配線とその上
のパシベーション層が真空中で連続被着されるため、上
部配線表面には汚染層が形成されない。従って、汚染層
を構成する酸素や水分が接合界面まで拡散し接合特性を
劣化させるという間開がなく、経時的あるいは熱的に安
定で信頼性の高いジョセフソン接合素子を製造すること
ができる。(Effects of the Invention) As explained above, according to the present invention, since the upper wiring and the passivation layer thereon are continuously deposited in a vacuum, no contamination layer is formed on the surface of the upper wiring. Therefore, there is no possibility that oxygen or moisture constituting the contamination layer will diffuse to the bonding interface and deteriorate the bonding characteristics, making it possible to manufacture a highly reliable Josephson junction element that is stable over time or thermally.
第１図（ａ）〜（Ｏは本発明の接合素子の製造方法を工
程順に示す断面図、第２図（ａ）、（ｂ）、第３図（ａ
）、 （ｂ）はそれぞれ接合表面に汚染層が存在する場
合、および存在しない場合のＮｂ／Ｎｂ２Ｏ５／Ｐｂ接
合における熱処理前後のオージェ深さ方向プロフィルを
示す図、竿部電極、１５．４５はエツチングマスク、１
６．４６はスペーサ層、１７．４７は上部配線、１８．
４９はパシベーション層、４８は汚染層である。FIGS. 1(a) to (O are cross-sectional views showing the method for manufacturing a bonding element of the present invention in order of process, FIGS. 2(a), (b), and 3(a).
) and (b) are diagrams showing the Auger depth profile before and after heat treatment in Nb/Nb2O5/Pb junctions with and without a contamination layer on the joint surface, respectively, the rod electrode, 15.45 is the etching mask, 1
6.46 is a spacer layer, 17.47 is an upper wiring, 18.
49 is a passivation layer, and 48 is a contamination layer.
Claims (1)
層と、このトンネル障害層を介して前記下部電極と対向
して形成された上部電極と、この上部電極に電気接触を
伴って形成された上部配線とを有するジョセフソン接合
素子の製造方法において、真空中で前記上部配線を被着
した後、真空を保持したままこの上部配線上にパシベー
ション層を被着し、前記上部配線と前記パシベーション
層を同時にパターニングすることを特徴とするジョセフ
ソン接合素子の製造方法。A lower electrode, a tunnel barrier layer formed on the lower electrode, an upper electrode formed opposite to the lower electrode via the tunnel barrier layer, and an upper electrode formed in electrical contact with the upper electrode. In the method for manufacturing a Josephson junction device having an upper wiring, after the upper wiring is deposited in a vacuum, a passivation layer is deposited on the upper wiring while maintaining the vacuum, and the upper wiring and the passivation layer are bonded together. A method for manufacturing a Josephson junction device, characterized by simultaneously patterning.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61224794A JPS6380580A (en) | 1986-09-25 | 1986-09-25 | Manufacture of josephson junction device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61224794A JPS6380580A (en) | 1986-09-25 | 1986-09-25 | Manufacture of josephson junction device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6380580A true JPS6380580A (en) | 1988-04-11 |
Family
ID=16819303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61224794A Pending JPS6380580A (en) | 1986-09-25 | 1986-09-25 | Manufacture of josephson junction device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6380580A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02139978A (en) * | 1988-11-21 | 1990-05-29 | Matsushita Electric Ind Co Ltd | Josephson element and its manufacture |
-
1986
- 1986-09-25 JP JP61224794A patent/JPS6380580A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02139978A (en) * | 1988-11-21 | 1990-05-29 | Matsushita Electric Ind Co Ltd | Josephson element and its manufacture |
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