JPS6380535A - Plasma processing apparatus - Google Patents

Plasma processing apparatus

Info

Publication number
JPS6380535A
JPS6380535A JP22549286A JP22549286A JPS6380535A JP S6380535 A JPS6380535 A JP S6380535A JP 22549286 A JP22549286 A JP 22549286A JP 22549286 A JP22549286 A JP 22549286A JP S6380535 A JPS6380535 A JP S6380535A
Authority
JP
Japan
Prior art keywords
wafer
substrate
electrode
semiconductor wafer
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22549286A
Other languages
Japanese (ja)
Other versions
JPH0624187B2 (en
Inventor
Takao Horiuchi
堀内 隆夫
Yoshifumi Tawara
田原 好文
Izumi Arai
泉 新井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to JP61225492A priority Critical patent/JPH0624187B2/en
Publication of JPS6380535A publication Critical patent/JPS6380535A/en
Publication of JPH0624187B2 publication Critical patent/JPH0624187B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To improve the adhesion property between a substrate to be processed and an electrode surface contacted therewith for improving electrical coupling properties, thermal conductivity and uniformity and to improve the processing efficiency, by providing a conducting resin body on the electrode surface contacted with the substrate. CONSTITUTION:A semiconductor wafer 20 is disposed on a wafer push-up pin 35 by a wafer conveyor and the wafer push-up pin 35 is lowered. As it is, there is a gap between the semiconductor wafer and the periphery of a wafer carrying base 22a whose top face is gradually projected. But this gap is eliminated by lowering a clamp ring 9 for pressing the periphery of the semiconductor wafer 20 against the wafer carrying base 22a. Such gap can not be eliminated completely by conventional wafer fixing mechanisms and the gap causes, in turn, deterioration in electrical coupling properties or thermal conductivity which, in turn, causes ununiform etching or decrease of etching efficiency. According to this embodiment, however, a conductive silicon rubber 33 having high elasticity is mounted on the wafer carrying base 22a so as to provide improved adhesion properties. Thus, the electrical coupling properties and the thermal conductivity between the semiconductor wafer 20 and the wafer carrying base 22a can be improved substantially.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、プラズマを利用して半導体基板を処理するプ
ラズマ処理装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a plasma processing apparatus that processes a semiconductor substrate using plasma.

(従来の技術) 近年半導体処理装置として、プラズマCVD装置、プラ
ズマエツチング装置、スパッタリング装置等のプラズマ
を利用した半揮体処理装置が広く普及している。
(Prior Art) In recent years, semi-volatile processing apparatuses that utilize plasma, such as plasma CVD apparatuses, plasma etching apparatuses, and sputtering apparatuses, have become widely used as semiconductor processing apparatuses.

例えばプラズマエツチング装置では、エツチング槽内に
反応気体を導入してこの反応気体をプラズマ状態に励起
させ、発生した活性成分と基板例えば半導体ウェハ上の
処理対称物とを反応させてエツチング処理を行なう。以
下に、プラズマ処理装置の一例としてこのプラズマエツ
チング装置について説明する。
For example, in a plasma etching apparatus, a reactive gas is introduced into an etching tank, the reactive gas is excited to a plasma state, and the generated active component reacts with a target object on a substrate, such as a semiconductor wafer, to perform an etching process. This plasma etching apparatus will be described below as an example of a plasma processing apparatus.

第7図は平行平板型電極を有するプラズマエツチング装
置を示しており、気密を保持するエツチング槽1内に半
導体ウェハ2のa置台と6なる下部電極3と、この下部
電極3と対向して高周波電f!4が配置されている。高
周波電極4は反応気体の導入管として作用するような構
造となっており、その下端部の電極部4aには多孔質部
材を用いている。
FIG. 7 shows a plasma etching apparatus having parallel plate type electrodes, in which a lower electrode 3, which serves as a mounting table 6 for a semiconductor wafer 2, is placed in an etching bath 1 which maintains airtightness, and a high-frequency etching device is placed opposite to this lower electrode 3. Electric f! 4 is placed. The high frequency electrode 4 has a structure that acts as a reaction gas introduction tube, and a porous member is used for the electrode portion 4a at the lower end thereof.

このようなプラズマエツチング装置では、エツチング槽
1内の雰囲気を真空ポンプ5により高真空例えば1O−
6Torrとした後、エツチング槽1内に反応気体源6
から反応気体例えばアルゴンガスをエツチングml内に
導入してエツチング槽1内をエツチング処理に必要な真
空度例えば10’〜1O−2Torrに保持する。
In such a plasma etching apparatus, the atmosphere inside the etching tank 1 is heated to a high vacuum, e.g.
After setting the pressure to 6 Torr, a reactive gas source 6 is placed in the etching tank 1.
A reactive gas, such as argon gas, is introduced into the etching chamber 1 to maintain the inside of the etching tank 1 at a vacuum level of, for example, 10' to 10@-2 Torr, which is necessary for the etching process.

次に高周波電極4に高周波;カフを印加して反応気体を
プラズマ化させ、このガスプラズマ8の反応成分により
エツチング処理を行なう。
Next, a high frequency cuff is applied to the high frequency electrode 4 to turn the reactive gas into plasma, and the reactive components of this gas plasma 8 perform an etching process.

ところで上述したようなプラズマエツチング装置では、
下部電極3上に直接半導体ウェハ2が当接する構造であ
るので、半導体ウェハ2と下部電極3との密着性が不十
分であると半導体ウェハ2と下部電極3間に間隙が生じ
てしまい、この間隙により電気的結合性や熱伝導性の低
下を招く恐れがある。
By the way, in the plasma etching apparatus as mentioned above,
Since the structure is such that the semiconductor wafer 2 is in direct contact with the lower electrode 3, if the adhesion between the semiconductor wafer 2 and the lower electrode 3 is insufficient, a gap will be created between the semiconductor wafer 2 and the lower electrode 3. There is a risk that electrical connectivity and thermal conductivity will be lowered due to gaps.

電気的結合性の低下は、処理効率の低下例えばプラズマ
エツチング装置ではエツチング処理率(以下エツチング
レート)の低下や処理むら発生等の原因となり、熱伝導
性の低下は半導体ウェハの温度上昇を招きウェハに塗布
されているフォトレジストを軟化させてエツチング処理
中に剥苓し易くしてしまうという問題がある。
A decrease in electrical connectivity causes a decrease in processing efficiency, such as a decrease in etching processing rate (hereinafter referred to as etching rate) and uneven processing in plasma etching equipment.A decrease in thermal conductivity causes a rise in the temperature of the semiconductor wafer, causing the wafer There is a problem in that it softens the photoresist coated on the surface and makes it easier to peel off during the etching process.

そこで従来のプラズマエツチング装置では下部電極の上
面を平坦にして半導体ウェハとの密着性を向上させてい
た。
Therefore, in conventional plasma etching equipment, the upper surface of the lower electrode is flattened to improve its adhesion to the semiconductor wafer.

(発明が解決しようとする問題点) ところが、半導体ウェハはその製造工程においてわずか
ながらの歪が発生し、しかもこの歪は半導体ウェハ個々
により異なるため、下部電極上面を平坦にしてもこの歪
により半導体ウェハと下部電極間には少なからず間隙を
生じてしまい完全な密着ができないという問題があった
(Problem to be solved by the invention) However, a slight amount of distortion occurs in semiconductor wafers during the manufacturing process, and this distortion varies depending on the individual semiconductor wafer. There was a problem in that a considerable gap was created between the wafer and the lower electrode, making it impossible to achieve complete adhesion.

これを解決するために、第8図に示すように下部電極3
の半導体ウェハ2との接触面3aをゆるやかな凸状に形
成するとともに、半導体ウェハ2の固定msとして下部
電極3上方にこれと平行に内径が半導体ウェハ2の径よ
りも若干小さいウェハ固定用のリング体(以下クランプ
リング)9を昇降自在に設け、このクランプリング9を
下降させて半導体ウェハ2周縁部を下部電極3に押圧し
て密着性を高めようとするウェハ固定機構を備えたもの
がある。
In order to solve this problem, as shown in FIG.
The contact surface 3a with the semiconductor wafer 2 is formed into a gentle convex shape, and a wafer fixing plate whose inner diameter is slightly smaller than the diameter of the semiconductor wafer 2 is provided above and parallel to the lower electrode 3 as a fixing ms for the semiconductor wafer 2. A wafer fixing mechanism is provided in which a ring body (hereinafter referred to as a clamp ring) 9 is movable up and down, and the clamp ring 9 is lowered to press the peripheral edge of the semiconductor wafer 2 against the lower electrode 3 to improve adhesion. be.

しかしながら、上述したウェハ固定機構では半導体ウェ
ハ2の歪の曲率と下部電極上面3aの曲率とが大きく異
なる場合には充分に対応しきれなくなり、また半導体ウ
ェハ周縁部のみをクランプリング9で押圧する構造であ
るため、半導体ウェハ固定時にウェハ周縁部からの応力
が中央部に集中して第8図に示すように半導体ウェハ2
が上方に向って弧状に反り、ウェハ2中央部と下部電極
2間に空隙10が生じてしまう。このような状態でエツ
チング処理をした半導体ウェハ2は第9図に示す如く、
ウェハ中央部2aが青色を、ウェハ外周部2bが緑色を
呈する。これはウェハ中央部2aがウェハ外周部2bに
くらベエッチングレートが小さく、均一な処理がなされ
ていないことを示している。
However, the above-mentioned wafer fixing mechanism cannot sufficiently cope with the case where the curvature of the distortion of the semiconductor wafer 2 and the curvature of the lower electrode upper surface 3a are significantly different, and the structure in which only the peripheral edge of the semiconductor wafer is pressed by the clamp ring 9 Therefore, when the semiconductor wafer is fixed, stress from the wafer periphery is concentrated in the center, causing the semiconductor wafer 2 to be fixed as shown in FIG.
is warped upward in an arc shape, and a gap 10 is created between the center of the wafer 2 and the lower electrode 2. The semiconductor wafer 2 that has been etched in this state has the following properties as shown in FIG.
The wafer central portion 2a appears blue, and the wafer outer peripheral portion 2b appears green. This indicates that the etching rate of the wafer central portion 2a is lower than that of the wafer outer peripheral portion 2b, and that uniform processing is not performed.

本発明は上述した問題点を解決するためになされたもの
で、電極と被処理基板との当接面の密着性を向上させる
ことで電気的結合性や熱伝導性を向上させて均一性が良
くしかも処理効率が高いプラズマ処理が可能となるプラ
ズマ処理袋に含提供することを目的とする。
The present invention was made to solve the above-mentioned problems, and by improving the adhesion of the contact surface between the electrode and the substrate to be processed, it improves electrical connectivity and thermal conductivity, and improves uniformity. The object of the present invention is to provide a plasma processing bag that enables plasma processing with good efficiency and high processing efficiency.

[発明の構成] (問題点を解決するための手段) 本発明のプラズマ処理装置は、プラズマ発生源を備えた
気密容器内に電極を配置し、この電極面に被処理基板を
当接させてプラズマ処理を行なうように構成されたプラ
ズマ処理装置において、前記電極の被処理基板との当接
面に導電性樹脂体を設けたことを特徴とするものである
[Structure of the Invention] (Means for Solving the Problems) The plasma processing apparatus of the present invention includes an electrode disposed in an airtight container equipped with a plasma generation source, and a substrate to be processed is brought into contact with the electrode surface. The plasma processing apparatus configured to perform plasma processing is characterized in that a conductive resin body is provided on the surface of the electrode that comes into contact with the substrate to be processed.

導電性樹脂体としてはカーボン含有のシリコンラバー等
の耐熱性、柔軟性に優れたものがよく、厚みは0.2n
+n程度のものが好適である。
The conductive resin body is preferably one with excellent heat resistance and flexibility, such as carbon-containing silicone rubber, and the thickness is 0.2 nm.
A value of approximately +n is suitable.

また電極と導電性樹脂体との取付は手段としては、硬化
後も弾性を有する導電性接着剤を用いた接着や熱圧着等
の手段がよい。
Further, the electrode and the conductive resin body may be attached by adhesion using a conductive adhesive that remains elastic even after curing, thermocompression bonding, or the like.

(作 用) 被処理基板と当接する電極の当接面に設けた導電性合成
樹脂膜は被処理基板と電極との密着性を大幅に向上させ
て電気的結合性や熱伝導性を良好にするので、均一で効
率のよいプラズマ処理が可能となる。
(Function) The conductive synthetic resin film provided on the contact surface of the electrode that contacts the substrate to be processed greatly improves the adhesion between the substrate to be processed and the electrode, resulting in good electrical connectivity and thermal conductivity. Therefore, uniform and efficient plasma processing becomes possible.

(実施例) 以下、本発明をプラズマエツチング装置に適用した一実
施例について図を参照にして説明する。
(Example) Hereinafter, an example in which the present invention is applied to a plasma etching apparatus will be described with reference to the drawings.

第1図および第2図はエツチング処理部を示しており、
このエツチング処理部は図示を省略した気密を保持する
エツチング槽内に設置されている。
Figures 1 and 2 show the etching processing section,
This etching processing section is installed in an etching bath which is kept airtight and is not shown in the drawings.

被処理基板の半導体ウェハ20は図示を省略した搬送装
置にてウェハカセットから取り出されてエツチング処理
部21に搬送され円盤状の下部工!f!22上に載置さ
れてここでエツチング処理を受けた後再び搬送装置にて
搬出される。
The semiconductor wafer 20 as the substrate to be processed is taken out from the wafer cassette by a transport device (not shown) and transported to the etching processing section 21, where a disk-shaped substructure is formed! f! After being placed on the substrate 22 and subjected to etching treatment there, it is carried out again by the conveyance device.

下部電極22の上方には高周波電源40と接続された中
空円磐状の高周波電極23が対向配置されており、この
高周波電極23上面中心部には反応気体発生器24で発
生した反応気体例えばアルゴンガスをエツチング槽1内
へ導入するための導入’Ef 24が垂設されている。
Above the lower electrode 22, a hollow circular rock-shaped high-frequency electrode 23 connected to a high-frequency power source 40 is disposed oppositely, and at the center of the upper surface of the high-frequency electrode 23, a reactive gas generated by a reactive gas generator 24, such as argon, is placed. An introduction 'Ef 24 for introducing gas into the etching tank 1 is vertically provided.

高周波電極23の下面電極部23aは多孔質部材例えば
メツシュ状に形成されたカーボンによつ形成されており
、反応気体導入管23から導入された反応気体がこの下
面電極部23aを通過して下部電極22上に載置された
半導体ウェハ20上に達するような構造としている。
The lower surface electrode portion 23a of the high-frequency electrode 23 is formed of a porous material, for example, carbon formed in a mesh shape, and the reaction gas introduced from the reaction gas introduction tube 23 passes through this lower surface electrode portion 23a to lower the lower surface electrode portion 23a. The structure is such that it reaches above the semiconductor wafer 20 placed on the electrode 22.

下部電極22の側面下方には口字状断面の環状中空体で
ある反応気体排気管26が下部電極22上面と段差を付
けて配設されており、その上面部には多数の排気孔27
が同心円状に一定間隔で穿設されている6反応気体排気
管26外周の一部からは、多数の排気孔27から導入さ
れた使用済反応気体を真空ポンプ28へ導くための配管
29が設けられている。
Below the side surface of the lower electrode 22, a reactive gas exhaust pipe 26, which is an annular hollow body with a mouth-shaped cross section, is disposed with a difference in level from the upper surface of the lower electrode 22, and a large number of exhaust holes 27 are provided in the upper surface.
A pipe 29 is provided from a part of the outer periphery of the six reaction gas exhaust pipes 26, which are concentrically bored at regular intervals, to guide the spent reaction gas introduced from the numerous exhaust holes 27 to the vacuum pump 28. It is being

半導体ウェハ固定機構として、下部電極22上方に半導
体ウェハの径よりも若干小さい内径を有したリング状の
クランプリング30が配置されており、このクランプリ
ング30は下部電極22円周部にそって等間隔に設けら
れた4本のクランプリング支持棒31にて支持されてい
る。4本のクライブリング支持棒31は下部電極22下
方に配置されたクランプリング昇降用駆動機構であるエ
アシリンダ32に接続されており、このエアシリンダ3
2の作用によりクランプリングが昇降可能となっている
As a semiconductor wafer fixing mechanism, a ring-shaped clamp ring 30 having an inner diameter slightly smaller than the diameter of the semiconductor wafer is arranged above the lower electrode 22, and this clamp ring 30 is arranged along the circumference of the lower electrode 22. It is supported by four clamp ring support rods 31 provided at intervals. The four clamp ring support rods 31 are connected to an air cylinder 32 which is a drive mechanism for lifting and lowering the clamp ring and which is arranged below the lower electrode 22.
2, the clamp ring can be moved up and down.

下部電極22は直径約200IIll、厚さ約1011
Ilの円板状をしており、その上面中央部には直径約1
251111、厚さ約8nmの円盤状凸部をしたウェハ
RE台22aが形成されている。このウェハ!!置台2
2a上面は半導体ウェハ20との密着性を良好にするた
めになめらかな凸状を有している。下部電極22の材料
には導電性、熱伝導性に優れた金属材例えばアルミニウ
ム等が用いられている。
The lower electrode 22 has a diameter of about 200 IIll and a thickness of about 1011
It has the shape of a disk with a diameter of approximately 1 in the center of its upper surface.
251111, a wafer RE table 22a having a disk-shaped convex portion with a thickness of about 8 nm is formed. This wafer! ! Stand 2
The upper surface of 2a has a smooth convex shape to improve adhesion to the semiconductor wafer 20. As the material of the lower electrode 22, a metal material having excellent electrical conductivity and thermal conductivity, such as aluminum, is used.

このウェハ’mT1台22a上面にはウェハ載置台22
aとほぼ同径又はより大きく、厚さ約0.2nuaのカ
ーボンを含有した導電性シリコンラバー33が貼着され
ている。導電性シリコンラバー33とウェハ載置台22
aとの貼着手段として本例では硬化後も弾性を有する導
電性合成樹脂系の接着剤による熱圧着とした。
On the upper surface of this wafer'mT1 stand 22a is a wafer mounting stand 22.
A carbon-containing conductive silicone rubber 33 having approximately the same diameter as or larger than a and a thickness of about 0.2 nua is attached. Conductive silicone rubber 33 and wafer mounting table 22
In this example, thermocompression bonding with a conductive synthetic resin adhesive which remains elastic even after curing was used as a means of adhering the material.

導電性シリコンラバー33表面には格子状の浅m 33
 aが形成されており、さらに中央部にはつエバ押し上
げピン昇降用の孔33bが4ケ所に穿設されている。
The surface of the conductive silicone rubber 33 has a grid-like shallow m 33
a is formed, and four holes 33b for raising and lowering the evaporator push-up pin are bored in the central part.

このウェハ押し上げピン昇降用の孔33bは、下部電極
22を貫通して押し上げピン上下駆動機構であるエアシ
リンダ34に接続されているウェハ押し上げピン35の
昇降用のもので、エツチング処理の終了した半導体ウェ
ハ20を下面から押し上げピン35によりを押し上げて
導電性シリコンラバー33から離間させる構造としてい
る。
This wafer push-up pin lifting hole 33b is for lifting and lowering the wafer push-up pin 35, which passes through the lower electrode 22 and is connected to an air cylinder 34 serving as a push-up pin vertical drive mechanism. The structure is such that the wafer 20 is pushed up from the lower surface by push-up pins 35 and separated from the conductive silicon rubber 33.

下部電極22の半導体ウェハ20裏面に対向する位置に
は、エツチング処理中に半導体ウェハ20を冷却するた
めの環状の冷却水循環用配管36が埋設されており、エ
ツチング処理中にこの冷却水循環用配管36内に冷却水
導入装置37から低温例えば15°Cの冷却水が導入さ
れる。
An annular cooling water circulation pipe 36 for cooling the semiconductor wafer 20 during the etching process is buried in a position facing the back surface of the semiconductor wafer 20 of the lower electrode 22. Cooling water at a low temperature, for example, 15° C., is introduced from a cooling water introducing device 37 into the chamber.

このようなプラズマエツチング装置のウェハ固定動作に
ついて第3図を参照にしながら説明する。
The wafer fixing operation of such a plasma etching apparatus will be explained with reference to FIG.

まずウェハ押し上げピン35が上昇している状態(第3
図(C))で図示を省略したウェハ撮送装置により半導
体ウェハ20をウェハ押し上げピン35上に′a置した
後、ウェハ押し上げピン35を下降させる(第3図(a
))、この状態では、ウェハ載置台22a上面がゆるや
かな凸状をしているため周縁部に半導体ウェハとの間隙
が生じるが、クランプリング9が下降して半導体ウェハ
20周縁部をウェハaZ台22aに押圧することでこの
間隙はなくなる(第3図(b))。このとき従来のウェ
ハ固定機構では、半導体ウェハ固有の歪やウェハ載置台
22a表面の加工精度の問題、クランプ圧力によるウェ
ハ中心部への応力の発生等から半導体ウェハ20とウェ
ハ載置台22a間に少なからず間隙が生じ、この間隙に
より電気的結合性や熱伝導性が低下してエツチングの処
理むらや、処理効率の低下を招いてしまうが、本例では
弾性に優れた導電性シリコンラバー33をウェハ8W台
22a上に貼着しているため密着性が向上し、このよう
な間隙の発生がなくなり半導体ウェハ20とウェハiZ
台22a間の電気的結合や熱伝導性が非常に優れたもの
となっている。
First, the state in which the wafer push-up pin 35 is raised (the third
After the semiconductor wafer 20 is placed on the wafer push-up pin 35 using a wafer transfer device (not shown in FIG. 3C), the wafer push-up pin 35 is lowered (FIG. 3A).
)) In this state, since the upper surface of the wafer mounting table 22a has a gentle convex shape, a gap between the peripheral edge and the semiconductor wafer is created, but the clamp ring 9 descends and places the peripheral edge of the semiconductor wafer 20 on the wafer aZ table. By pressing on 22a, this gap disappears (FIG. 3(b)). At this time, in the conventional wafer fixing mechanism, there is a small amount of space between the semiconductor wafer 20 and the wafer mounting table 22a due to distortion inherent in the semiconductor wafer, processing accuracy problems on the surface of the wafer mounting table 22a, and stress generated in the center of the wafer due to clamping pressure. However, in this example, a conductive silicone rubber 33 with excellent elasticity is used as a wafer. Since it is pasted on the 8W stand 22a, the adhesion is improved and the generation of such a gap is eliminated, and the semiconductor wafer 20 and wafer iZ
The electrical connection and thermal conductivity between the stands 22a are extremely excellent.

さて、エツチング作業終了後はクランプリング9を上昇
させたあと、ウェハ押し上げピン35を上昇させ半導体
ウェハ20をウェハ載置台22aから押し上げる(第3
図(C))。通常エツチング処理は高温環境下で行なわ
れるため、半導体ウェハ20は高温例えば約100℃ま
で上昇し、半導体ウェハ20と導電性シコンラバー33
がW&着してしまい半導体ウェハ20の導電性シリコン
ラバー33からの離間が困難となる恐れがあるが、本例
では導電性シリコンラバー33表面に格子状の浅溝33
aを形成しているためこのような問題は発生しない、な
お、この浅溝33aは第3図(b)で示したように半導
体ウェハ20固定時には完全につぶされて隙間の発生が
生じない程度のものであることは無論である。
Now, after the etching work is finished, the clamp ring 9 is raised, and then the wafer push-up pin 35 is raised to push the semiconductor wafer 20 up from the wafer mounting table 22a (third
Figure (C)). Since the etching process is normally performed in a high temperature environment, the semiconductor wafer 20 is heated to a high temperature, for example, about 100°C, and the semiconductor wafer 20 and the conductive silicone rubber 33
However, in this example, a lattice-shaped shallow groove 33 is formed on the surface of the conductive silicon rubber 33.
However, as shown in FIG. 3(b), this shallow groove 33a is completely crushed when the semiconductor wafer 20 is fixed, so that no gap occurs. It goes without saying that it belongs to

上述実施例のプラズマエツチング装置を用いて実際に実
験をしたので以下に説明する。
An actual experiment was conducted using the plasma etching apparatus of the above embodiment, which will be explained below.

実験は、導電性シリコンラバーを使用していない装置、
本例のカーボン含有の導電性シリコンラバーを用いた装
置の2種類について行なった。また、実験に際しては装
置構造はもちろんのこと、使用電極の部材および形状、
反応気体の種類、電源出力値、真空度等のエツチング処
理条件は全て同一とした。供給電源としては、エツチン
グ対称物が酸化膜であったなめ、380k)tan;周
波電源を用いている。もちろんエツチング対称物により
最適な電源周波数は異なる。
The experiment was conducted using a device that did not use conductive silicone rubber.
Two types of devices using the carbon-containing conductive silicone rubber of this example were tested. In addition to the equipment structure, the materials and shapes of the electrodes used,
The etching conditions such as the type of reaction gas, power output value, degree of vacuum, etc. were all the same. As the object to be etched was an oxide film, a 380K tan frequency power supply was used as the power supply. Of course, the optimum power supply frequency differs depending on the object to be etched.

以下表1に示す実験条件のもとに実験を行ない表2に示
す結果を得た。
An experiment was conducted under the experimental conditions shown in Table 1 below, and the results shown in Table 2 were obtained.

(以下余白) 表1  実験条件 表2  実験結果 この実験結果から判明したことは、導電性シリコンラバ
ーを使用した場合には、これを使用しない場合に対し、 (1)エツチングレートが469人/分(2) Siエ
ンチレートが一154人/分(3) Si遷択比が6.
3 (4)半導体ウェハ上面温度が約−20°Cの向上がは
かれ、明らかに導電性シリコンラバーの効果が現れた。
(Leaving space below) Table 1 Experimental conditions Table 2 Experimental results The results of this experiment revealed that: (1) the etching rate was 469 people/min when conductive silicone rubber was used, compared to when it was not used; (2) Si entrainment rate is 1154 people/min (3) Si transition ratio is 6.
3 (4) The upper surface temperature of the semiconductor wafer was improved by about -20°C, clearly showing the effect of the conductive silicon rubber.

さらにエツチング作業中の半導体ウェハ上面部の温度分
布がほぼ均一になった。
Furthermore, the temperature distribution on the upper surface of the semiconductor wafer during etching became almost uniform.

上記実験結果から考えられることは、導電性シリコンラ
バーにより半導体ウェハと下部電極との密着性が大福に
向上した結果、(イ)半導体ウェハと下部電極間との電
気的結合が良好になって半導体ウェハと対向電極間の電
界の強さが均一となり処理効率が向上したこと、(ロ)
半導体ウェハと下部電極間の熱伝導性が良好になり、冷
却効果が向上したことである。またエツチング処理完了
後における半導体ウェハの等電性シリコンラバーからの
階間時に際し、半導体ウェハと導電性シリコンラバーと
の融着は認められず、導電性シリコンラバーを貼着して
いない装置と何らかわりなく容易に離間可能であった。
What can be considered from the above experimental results is that as a result of the conductive silicone rubber significantly improving the adhesion between the semiconductor wafer and the lower electrode, (a) the electrical bond between the semiconductor wafer and the lower electrode becomes better and the semiconductor (b) The strength of the electric field between the wafer and the counter electrode is uniform, improving processing efficiency.
Thermal conductivity between the semiconductor wafer and the lower electrode is improved, and the cooling effect is improved. Furthermore, when the semiconductor wafer was separated from the isoelectric silicon rubber after the etching process was completed, no fusion was observed between the semiconductor wafer and the conductive silicon rubber, and there was no difference between the device and the device to which the conductive silicon rubber was not attached. It was still possible to separate easily.

これは導電性シリコンラバー上に形成した浅溝が半導体
ウェハとの融着を防止したためである。
This is because the shallow grooves formed on the conductive silicon rubber prevented fusion with the semiconductor wafer.

ところで、本発明者はクランプリングの半導体ウェハに
対する押圧力についても着目し、クランプリングの押圧
力変化とエツチングレートの関係を求めるために実験を
行なったので以下に説明する。実験は前述実施例の装置
を用いて以下の表3に示す実験条件下で行なった。測定
はクランプ圧力を10k(If(クランプリング支持棒
1木当たり2.5kgf)、27kgf(同6.75k
gf) 、42kgf(同10.5kgf)、について
行い、結果を第4図に示す。
By the way, the present inventor also paid attention to the pressing force of the clamp ring against the semiconductor wafer, and conducted experiments to determine the relationship between the change in the pressing force of the clamp ring and the etching rate, which will be described below. The experiment was conducted under the experimental conditions shown in Table 3 below using the apparatus of the above-mentioned Example. Measurements were made at clamp pressures of 10k (If (2.5kgf per clamp ring support rod) and 27kgf (6.75kgf per clamp ring support rod).
gf), 42 kgf (10.5 kgf), and the results are shown in Figure 4.

(以下余白) 表3  実験条件 第4図において、X@におけるa、bおよびCは半導体
ウェハ周縁部の一点をaとし、半導体ウェハ中心部をす
、bを通りaと対向する側の半導体ウェハ周縁に設けた
点をCとし、これらa→b→C線上におけるエツチング
レートをY軸にとっている。
(Leaving space below) Table 3 Experimental conditions In Figure 4, a, b, and C in X@ represent a point a on the periphery of the semiconductor wafer, a point a on the semiconductor wafer periphery, and a semiconductor wafer on the side opposite to a passing through b. A point provided on the periphery is designated as C, and the etching rate on these lines a→b→C is taken as the Y axis.

実験結果から判明することは、(イ)クランプ圧が大き
くなる程エツチングレートが低下すること、(ロ)クラ
ンプ圧が27kgfと42k(lfのときに半導体ウェ
ハ中心部のエツチングレートの低下が顕著であること、
(ハ)クランプ圧が10kgfのときが最も均一なエツ
チングができることである。
The experimental results reveal that (a) the etching rate decreases as the clamp pressure increases, and (b) the etching rate at the center of the semiconductor wafer decreases significantly when the clamp pressure is 27 kgf and 42 k(lf). There is something
(c) The most uniform etching can be achieved when the clamp pressure is 10 kgf.

これら原因はクランプ圧が大きくなりすぎると、半導体
ウェハ20が上方へ向って弧状に反り、半導体ウェハ中
心部と導電性シリコンラバー間33に間隙が生じるため
である。従って、厚さが630μmの5インチウェハの
場合にはその周縁部を10kgfで押圧する方法が最も
効率的であることが判明しな。
This is because if the clamping pressure becomes too large, the semiconductor wafer 20 warps upward in an arc, creating a gap between the center of the semiconductor wafer and the conductive silicon rubber 33. Therefore, in the case of a 5-inch wafer with a thickness of 630 μm, it has been found that the most efficient method is to press the periphery with 10 kgf.

ところで本発明に使用する導電性合成樹脂膜は柔軟性に
優れているもの程密着性が良くなり好ましいが、ウェハ
固定時にクランブリング押圧部即ち導電性合成樹脂膜周
縁部に応力が加わり皺が発生し易くなり、この皺により
空隙が生じる可能性がある。
By the way, the more flexible the conductive synthetic resin film used in the present invention is, the better the adhesion will be, which is preferable, but when the wafer is fixed, stress is applied to the crumpling press area, that is, the periphery of the conductive synthetic resin film, causing wrinkles. These wrinkles may cause voids to form.

本発明の他の実施例として第5図に示すように、ウェハ
載置台22a上部に半導体ウェハ20よりも若干率さな
径で深さが導電性合成樹脂膜とほぼ同じ凹部40を形成
し、この凹部40に導電性合成樹脂膜41を装着するこ
とにより(第5図(a))、ウェハ固定時における導電
性合成樹脂膜41外周部に対する応力をウェハ載置台2
2aに吸収させて皺の発生を減少させることができる(
第5図(b))、尚、本発明に使用する導電性樹脂体と
しては、導電性テフロンや導電性シリコンゴムや導電性
弗素系ゴム等、弾性、熱伝導性、電気伝導性に優れたも
のであればいずれでもよい。
As another embodiment of the present invention, as shown in FIG. 5, a recess 40 is formed in the upper part of the wafer mounting table 22a, with a diameter slightly smaller than that of the semiconductor wafer 20 and a depth approximately equal to that of the conductive synthetic resin film. By attaching the conductive synthetic resin film 41 to this recess 40 (FIG. 5(a)), the stress on the outer circumferential portion of the conductive synthetic resin film 41 when the wafer is fixed is reduced to the wafer mounting table 2.
2a can reduce the appearance of wrinkles (
FIG. 5(b)), The conductive resin body used in the present invention is made of a material having excellent elasticity, thermal conductivity, and electrical conductivity, such as conductive Teflon, conductive silicone rubber, and conductive fluorine rubber. Any item is fine.

また、本発明はプラズマCVD、ECRエツチング、ス
パッタリング装置等、電極と被処理基板が当接し、プラ
ズマ雲囲気を設ける構造のものであれぽいずれにも適用
可能である。またプラズマの雰囲気は高周波放電に限ら
ずマイクロ波放電、直流放電によって形成してもよい。
Further, the present invention can be applied to any apparatus, such as plasma CVD, ECR etching, and sputtering apparatuses, which have a structure in which an electrode and a substrate to be processed are in contact with each other and a plasma cloud is provided. Further, the plasma atmosphere is not limited to high frequency discharge, and may be formed by microwave discharge or direct current discharge.

[発明の効果] 以上説明したように本発明のプラズマ処理装置によれば
、処理対象物と下部電極との密着性が向上するので、電
気的結合性や熱伝導性か向上し、均一性が良くしかも処
理効率の盲いプラズマ処理が可能となる。
[Effects of the Invention] As explained above, according to the plasma processing apparatus of the present invention, the adhesion between the object to be processed and the lower electrode is improved, so electrical coupling and thermal conductivity are improved, and uniformity is improved. It becomes possible to perform plasma processing with high efficiency and low processing efficiency.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明を適用した一実施例であるプラズマエ
ツチング装置のエツチング処理部を示す斜視図、第2図
は第1図の縦断面図、第3図はウェハ固定機構の動作を
示す断面図、第4図はクランプ圧とエツチングレートの
関係を示す図、第5図は他の実施例のウェハ固定aFf
Iを示す図、第6図はプラズマエツチング装置の概念的
な構成を示す断面図、第7図および第8図は従来のウェ
ハ固定機構を示す断面図、第9図は従来装置によりエツ
チング処理した半導体ウェハの表面の処理状態を示す図
である。 20・・・・・・半導体ウェハ、21・・・・・・エツ
チング処理部、22・・・・・・下部電極、22a・・
・・・・ウェハ載置台、23・・・・・・対向主峰、3
0・・・・・・クランプリング、31クランブリング支
持棒、32・・・・・・エアシリンダ、33・・・・・
・導電性シリコンラバー、33a・・・・・・浅溝、3
4・・・・・・エアシリンダ、35・・・・・・ウェハ
押し上げピン、40・・・・・・凹部、41・・・・・
・導電性合成樹脂膜。 出願人      東京エレクトロン株式会社代理人 
弁理士  須 山 佐 − 工 第2図 (C1 第3図 第4図 (a) 第5図 第8図 第9図
FIG. 1 is a perspective view showing an etching processing section of a plasma etching apparatus which is an embodiment of the present invention, FIG. 2 is a vertical cross-sectional view of FIG. 1, and FIG. 3 shows the operation of a wafer fixing mechanism. A sectional view, FIG. 4 is a diagram showing the relationship between clamp pressure and etching rate, and FIG. 5 is a wafer fixing aFf of another embodiment.
6 is a sectional view showing the conceptual configuration of a plasma etching device, FIGS. 7 and 8 are sectional views showing a conventional wafer fixing mechanism, and FIG. 9 is a sectional view showing a conventional wafer fixing mechanism. FIG. 3 is a diagram showing a processing state of the surface of a semiconductor wafer. 20... Semiconductor wafer, 21... Etching processing section, 22... Lower electrode, 22a...
... Wafer mounting table, 23 ... Opposing main peak, 3
0... Clamp ring, 31 Clamp ring support rod, 32... Air cylinder, 33...
・Conductive silicon rubber, 33a... Shallow groove, 3
4...Air cylinder, 35...Wafer push-up pin, 40...Concavity, 41...
・Conductive synthetic resin film. Applicant Tokyo Electron Co., Ltd. Agent
Patent Attorney Suyama Sa - Engineering Figure 2 (C1 Figure 3 Figure 4 (a) Figure 5 Figure 8 Figure 9

Claims (5)

【特許請求の範囲】[Claims] (1)プラズマ発生源を備えた気密容器内に電極を配置
し、この電極面に被処理基板を当接させてプラズマ処理
を行なうように構成されたプラズマ処理装置において、 前記電極の被処理基板との当接面に導電性樹脂体を設け
たことを特徴とするプラズマ処理装置。
(1) In a plasma processing apparatus configured to perform plasma processing by placing an electrode in an airtight container equipped with a plasma generation source and bringing the substrate to be processed into contact with the surface of the electrode, the substrate to be processed by the electrode; A plasma processing apparatus characterized in that a conductive resin body is provided on a contact surface with the plasma processing apparatus.
(2)プラズマ処理装置が、被処理基板を載置するエッ
チング電極と、前記エッチング電極上に設けられた導電
性合成樹脂膜と、前記エッチング電極と対向して配置さ
れた対向電極と、前記エッチング電極の上方にこれと平
行に配置された内径が被処理基板の外径よりもやや小さ
い基板押圧リング体と、前記基板押圧リング体を昇降さ
せて下降時に前記被処理基板周縁部を前記エッチング電
極に押圧するための基板押圧リング体昇降装置とを備え
たことを特徴とする特許請求の範囲第1項記載のプラズ
マ処理装置。
(2) The plasma processing apparatus includes an etching electrode on which a substrate to be processed is placed, a conductive synthetic resin film provided on the etching electrode, a counter electrode disposed facing the etching electrode, and the etching electrode. A substrate pressing ring body disposed above and parallel to the electrode, the inner diameter of which is slightly smaller than the outer diameter of the substrate to be processed; and the substrate pressing ring body is raised and lowered, and when lowered, the peripheral edge of the substrate to be processed is pressed against the etching electrode. 2. The plasma processing apparatus according to claim 1, further comprising a substrate pressing ring lifting device for pressing the substrate.
(3)導電性樹脂体の被処理基板との当接面に粗面が形
成されていることを特徴とする特許請求の範囲第1項記
載のプラズマ処理装置。
(3) The plasma processing apparatus according to claim 1, wherein a rough surface is formed on the surface of the conductive resin body that comes into contact with the substrate to be processed.
(4)導電性樹脂体が被処理基板と当接する電極の当接
面に導電性合成樹脂系接着剤により貼着されていること
を特徴とする特許請求の範囲第1項記載のプラズマ処理
装置。
(4) The plasma processing apparatus according to claim 1, wherein the conductive resin body is adhered to the contact surface of the electrode that comes into contact with the substrate to be processed using a conductive synthetic resin adhesive. .
(5)導電性樹脂体が導電性シリコンラバーであること
を特徴とする特許請求の範囲第1項記載のプラズマ処理
装置。
(5) The plasma processing apparatus according to claim 1, wherein the conductive resin body is a conductive silicone rubber.
JP61225492A 1986-09-24 1986-09-24 Plasma processing device Expired - Lifetime JPH0624187B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61225492A JPH0624187B2 (en) 1986-09-24 1986-09-24 Plasma processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61225492A JPH0624187B2 (en) 1986-09-24 1986-09-24 Plasma processing device

Publications (2)

Publication Number Publication Date
JPS6380535A true JPS6380535A (en) 1988-04-11
JPH0624187B2 JPH0624187B2 (en) 1994-03-30

Family

ID=16830166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61225492A Expired - Lifetime JPH0624187B2 (en) 1986-09-24 1986-09-24 Plasma processing device

Country Status (1)

Country Link
JP (1) JPH0624187B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4908095A (en) * 1988-05-02 1990-03-13 Tokyo Electron Limited Etching device, and etching method
US4931135A (en) * 1987-12-25 1990-06-05 Tokyo Electron Limited Etching method and etching apparatus
JPH02148837A (en) * 1988-05-23 1990-06-07 Lam Res Corp Device and method of clamping semiconductor wafer
JP2009164283A (en) * 2007-12-28 2009-07-23 Nikon Corp Substrate retaining device, exposure device, and method of manufacturing device
JP2010098296A (en) * 2008-09-17 2010-04-30 Hitachi Kokusai Electric Inc Substrate processing apparatus and method
JP2016129176A (en) * 2015-01-09 2016-07-14 東京エレクトロン株式会社 Cooling structure and parallel plate etching device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5687667A (en) * 1979-12-20 1981-07-16 Toshiba Corp Reactive ion etching method
JPS6054327U (en) * 1983-09-21 1985-04-16 株式会社日立製作所 semiconductor manufacturing equipment

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5687667A (en) * 1979-12-20 1981-07-16 Toshiba Corp Reactive ion etching method
JPS6054327U (en) * 1983-09-21 1985-04-16 株式会社日立製作所 semiconductor manufacturing equipment

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4931135A (en) * 1987-12-25 1990-06-05 Tokyo Electron Limited Etching method and etching apparatus
US4908095A (en) * 1988-05-02 1990-03-13 Tokyo Electron Limited Etching device, and etching method
JPH02148837A (en) * 1988-05-23 1990-06-07 Lam Res Corp Device and method of clamping semiconductor wafer
JP2009164283A (en) * 2007-12-28 2009-07-23 Nikon Corp Substrate retaining device, exposure device, and method of manufacturing device
JP2010098296A (en) * 2008-09-17 2010-04-30 Hitachi Kokusai Electric Inc Substrate processing apparatus and method
JP4703749B2 (en) * 2008-09-17 2011-06-15 株式会社日立国際電気 Substrate processing apparatus and substrate processing method
JP2016129176A (en) * 2015-01-09 2016-07-14 東京エレクトロン株式会社 Cooling structure and parallel plate etching device

Also Published As

Publication number Publication date
JPH0624187B2 (en) 1994-03-30

Similar Documents

Publication Publication Date Title
TWI415212B (en) Bevel etcher with vacuum chuck
KR100635845B1 (en) Electrostatic chuck and its manufacturing method
US6259592B1 (en) Apparatus for retaining a workpiece upon a workpiece support and method of manufacturing same
US20130093146A1 (en) Ceramic-metal bonded body
JPH08316215A (en) Gas heat transfer plasma treating device
US6572814B2 (en) Method of fabricating a semiconductor wafer support chuck apparatus having small diameter gas distribution ports for distributing a heat transfer gas
JP2001189378A (en) Wafer-chucking heating apparatus
JP2007067037A (en) Vacuum processing device
WO2020044843A1 (en) Electrostatic chuck device and method of manufacturing electrostatic chuck device
JPH10223621A (en) Vacuum treating apparatus
JP3311812B2 (en) Electrostatic chuck
JPS6380535A (en) Plasma processing apparatus
JPH0513558A (en) Wafer heating device and its manufacture
JP6982837B2 (en) Plasma processing method
JP4518712B2 (en) Tray-type multi-chamber substrate processing equipment
JPH0824117B2 (en) Plasma processing method
TWI633574B (en) Semiconductor processing device and method for processing substrate
JP3662909B2 (en) Wafer adsorption heating device and wafer adsorption device
JPH04300136A (en) Electrostatic chuck and its manufacture
JPH01227438A (en) Base plate for semiconductor substrate
JP3162886B2 (en) Processing equipment
JP2000216232A (en) Electrostatic chuck and manufacture thereof
JPS63131519A (en) Dry etching apparatus
JP2004006300A (en) Method and apparatus for plasma treatment, and tray for plasma treatment
WO2017148126A1 (en) Electrostatic chuck device