JPS6379414A - Voltage controlled type variable delay circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit constitution and to attain stable delay by providing a shift circuit having a shift register retarding a signal to be delayed for a prescribed time by the output of a ring oscillator whose oscillating frequency is changed by the a power voltage. CONSTITUTION:A common variable power voltage VDD is fed to each inverter of a ring oscillator 10 where plural inverters 11 are connected in a ring to change the oscillating frequency. A shift circuit provided with a waveform shaping buffer gate 20 and one-stage shift register 21 for delay is connected to the output side of the oscillator 10. The output of the oscillator 10 is subjected to waveform shaping by the buffer gate 20 and a clock signal phiis given to the clock terminal CK of the shift register 21. The shift register 21, based on the clock signal phi, retards the input signal VI by a shift number 1 to output an output signal VO. A reference voltage VDD is varied to change the oscillating frequency, thereby varying a delay time. Thus, stable delay is attained by the simple circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a voltage-controlled variable delay circuit used in places where a delay is provided to the F)I signal of a laser disc player or a video disc player. .

(Prior art) Conventionally, technologies in this field include television technology, (
1986-1> Denshi Gijutsu Publishing Co., Ltd., 'P, 75°76
It is rare to find one described in . The configuration will be explained below using figures.

FIG. 2 is a circuit diagram showing an example of the configuration of a conventional voltage-controlled variable delay circuit, and FIGS. 3 (1) and (2) are operational waveform diagrams of the circuit.

This delay circuit includes an input terminal 1 that receives an input signal VI;
and an output terminal 2 for sending out an output signal VO, and tens of thousands of C')IQs inverters 3-1 to 3-N are connected in series between the output terminals 1 and 2.

A control circuit (not shown) is connected to each of these inverters 3-1 to 3-H, and a common power supply voltage VDD is supplied from this control circuit to each of inverters 3-1 to 3-N.

In the above configuration, when the input signal VI is input to the input terminal 1, the input signal VI is transmitted to each inverter 3-1 to 3-3.
-N, the output signal vO is sequentially inverted and delayed by a predetermined time Td.
is output from output terminal 2. The time Td is the sum of the delay times of each inverter 3-1 to 3-H.

The delay time 1d is controlled by a common power supply voltage VCC supplied from a control circuit (not shown) to each inverter 3-1 to 3-N.
By changing , the time 1d can be changed.

(Problems to be Solved by the Invention) However, in the delay circuit with the above configuration, the inverter 3
-1 to 3-N are connected in series, so even if the change in the output waveform with respect to the input waveform per inverter stage is small, it will be multiplied by the total, and in the end, the output waveform with respect to the input waveform will change as a whole. There was a risk that the amount of change would become large.

Therefore, in order to correct such changes in the waveform, the dimensions of the transistors constituting the inverter in the intermediate stage are adjusted so that the characteristics of the inverter are opposite to those of the inverter in the previous stage, thereby changing the waveform. A method of canceling out the variation can be considered, but this method requires trial and error during design to eliminate the waveform variation, which has the drawback of requiring a great deal of time and effort during design.

The present invention provides a voltage-controlled variable delay circuit that solves the problems of the prior art, such as large changes in the output waveform and the need for time and effort during design.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a voltage-controlled variable delay circuit that includes at least a ring oscillator whose oscillation frequency changes depending on the power supply voltage, and a ring oscillator that is connected to the output of the ring oscillator. A shift circuit includes a shift register that shifts a delayed signal and delays the delayed signal by a predetermined period of time.

(Function) According to the present invention, since the delay circuit is configured as described above, the ring oscillator outputs an output signal with an oscillation frequency corresponding to the power supply voltage supplied to it, and the shift register shifts the output signal. It works so that the delayed signal has a predetermined delay time.

This makes it possible to generate a highly accurate delay time with a small change in the output waveform. Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a configuration block diagram of a voltage-controlled variable delay circuit showing a first embodiment of the present invention.

This delay circuit consists of a ring oscillator (circular oscillator) 10
and a shift circuit connected to its output side. The ring oscillator 10 has a configuration in which a plurality of (N) inverters 11 are connected in series in a ring shape, and a control circuit (not shown) is connected to each inverter 11.
A common power supply voltage V from this control circuit to each inverter 11
DD is supplied.

The shift circuit connected to the output side of the ring oscillator 10 includes a waveform shaping buffer 7 gate 20 . and a one-stage shift register 21 for delay. The shift register 21 has a clock terminal CK that inputs a clock signal φ, an input terminal IN that inputs an input signal VI that is a delayed signal, and an output terminal OUT that outputs an output signal vO.
The clock terminal CK is connected to the output side of the ring oscillator 10 via the buffer gate 20.

Next, the operation shown in FIG. 1 will be explained with reference to FIGS. 4 and 5. Note that FIG. 4 is a power supply voltage dependence characteristic diagram of the oscillation frequency in the ring oscillator 10, and FIG. 5 is a time chart for explaining the operation of FIG. 1.

As shown in FIG. 4, the ring oscillator 10 exhibits a linear characteristic in its oscillation frequency with respect to a power supply voltage VDD supplied from a control circuit (not shown), and provides its output to the buffer gate 20. The buffer gate 20 shapes the waveform of the output of the ring oscillator 10 and provides a lock signal φ to the shift register 21 as shown in FIG. Then, the shift register 21 receives an input signal @v■ based on the clock signal φ.
is delayed by one shift stage and its output signal @VO is sent from the output terminal OUT. Here, the delay time can be changed by changing the power supply voltage VDD supplied to the ring oscillator 10 or by changing the number of stages of the shift register 21.

In this way, in this embodiment, the shift register 21 is operated using the ring oscillator 1° as the source, so the number of inverters 11 that make up the ring oscillator 10 can be reduced, and the delay circuit can be easily configured with a small number of elements. In addition, since the shift register 21 is used, there is an advantage that the delay operation is stable.

FIG. 6 is a configuration diagram of a voltage-controlled variable delay circuit showing a second embodiment of the present invention.

This delay circuit includes a ring oscillator 30 and a three-channel shift circuit connected to its output side. The ring oscillator 30 has a configuration in which N inverters 31 are connected in series in a ring shape, as in the conventional case.

The shift circuit includes buffer gates 40-1 for waveform shaping.
40-2.40-3, set/reset type flip-flop for each channel period (hereinafter referred to as R3-FF)
41-1.41-2.41-3, one-stage shift register for delay 4.2-1.42-2.42-3, AND gate for sampling (hereinafter referred to as AN[)> 43-
1.43-2.43-3, and OR Gate (hereinafter referred to as OR
) 44.

Buffer gates 40-1 to 40-3 are respectively connected to three output terminals of ring oscillator 30, and waveform-shape each output of ring oscillator 30 to generate clock signal φ1.
．． φ2. This is a circuit that outputs φ3 respectively. R3-F
F41-1 to 41-3 are clock signals φ1 to φ1, respectively.
Sera 1 to input φ3 to terminal 4l-Is to 41-33
, clock signal φ2. φ3. Reset terminals 4l-IR to 4l-3R to which φ1 is input, and clock signals φ10 to
It has output terminals 41-10 to 41-30 that output φ30, and each reset terminal 4l-IR, 4l-2R and 4l-3R are connected to each buffer gate 40-2, 40-3, and 40-1, respectively. The shift registers 42-1 to 42-3 have an input terminal IN that receives an input signal VI, and a clock signal φ10 to φ.
30 to the clock terminal C that inputs it, and the output signal 01 to
Each terminal has 00 output terminals that output 03, and each tarok terminal CK connects to each R3-FF output terminal 41-10 to 41.
-30 and the input sides of each AND43-1 to 43-3, and each output terminal OUT is connected to the input side of each AN[)43-1 to 43-3, respectively. Each AN043-1 to 43
-3 is the clock signal φ10~φ30 and the output signal 01~
03 and their respective output signals @01
This is a circuit that gives 0 to 030 to 0R44.

0R44 takes the logical sum of each output signal 010 to 030,
This is a circuit that sends out the output signal vO.

Next, the operation shown in FIG. 5 will be explained with reference to FIG. Incidentally, FIG. 7 is a time chart for explaining the operation of FIG. 6.

The three outputs of the ring oscillator 30 are connected to each buffer gate 40.
-1 to 40-3, and the output clock signals φ1 to φ3 are applied to the set terminals 4l-Is to 41-33 and the reset terminal 4 of each R3-FF41-1 to 41-3.
1-IR to 41-3R. Then, R3-F
F41-1 is set by clock signal φ1 and rises;
It is reset by the clock signal φ2 and falls. Similarly, other R3/FFs 41-2 and 41-3 are set and reset to output lock signals φ10 to φ30 as shown in FIG.

In this way, each output clock signal φ10 to φ is synchronized between channels by R3-FF41-1 to 41-3.
30 is each shift register 42-1 to 42-3 and AN
D43-1 to 43-3 are given.

The shift register 42-1 shifts the input signal VI, which is a delayed signal, by one stage using the clock signal φ10, and provides the output signal @01 to the AND 43-1. Similarly, the shift registers 42-2, 42-3 also use the input signal Vl as the clock signal φ20. Shift by one stage with φ30 and output signal 02
03 is given to AND43-2 and 43-3, respectively. AND43-1 converts output signal 01 into clock signal φ10
The output signal 010 is sampled at 0R44. Similarly, the other ANDs 43-2 and 43-3 convert the output signal 02.03 into the clock signal φ20. It samples at φ30 and gives its output signals 020 and 030 to 0R44. This causes 0R44 to output signals 010 to 030.
The logical OR is taken and the output signal vO is sent out. This output signal vO has a waveform obtained by delaying the input signal VI by a predetermined time. The delay time can be controlled by changing the power supply voltage VDD supplied to the ring oscillator 30, or by changing the power supply voltage VDD supplied to each shift register 42-1 to 42-3, as in the first embodiment.
By changing the number of stages, the delay time can be changed.

In this embodiment, a three-channel shift register 42-
1 to 42-3, etc., and by taking the logical sum of their outputs, the delay can be applied as a whole at a frequency that is multiple times the number of channels in the shift frequency of each channel.
Even with slow elements, delay times sampled at high frequencies can be obtained. This makes it possible to increase the accuracy of the delay time.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, ring oscillator 10.30 may be configured with elements other than inverter 11.31, gate circuits 43-1 to 43-3.44 in FIG. 6 may be configured with other gate circuits, or gate circuits 43-1 to 43-3.44 in FIG. The circuit shown in FIG. 6 may be configured with four or more channels.

(Effects of the Invention) As described above in detail, according to the present invention, a shift register is used to shift the delayed signal by the output of the ring oscillator and delay the signal for a predetermined time. The circuit configuration can be simplified by reducing the number of constituent elements.

Furthermore, since a shift register is used, changes in the output waveform are small and a stable delay time can be obtained, which can be expected to facilitate design.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of a voltage-controlled variable delay circuit showing a first embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional voltage-controlled variable delay circuit, and FIG. 3 (1). (2) is the operating waveform diagram in Figure 2, Figure 4 is the oscillation frequency characteristic diagram in Figure 1, Figure 5 is the time chart in Figure 1, and Figure 6 is the time chart in Figure 1.
The figure is a block diagram of a voltage-controlled variable delay circuit showing a second embodiment of the present invention, and FIG. 7 is a time chart of FIG. 6. 10, 30...Ring oscillator, 21.42
-1 to 42-3...Shift register, 44...
...OR, VI... Input signal, vO...
...output signal.

Claims (1)

[Claims] 1. A shift circuit including a ring oscillator whose oscillation frequency changes depending on the power supply voltage, and a shift register that shifts a delayed signal using the output of the ring oscillator and delays the delayed signal for a predetermined period of time. A voltage-controlled variable delay circuit characterized by: 2. The shift circuit includes a plurality of shift registers that separately shift the delayed signal using a plurality of outputs of the ring oscillator, and a gate circuit that takes logic of the outputs of these shift registers. The voltage-controlled variable delay circuit according to item 1.