JPS6378399A - Digital communication system - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] (Technical field to which the invention belongs) The present invention relates to signal storage and playback systems.

BACKGROUND OF THE INVENTION In normal real-time signals such as audio or images, there are typically 20 to 10-plus periods of time in which there is no signal. Such signals can be converted to digital signals for digital transmission and reproduction. For such a system, the signal is modulated using a Hals code,
It can be processed by differential pulse code modulation, delta modulation, or adaptive predictive difference code modulation. In Kobashira et al.'s modulation method, an analog signal is sampled at different intervals and quantized into many levels.

If the signal has a fixed pattern, such as in a music box or recording, this signal can be stored in memory and played back when commanded. In such applications, it is desirable to leave some memory capacity for economical reasons.

Means for Solving the Problem The object of the invention is to provide a means for excluding the storage of null signals in recorded communication systems.

Another object of the invention is to save memory capacity of communication systems for storage of recorded signals such as audio.

Yet another object of the invention is to achieve the above object using simple decoding and storage circuitry.

A final object of the invention is the construction of a simple and economical integrated circuit for digital communications.

The above object is achieved in the present invention by pulse code modulation. During signal periods with no signal, no content is stored in the memory and the decoder for the memory is deactivated. By eliminating the storage of null signals, memory size is reduced. By partially decoding the timing code, the decoder circuit is simplified.

Embodiments In digital communication systems, analog signals such as audio or images are sampled at small time intervals. At each sampling interval, the amplitude of the signal is quantized into a small number of squares. These quantized levels are then converted to digital signals by analog-to-digital conversion techniques well known in the art.

In this conversion, successive audio samples are converted into digitally coded signals having values corresponding to the amplitudes of the audio samples. The digital signal from the A/D converter is converted into a valid coded signal by an encoder. This encoding method is ・ξ
A pulse code modulation method, a difference pulse code modulation method, a delta modulation method, or an expected difference code modulation method may be used. Such modulation methods are known.

In real-time signals, the waveform typically includes a proportion of null signal periods in which the waveform does not change amplitude. For example, the waveform for the word "6" is shown in FIG. 1(a). In the figure, the vertical axis represents the amplitude of the signal, and the horizontal axis represents time. During periods 101 and 103 the amplitude changes with time. There is no change in amplitude during period 102, and this period is known as the null signal period. In a given audio signal, the null periods typically occupy 20 to 40 fractions of the time.

After the analog signal is encoded into a digital signal, such as a binary pulse, the digital information is stored in memory. When this signal is played back, the information stored in memory is decoded and converted back into an analog signal. Such decoding and playback methods are known in the art. Literature “Waveform Quantization and Coding Method J (N, S
, edited by Jayant, published by EEE Press).

The signal of FIG. 1(a) is divided into time intervals of N in FIG. 1(b), TI +T2 . +TL l +TL +TL+
1 + +TL+S IT,, +S+Il・TN-11
It is divided into TN. From time interval T1 to TI, the signal changes with time.

During the time interval TL+1 to T, . . . +S, there is no signal. Interval T 1. From +S+1 to TN the signal changes again with time.

A feature of the invention is that signals in null periods are not stored in memory. Only the time-varying portion of this signal is stored in memory. The waveform of the expanded signal is shown in FIG. 2(a). The signal is at N sampling points, SPl.

SF3. sp3. , , SPH. Each sampling point is divided into 2 bits of the process by time division of 2 to 1 power.
It is a hexadecimal code. The amplitude of each sampling point can also be represented by the binary cobi of J bits with square to cube time division. In Figure 2(b),
■=4. Chill with J=4. A number of M sampling points forms one section. If the amplitude of any section falls to a certain value, the signal is considered to be a null signal. When two digitized signals are stored in memory, each code group has a particular set of abiles. However, when a null signal is encountered, the timing aviles code continues to count, but the amplitude data of the encoded null signal is not stored in memory.

The basic configuration for implementing this method is shown in FIG. The memory is configured to include an X-axis decoder 43, a Y-axis decoder 42, and a memory matrix 11. In memory matrix 41, each small square represents one bit of stored data. Each line is a binary code of one code group, e.g. B1+B2+ B11 I I BM-1+ BM
remember. The decoder produces an output to select a particular bit in memory. The sequence of times in the selection is the one whose result appears at the output of the decoder.
address code.

This memory configuration is used in a system such as that shown in FIG. In this, an address code generator 44 is used to generate the inputs to the x-axis and y-axis decoders. The data code output of the memory matrix is sent to a D/A converter 45 to reproduce the original signal.

Consider again the signal shown in Figure 2(a), where the horizontal axis represents time and the vertical axis represents amplitude.The signal is sampled into many time intervals, and the amplitude is shown in Figure 2(b). Quantized to discrete levels as shown.

The time interval is address code, x3x2Xlx.

It can be expressed by For example, CO)PA000
0 represents the first time interval and 0001 represents the second interval around the binary count. The amplitude is represented by the binary data code 1-' 0111 for the maximum amplitude and 1000 for the minimum amplitude. In this waveform, the timing address code 1-'0111
The amplitude between and 1100 is constant and represents a null signal period. The coded time-varying amplitudes between coding time intervals 0111 and 0111 are then stored in memory.
A zero signal period of 00 comes. According to the invention, coded amplitude data for this period is not stored in memory.

After a null signal period, the amplitude between the coded timing abyss codes 1100 and 1111 changes with time again.

The front panel includes timing address code and amplitude data.
Shows the relationship between the code. In the tree table, B1 is the least significant bit for the amplitude data code and B4 is the base most significant bit. If the data code 9 is represented bit by bit as a function of the timing address code, then this relationship is expressed in four matrices, one for each bit, as shown in Figure 5. It can be expressed as For each machine) In IJ Lux, the row is the result of the address code of X3X2, and the column is the result of the address code x
Represents the result of the lxo address code. Therefore, the first, second, and lth rows from the top represent signal periods that change over time 7, and the third row represents a null signal period.

According to the invention, data codes in null signal periods are not stored in memory resources. this is,
This is accomplished by excluding the decoder output results for address codes that represent no signal periods, and by providing only partial results during time-varying signal periods. Third
In the case of the waveform shown in the figure, the decoder has a sampling interval T1
Give the resulting output from to TL, and set the sampling interval T
The result is not output from L to 'rL+s, and the result is output again from sampling interval TL+S+1 to TN.

These results are arranged to energize the X-axis selection line and the Y-axis selection line for two-dimensional addressing operation of the memory cell. , The matrix shown in FIG. 5 is as shown in FIG.
3, x-axis decoder 24 translated for the integrated circuits shown in FIG. 6(b), FIG. 6(c), and FIG. G(d).
3° Y-axis decoder 2. t2 and the storage device 241 have the configuration shown in FIG. 3? j I': I am doing it. However, instead of one-dimensional O addressing from the X-axis decoder only as suggested in FIG. 3, the time sequence as represented by
7 KoF' 243 Oyo□ Y 3'f5te= -y
' 2.12 Obtained by empty two-dimensional addressing.

These circuits Vl, a large number of metal oxide film halves, are composed of body field effect transistors (MOSFETs). This M.O.
Some of the 8F'ETs are of the enhancement mode type and others are of the depletion mode type. The x-axis decoder 243 is a selector type logic circuit. This circuit is used as a pass-type transistor and has a number of enhancement modes connected in series with a number of depletion layer modes.
' ET. Pass type transistor tray/
and North become conductive when a voltage of binary FrJ level is applied to the gate.

A depletion layer mode MOSFET is always in a conductive state.

There are as many enhanced non-tomote MOSFETs in each row as there are Aviles codes in the XIII decoder. For example, if the result x3x2 is selected, the enhancement mode for the first row of the X-axis decoder is set to 103F'.
ET is turned on. The engine motor in series with this force and others is the load element R13.
is connected to form a NAND gate (for positive logic systems). This load element is another MOSFET,
This can be switched on when the clock .xi.cis01 is applied to the gate.

The same X-axis decoder is used for all matrices.

The same X-axis decoder can be shared by more than one matrix.

Similarly, 1Y-axis decoder 242 is another selector type logic circuit. Each column is the result,X,X,,,XOX,.

It becomes conductive according to XoXl and XoXl.

These circuits become the Y-axis selection lines for the memory cells.

In storage devices, there are also arrays of MOSFETs. These MOSFETs are arranged in a matrix according to the matrix shown in FIG. 5, and are located at the intersections of the X-axis selection line and the Y-axis selection line. Each X-axis select line energizes the gates of those MO8F'ETs at the intersection in one row. The MOSFETs in one column are connected in series as pass type transistors to the Y-axis selection line. At any intersection point, Bl, B2 . B3
6(a) and 6() corresponding to the matrix for
b) The logical value “
0' can be represented by a depletion mode 'MOSFET, and the logical value r ] J can be represented by an acknowledgment mode MO8F'ET (C, or alternatively, a matrix for B4 in Figure 5) IJ Lux Correspondence As shown in FIG. 6(d), the m logical value roJ at a certain intersection is the enhancement mode MOS
It can be represented by a FET, and a logic value "1" can be represented by a depletion mode MOSFET.

In the case of a row corresponding to a certain null signal period, there is no selection line for that result (e.g. x3 in this example
x2). Therefore, this line is skipped and
8F'ET is not used. Therefore, memory capacity is saved. Is it possible to store one row of memory 7 tricks? The pass type transistors are connected in series (C-connected) with the pass type transistors in the Y-axis decoder and load elements such as R1, R2, R3 or R4 to form a NAND logic gate. The output of the gate is timing address low 1-”
and the corresponding data code.This logic game
The output of the data code B4. B3. B2. Bl
can be provided flowing to two buffers such as I14 and I24 to obtain I24. IIJ type buffer is 2
This inverter consists of two inverters, which inverts an input such as B3 in FIG. 6(C) twice and outputs B3, which is the same as input S3.
This results in a logical level of The 24-type buffer consists of one innominator, which outputs the sixth (,1) as output B4.
The input logic level, such as B4 in FIG. 1, is inverted. For example, address row 1-'0001 is selected and B+=0°B2=
O, B3=1, B4=1 Te & ff lever 7 Ra fx
stomach. X3=Q, X2=Q, X1=Q, x (If 1=1, the first row and second column of the memory matrix are selected.

When a row is selected, all gates in this row in the memory matrix are low. M.O.S.
When the gate of a FET goes low, the corresponding enhancement mode MOSFET is turned off, but the depletion mode MOSFET is not turned off. In Fig. 6, the intersection point in Fig. 6(d) The depletion layer mode MOSFET, P4, in the matrix of B4 is not turned off.The rest of the unselected lines are at logic "1" level, so the MOSFETs in all these rows
is on.

Since B4 is on, the buffered output B4 is “1
”, the output of the NAND gate becomes “0”. On the other hand, B3 in the B3 matrix of FIG. 6(c) is turned off and output B3 is also on the "1" rail. In the remainder of the circuit, the MOSFET at the corresponding intersection (ie, row 1, column 2) is of the depletion mode type, which cannot be turned off when selected. Therefore, the output B2 in FIGS. 6(a) and 6(b)
And B1 becomes low at the "0" level.

Note that the third row of the matrix in FIG. 5, which represents a null signal, is not included in the memory matrix of FIG. Therefore, one row of MOSFETs is eliminated, thereby saving chip area in the integrated circuit.

The memory matrix is essentially a read-only memory. As in conventional ROM, the MO3F"ET of this matrix uses custom masking methods known in the semiconductor industry, electrically programmable RO
It can be programmed by different techniques, such as those used for M, non-volatile memories, etc.

[Brief explanation of the drawing]

Figure 1(a) is a graph showing a typical audio waveform;
b) The figure is a graph showing the time-varying period of the waveform and the signal period of no signal,
FIG. 2(a) is a graph showing an extended waveform with a time-varying period and no signal period, and FIG. 2(b) is a graph showing the amplitude data code and timing address of the signal shown in FIG. 2(a). Figure 3 is a diagram showing the memory structure for storing the pulse code modulated signal; Figure 4 is a block diagram showing the system for storing and reproducing the signal; Figure 5 is the amplitude data code for the different bits. A two-dimensional Mad IJ diagram showing the relationship between 8 and the timing-at9 address code, and Figure 6 shows (a) the least significant bit, (b) the second bit, and (c) the The third bit, (d) is the circuit diagram of the memory according to the present invention for the most significant bit. 41...Memory matrix 42...Y-axis decoder 43...XII+decoder 44...Address code generator 45...
・D) Tal/Analog Fist Converter □- ＼1 Agent Patent Attorney Kyo Yu Asa 3, 2” Arc Code Xs X2 Xi XOB4 B3 B2 Bt
Figure 2 Width (a) Time ^ coat - Figure 3 81 Snake 2X1xOX1
XO 3 x 2 B 3 3 x 2 B 4 X 1 l Patent Application No. 218489 of 19862, Title of the invention: Digital communication system 3, Relationship with the case of the person making the amendment Applicant Address Name: Industrial Technology Research Institute 4, Agent address: Ote, Chiyoda-ku, Tokyo 2-2-1 Shin-Otemachi Building, Room 206, 5, Date of amendment order: November 25, 1985 (Date of dispatch) 6, Subject of amendment (1) Application form stating the name of the applicant's representative (2) ) Power of attorney, corporate certificate (3) Typed details 4) Drawings

Claims (1)

[Claims] 1. A digital communication system for storing and reproducing a fixed pattern of signals having a signal period of zero, comprising: a device for quantizing and sampling the signal; a device for encoding the level into a quantum level, said level being represented by a data code, and a device for storing said level in different cells, except for said null signal period, in sequential correspondence with said signal. A device for addressing the cell, a device for excluding addressing of the memory during the null signal period, and a device for regenerating the first signal including the null signal period. Digital communication system. 2. A digital communication system for encoding a fixed pattern signal as claimed in claim 1, wherein said signal is an audio signal. 3. said device for addressing said cell includes an X-axis decoder and a Y-axis decoder, said X-axis decoder and Y-axis decoder connecting an
the device having an output for energizing an axis selection line to exclude addressing of the memory during the null signal cycle;
3. The digital communication system of claim 2, further comprising a device for partially decoding said decoder. 4. Each of the decoders includes a large number of selector type logic circuits, and each of the selector type logic circuits includes a large number of depletion layer mode MOSFs.
ET and an enhancement mode MOSFET, each MOSFET having a drain, a source, and a gate, and the enhancement mode MOSFET conducts between the drain and the source when turned on by the respective gate voltage. the selector-type logic circuit operates as a pass-type transistor connected in series with one load element; Mode MOSFET
4. The digital communication system according to claim 3, wherein the digital communication system is selected by switching on. 5. said partially decoding device
5. A digital communication system as claimed in claim 4, characterized in that it has a partial result of an address code, said result appearing at the output of said decoder to energize said selection line. 6. The memory includes a plurality of enhancement cells as the memory cells each representing two binary logic levels at the intersection of the X-axis selection line and the Y-axis selection line.
mode MOSFET and a depletion mode MOSFET, wherein the enhancement mode MOSFET is preprogrammed according to the data code of the signal, and the MOSFET in the memory is configured to select the Y-axis as a second logic gate. forming a pass transistor connected in series with one of the lines, the MOSFET in the memory having a gate connected to and controlled by the X-axis selection line. A digital communication system according to scope 3. 7. A digital communication system according to claim 6, characterized in that there are J output bits forming the 2 to J power of the quantization level. 8. Each output bit is an output of the second logic gate having the same logic level as the memory cell selected by the two-dimensional addressing device. The digital communication system according to item 7. 9. The memory has a plurality of enhancement modes M as the memory cells each represent two binary logic levels at the intersection of an X-axis selection line and a Y-axis selection line.
consisting of an OSFET and a depletion mode MOSFET, the MOSFET in the memory is preprogrammed to set each mode according to the content of the signal, the X-axis selection line controls the gate of the MOSFET at the intersection, the MOSFET at the intersection point is connected in series with the Y-axis select line as a pass transistor to form a second logic gate, the second logic gate being one of the coded signals;
6. Digital communication system according to claim 5, characterized in that it has an output forming bits. 10. Digital communication according to claim 8, characterized in that each said X-axis decoder controls the gate of a pass type transistor of said Y-axis selection line at said intersection point for said one or more bits. system.