JPS6378213A - Cpu resetting system - Google Patents

Abstract

PURPOSE:To scale down a device and to reduce its cost by providing a trapezoidal wave generator circuit, a DC power source circuit and two AND circuits so as to constitute a resetting control circuit. CONSTITUTION:The trapezoidal wave generator circuit 4 generates a trapezoidal wave if an AC signal dropping a commercial power source exceeds a prescribed voltage. The DC power source circuit 5 generates a DC voltage signal if a power source voltage is impressed to a CPU1. A resistance R1 and a capacitor C2 delay the output signal of the circuit 5. When the output signal CH1 of the delay circuit is at a level H and the output trapezoidal wave ANin of the circuit 4 is at a level H, the output of a NAND gate NAND1 comes to a level L. Accordingly, the output of a NAND gate NAND2 becomes a level H, and the reset CPU1 is released. When the CPU1 starts executing, an output CPUOUT is made at a level H. Then the output of an inverter I comes to a level L, which leads the output of the NAND2 at a level H. Consequently, the resetting release state is maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field This invention is applicable to
The present invention relates to a CPU reset system that performs reset control.

The CPU reset system according to the present invention includes a reset control circuit that generates and releases a reset signal for a CPU that executes a predetermined program after the reset is released, and immediately after the power is turned on and off. By resetting the CPU in situations where the power supply is unstable, such as
Control to prevent U from malfunctioning.

In particular, the present invention is intended to release the reset state only when the CPU is in an operable state, thereby reliably preventing malfunction of the CPU.

(C) Conventional technology A system using a CI (I) U consisting of a microprocessor, etc. is equipped with a reset control circuit that generates a reset signal to the cPU when the power is turned on, and releases the reset after the power supply voltage has stabilized. It is being Conventionally, such a reset control circuit has been designed to handle power supply voltage fluctuations and C
A circuit was provided to check the voltage range in which the PU operated stably, and the entire circuit was extremely complex. Of course, if the circuit only generates a reset signal to the CPU for a certain period of time when the power is turned on, the reset control circuit can be configured with a simple CL time constant circuit, but it will not be affected by external noise or chattering of the power switch. It was also necessary to perform a stable reset operation for such situations.

(d) Problems to be Solved by the Invention However, since such conventional reset control circuits are configured using a large number of electronic components, the circuit board occupies a relatively high proportion, and small electronic components are used. It was difficult to use it in equipment. It was also one of the causes that hindered cost reduction of the entire device. This invention solves these conventional problems and provides a CPU that configures the circuit with fewer electronic components, making it possible to downsize the device and reduce costs.
The purpose is to provide a reset system.

(e) Means for Solving Problems This invention includes means for generating a reset signal when the power is turned on, to the CPU that executes a predetermined program after the reset is canceled, and after the power is stabilized, the reset is canceled. In a CPU reset system comprising a reset control<1td circuit, the reset control circuit includes a trapezoidal wave generation circuit that full-wave rectifies a commercial power supply or an AC signal obtained by stepping down the commercial power supply, clamps it to a constant voltage, and generates a trapezoidal wave. , a DC power supply circuit that generates a DC voltage signal from a commercial power supply, the output signal of this DC power supply circuit, and the output signal of the trapezoidal wave generation circuit, and when the result is logic 1, the CP
The present invention is characterized in that it is provided with an AND circuit for canceling the reset of tJ, and also provided with means for maintaining the cent cancellation state after the CPU is canceled or generating a cent cancellation signal.

(f) With the above-described configuration, the trapezoidal wave generating circuit generates a signal when the commercial power supply or the AC signal obtained by stepping down the commercial power supply exceeds a predetermined voltage.
Generates a trapezoidal wave. The DC power supply circuit generates a DC voltage signal when a power supply voltage is applied to the CPU. Furthermore, the AND circuit generates DC voltage from the DC power supply,
And a logic 1 is generated under the condition that a trapezoidal wave is generated. This AND circuit generates a logic I signal, so that cp
Cancel the reset of U. As a result, the CPU starts operating and generates a reset release signal that maintains the reset release state. As a result, the CPU performs processing according to a predetermined program until the power is turned off.

[g) Embodiment FIG. 1 is a circuit diagram of a CP reset system according to an embodiment of the present invention, and FIG. 2 is a diagram showing waveforms of each part thereof.

In FIG. 1, reference numeral 4 represents a trapezoidal wave generating circuit. The trapezoidal wave generation circuit 4 includes a power transformer T that steps down the commercial power source <AClooV), a diode bridge DB that includes diodes D1 to D4 that full-wave rectifies the output of the transformer T, and a diode bridge DB that converts the full-wave rectified waveform into a constant voltage. The resistance to be clamped to 4. It consists of a Zener diode ZD and a resistor SE5 that pulls down the output potential of this circuit to the "L" level when a trapezoidal wave is not generated.

The waveform FW shown in FIG. 2 represents the output waveform of the full-wave rectifier circuit, and the waveform ANin represents the output circuit of the trapezoidal wave generating circuit, which is supplied to the CPU described later.

In FIG. 1, reference numeral 5 represents a DC power supply circuit, which is comprised of a regulator circuit 3 for stabilizing the output voltage of the full-wave rectifier circuit and a smoothing capacitor CI. The waveform Vcc shown in FIG. 2 represents the waveform of the output voltage of this DC power supply circuit. As shown in the figure, timing t. After the power is turned on at , the power supply voltage is stabilized at the timing tl after a certain period of time delay due to delay elements such as smoothing capacitors. This power supply voltage will be used as a power supply for the entire system 2 including the CPU, which will be described later.

In FIG. 1, the resistor i1 and the content C2 constitute a C order time constant circuit, which delays the output signal of the DC power supply circuit 5.

Note that diode D is connected to capacitor C and NAND as described later.
Provided to pull down the input terminal of the gate.

The waveform CHI shown in FIG. 2 represents the output signal of this delay circuit, and reaches the "H" level at timing t2, which is further delayed from the rising edge tl of the DC power supply Vcc.

The NAND gate NAND 1 receives the output signal CHI of the delay circuit and the ANin output from the trapezoidal wave generating circuit.
This is a gate that performs a logical product with. NAND2 is NAND
This gate calculates the AND of the signal output from I and the output signal of inverter I, and the output signal of this gate is C
The signal is given as the RESE 'r times the PUI. As shown in Figure 2, the output signal CHI of the delay circuit is "■1"
level and when the trapezoidal wave ANin is at “l(” level,
The output of NAND 1 becomes "L" level (t2). Therefore, the output of NAND2 becomes "H" level, and CP
U1 enters the reset release state.

When the CPUI enters the reset release state, it starts executing according to a predetermined program. When the CPUI starts execution, first, the CPU0UT is set to the "H" level. When CPU0UT becomes H" level, the output of inverter I becomes L" level as shown in Figure 1, and the NAN
The output of D2 becomes "H" level. Therefore, game) NA
The reset release state is maintained regardless of the output signal of NDI. Note that the resistor R3 represents a pull-down resistor for the input of the inverter I.

When the power switch is turned off or there is a power outage, the trapezoidal wave ANin is not generated from timing t4 as shown in Figure 2, and after a certain period of time at t, CPU0UT goes to the "L" level, and this Accordingly, RE S E T'
It becomes L'' level. Thereafter, the power supply voltage Vcc falls (t6).

FIG. 3 is a flowchart showing the processing procedure of the CPUI. When the operation starts as described above, the signal CPU0UT
is set to "■]" level (nl).

Specifically, set the corresponding bit of the output port.

After that, predetermined processing is performed (n3).

While performing such processing, the trapezoidal wave AN i in is monitored. In other words, if the signal ANin is at the "L" level, the signal ANin is turned off again after a certain period of time has elapsed.
(n2-n4-n5). Signal ANin
If remains at “L” level for a certain period of time, CPU0UT
is set to "L" level (n6). By this, C.P.
U resets itself and stops operating.

(h1 Effects of the Invention As described above, according to the present invention, the circuit for canceling the reset of the CPU when the power supply voltage becomes stable can be configured with a small number of circuits, thereby making it possible to reduce the board area and cost.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a CPU reset system according to an embodiment of the present invention, FIG. 2 is a diagram showing waveforms of each part thereof, and FIG. 3 is a flowchart showing a processing procedure of the CPU of the CPU reset system. 1-CPU. 4 - Trapezoidal wave generation circuit, 5 - DC power supply circuit, NANDl - AND circuit.

Claims (1)

[Claims] (1) CP that executes a predetermined program after reset release
In a CPU reset system, the reset control circuit includes means for generating a reset signal when the power is turned on, and releases the reset after the power is stabilized, wherein the reset control circuit is provided with a commercial power source or a step-down source of the commercial power source. a trapezoidal wave generation circuit that full-wave rectifies the generated AC signal and clamps it to a constant voltage to generate a trapezoidal wave, a DC power supply circuit that generates a DC voltage signal from a commercial power supply, and an output signal of this DC power supply circuit and the trapezoidal wave. an AND circuit that calculates an AND with the output signal of the wave generation circuit and releases the reset of the CPU when the result is logical 1; and a reset release signal that maintains the reset release state of the CPU after the reset is released. A CPU reset system characterized by providing a means for generating.