JPS6377730A - Multilayer substrate - Google Patents
Multilayer substrateInfo
- Publication number
- JPS6377730A JPS6377730A JP61221804A JP22180486A JPS6377730A JP S6377730 A JPS6377730 A JP S6377730A JP 61221804 A JP61221804 A JP 61221804A JP 22180486 A JP22180486 A JP 22180486A JP S6377730 A JPS6377730 A JP S6377730A
- Authority
- JP
- Japan
- Prior art keywords
- voids
- substrate
- gas
- multilayer
- gas vent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title abstract description 23
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 238000010030 laminating Methods 0.000 claims abstract 2
- 238000003475 lamination Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 239000011800 void material Substances 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000003825 pressing Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 244000061354 Manilkara achras Species 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000013022 venting Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層基板のＰ＃層方法に係り、特に積層時に発
生した積層基板間のガス抜きか良くボイドの無い積層基
板に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a P# layer method for multilayer substrates, and particularly relates to a multilayer substrate that is free from voids and has good gas removal between the multilayer substrates during lamination.
従来、積層板積み十げ法については安達芳夫、島田良己
の共訳によるプリント１回路ハンドブックの第５章−５
３項において掲載さねている。１〜かし積層時のガス発
生によるボイドにげのためのガス抜き大忙ついては配慮
さねていなかった。Previously, the laminate stacking method was described in Chapter 5-5 of the Print 1 Circuit Handbook, co-translated by Yoshio Adachi and Yoshimi Shimada.
It is not listed in Section 3. 1. No consideration was given to the busy process of venting gas to eliminate voids caused by gas generation during stacking.
〔発明が解決１．ようとする問題点〕 筑３図１に従来技術による積層時の断面図を示す。[The invention solves the problem 1. [Problems to be solved] Chiku: Fig. 1 shows a cross-sectional view during lamination according to the prior art.
外層基板−１，１′とプリプレグ−２，２′の間及び内
啼基板−３とプリプレグ−２，２′の間に積層時の加熱
によりガスが発生１．ボイド−３ができる。Gas is generated between the outer layer substrates 1 and 1' and the prepregs 2 and 2' and between the inner substrate 3 and the prepregs 2 and 2' due to heating during lamination.1. Void-3 is created.
この図はｔｔ＃ｍ工程か進むにつれボイド−３が材料端
面側へ押［７出され行く状態を示す。した１〜中央から
端面までの距離が長いため積層工程終了までにボイド−
３が押し高さねにくい。以上のように従来技術ではボイ
ドが残りやすいという点で問題があった。This figure shows a state in which the void 3 is pushed toward the end surface of the material as the tt#m process progresses. Since the distance from the center to the end face is long, voids may occur by the end of the lamination process.
3 is difficult to push high. As described above, the conventional technology has a problem in that voids tend to remain.
本発明の目的は上記問題点な解決Ｅ７、ボイドの抜けの
良い多層基板の′ＮＷ１方法な実現することにある。The object of the present invention is to solve the above-mentioned problems E7 and to realize a multilayer substrate 'NW1 method with good void removal.
本考案では積層基板の表布として使用さねない位置にガ
ス抜き穴を設けたことにより前記問題点の解決な図って
いる。The present invention attempts to solve the above-mentioned problems by providing gas vent holes in positions that cannot be used as outer fabrics of the laminated substrate.
積層基板の製品としで使用されない位置にガス抜キ穴を
設けたことにより、積層時に積層基板間に発生したボイ
ドの端面までの距離が短くなり、ボイドの抜けが良くな
り、ボイド残りの無い多層基板な′μｓ昌できる。By providing gas vent holes in the positions of the laminated substrates that are not used in the product, the distance to the end face of the voids that occur between the laminated substrates during lamination is shortened, and the voids can be easily removed, making it possible to create a multilayer product with no residual voids. You can change the board size.
〔実７羅〕ンＩＩ Ｊ
以下、本発明θ）一実施例を第１図、第２図により説明
する。第１図は本発明の実施例１の槓ノー基板の構成図
である。ダト層基板−１，１１，プリプレグ−２，２１
及び内層基板−６の製品として使用されない位置にガス
抜き穴−５か設けられている。第２１ゾ１は第１図に示
才実施例の釉層時断面図である。[Example 7] N II J Hereinafter, one embodiment of the present invention θ) will be described with reference to FIGS. 1 and 2. Embodiment 1 FIG. 1 is a configuration diagram of a base plate according to a first embodiment of the present invention. Dato layer substrate-1, 11, prepreg-2, 21
Also, a gas vent hole 5 is provided in a position of the inner layer substrate 6 that is not used as a product. No. 21 1 is a sectional view of the glaze layer of the embodiment shown in FIG.
嘴層時の加勢により外層基板−１，１°とプリプレグ−
２，２１０聞及び内層基板−６とプリプレグ−２，２’
の間にガスか発生しボイド−６ができる。Due to the force applied during the beak layer, the outer layer substrate -1,1° and the prepreg -
2,210 layers and inner layer substrate-6 and prepreg-2,2'
During this time, gas is generated and void-6 is formed.
積層工程か進むにつむ、ボイド−３か材料端面及びガス
抜き大側へ押し出さハて付く。既に述べた如く、ガス抜
き穴−５を設けたことによりボイド−３の端面及びカス
抜き穴−５−１：での距離が短くなり、積層工程終了ま
でにボイド−３かスムーズに押し、出される。As the lamination process progresses, the void 3 is pushed out to the end face of the material and the large side of the gas vent. As already mentioned, by providing the gas vent hole 5, the distance between the end face of the void 3 and the waste removal hole 5-1 is shortened, and the void 3 can be smoothly pushed and ejected by the end of the lamination process. It will be done.
以上の様に本実施例によれば、積層基板の積層１時に発
生した積層基板間のガス抜きか良くボイドの無い多層基
板を製造することができろ。As described above, according to this embodiment, it is possible to manufacture a multilayer substrate without voids, which can be well vented between the laminated substrates during the first lamination of the laminated substrates.
〔発明の効果Ｊ
本発明によねば、積層基板の積層時に発生したＮ層系板
間のガス抜きか良くなるので、ボイドの無い多層基板を
製造することかできる。[Effect of the Invention J] According to the present invention, gas removal between the N-layer boards that occurs during lamination of the multilayer board is improved, so a multilayer board without voids can be manufactured.
第１図は本発明の一実施例による積層基板の構成図、第
２図は本発明による積層時断面図、第６図は従来技術に
よろ積層時断面図である。
１．１１・・・外層基板、２．２１・・プリプレグ、３
・・・内層基板、４・・ボイド、５・・ガス抜き穴。FIG. 1 is a configuration diagram of a laminated substrate according to an embodiment of the present invention, FIG. 2 is a cross-sectional view when laminated according to the present invention, and FIG. 6 is a cross-sectional view when laminated according to the prior art. 1.11...Outer layer substrate, 2.21...Prepreg, 3
...Inner layer substrate, 4..Void, 5..Gas vent hole.
Claims (1)
プレグあるいは樹脂を塗布し、積み重ねて行く多層基板
の積層方法において、積層基板の製品として使用されな
い位置に積層時の加熱によつて発生したガスによるボー
ドをにがすためのガス抜き穴を設けたことを特徴とする
各層基板。1. In the method of laminating multilayer boards in which circuits are formed on one or both sides, prepreg or resin is coated and stacked, gas generated by heating during lamination may occur in positions of the multilayer board that will not be used as a product. Each layer board is characterized by having gas vent holes for peeling off the board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61221804A JPS6377730A (en) | 1986-09-22 | 1986-09-22 | Multilayer substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61221804A JPS6377730A (en) | 1986-09-22 | 1986-09-22 | Multilayer substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6377730A true JPS6377730A (en) | 1988-04-07 |
Family
ID=16772456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61221804A Pending JPS6377730A (en) | 1986-09-22 | 1986-09-22 | Multilayer substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6377730A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0556429U (en) * | 1991-12-28 | 1993-07-27 | トヨタ車体株式会社 | Interior material |
| US6732905B2 (en) * | 2002-04-16 | 2004-05-11 | Agilent Technologies, Inc. | Vented cavity, hermetic solder seal |
| WO2013005720A1 (en) * | 2011-07-06 | 2013-01-10 | 株式会社 豊田自動織機 | Circuit board, and manufacturing method for circuit board |
| JP2018167401A (en) * | 2017-03-29 | 2018-11-01 | 日本ガスケット株式会社 | Method of producing resin member |
| US10329696B2 (en) * | 2012-12-21 | 2019-06-25 | Cytec Industries Inc. | Curable prepregs with surface openings |
| JP2020120024A (en) * | 2019-01-25 | 2020-08-06 | 株式会社村田製作所 | Manufacturing method of multilayer substrate |
-
1986
- 1986-09-22 JP JP61221804A patent/JPS6377730A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0556429U (en) * | 1991-12-28 | 1993-07-27 | トヨタ車体株式会社 | Interior material |
| US6732905B2 (en) * | 2002-04-16 | 2004-05-11 | Agilent Technologies, Inc. | Vented cavity, hermetic solder seal |
| GB2387562B (en) * | 2002-04-16 | 2005-06-15 | Agilent Technologies Inc | Method of attaching componenets and component structure |
| WO2013005720A1 (en) * | 2011-07-06 | 2013-01-10 | 株式会社 豊田自動織機 | Circuit board, and manufacturing method for circuit board |
| CN103621190A (en) * | 2011-07-06 | 2014-03-05 | 株式会社丰田自动织机 | Circuit board, and manufacturing method for circuit board |
| US10329696B2 (en) * | 2012-12-21 | 2019-06-25 | Cytec Industries Inc. | Curable prepregs with surface openings |
| US10821680B2 (en) * | 2012-12-21 | 2020-11-03 | Cytec Industries Inc. | Curable prepregs with surface openings |
| JP2018167401A (en) * | 2017-03-29 | 2018-11-01 | 日本ガスケット株式会社 | Method of producing resin member |
| JP2020120024A (en) * | 2019-01-25 | 2020-08-06 | 株式会社村田製作所 | Manufacturing method of multilayer substrate |
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