JPS6377365U - - Google Patents

Info

Publication number
JPS6377365U
JPS6377365U JP1986171614U JP17161486U JPS6377365U JP S6377365 U JPS6377365 U JP S6377365U JP 1986171614 U JP1986171614 U JP 1986171614U JP 17161486 U JP17161486 U JP 17161486U JP S6377365 U JPS6377365 U JP S6377365U
Authority
JP
Japan
Prior art keywords
fixed
base plate
optical system
optical
flat package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986171614U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986171614U priority Critical patent/JPS6377365U/ja
Publication of JPS6377365U publication Critical patent/JPS6377365U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案のフラツトパツケージ形光モジ
ユールの一実施例のカバーケース固定前の斜視図
、第２図は従来のフラツトパツケージ形光モジユ
ールのフタ固定前の斜視図である。 １……ベース板、２……カバーケース、３……
溶接部、４……光学系、５……接続端子、６……
ボンデイングワイヤ、７……光フアイバ挿入用パ
イプ、８……ケース、９……フタ。

Claims (1)

    【実用新案登録請求の範囲】
  1. フラツトパツケージ形光モジユールにおいて、
    平板状のベース板上に発光素子、集光素子等から
    なる光学系が固定され、カバーケースが前記光学
    系を履うように前記ベース板に固定されているこ
    とを特徴とするフラツトパツケージ形光モジユー
    ル。
JP1986171614U 1986-11-07 1986-11-07 Pending JPS6377365U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986171614U JPS6377365U (ja) 1986-11-07 1986-11-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986171614U JPS6377365U (ja) 1986-11-07 1986-11-07

Publications (1)

Publication Number Publication Date
JPS6377365U true JPS6377365U (ja) 1988-05-23

Family

ID=31107402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986171614U Pending JPS6377365U (ja) 1986-11-07 1986-11-07

Country Status (1)

Country Link
JP (1) JPS6377365U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05175552A (ja) * 1991-12-25 1993-07-13 Nec Corp 光学素子基板の実装構造

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05175552A (ja) * 1991-12-25 1993-07-13 Nec Corp 光学素子基板の実装構造

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