JPS6377246A - Digital phase modulation circuit - Google Patents

Abstract

PURPOSE:To cause phase inversion and to obtain a desired phase modulation wave by receiving an input digital signal, applying band limit by an LPF and exclusively ORing an output polarity bit and an output from an oscillator. CONSTITUTION:An output of a digital LPF 21 consists of a polarity bit output SB (most significant bit) representing the polarity through the addition of prescribed band limit from a digital input signal Sin by a ROM 23 and an output group AB representing the amplitude. The output SB and a carrier CR from an oscillator 22 are inputted to an exclusive CR gate 23, where multiplication of logical '1', '0' is applied. As a result, the phase of the carrier CR is deviated to '0' or pi in response to the polarity (1, 0) of the input signal Sin and basic biphase modulation is applied. Thus, no direct multiplication is applied between the digital input signal Sin and the carrier CR, the sampling frequency is not interposed.

Description

[Detailed Description of the Invention] [Summary] This is a digital phase modulation circuit that combines the polarity bit of the output from a digital low-pass filter that limits the band of a human-powered digital signal and the output from an oscillator that generates a one-wave transmission wave. By calculating the exclusive OR, phase inversion is caused and a required phase modulated wave is obtained, thereby making it possible to make the frequency of the carrier wave higher than before.

[Industrial application field]

The present invention relates to a digital phase modulation circuit.

With the expansion of computer systems in recent years, the need for exchanging data with remote terminal devices and the like has increased, and for this reason, the importance of digital data transmission systems is increasing. -Finally, amplitude modulation, frequency modulation, phase modulation, etc. are used to transmit digital data on a carrier wave, and the present invention refers to a digital modulation circuit based on phase modulation. This digital phase modulation circuit is particularly suitable for wireless data transmission.

[Conventional technology]

FIG. 6 is a diagram showing an example of a conventional digital phase modulation circuit. In this figure, a digital phase modulation circuit 10 outputs a digital human input signal S i to be digitally phase modulated.
n and sends out a phase modulated output S out. Signal S1. , first, a digital low-pass filter (LP
F) is applied to 11, where a certain band limit is applied (see fB in the figure), and then input to multiplier 13. Multiplication 3
t3, on the other hand, receives the encoded carrier CR' (frequency r') from the carrier generator 12 and multiplies CR' by the output of the low-pass filter 11 'T,'1. Digital modulation is performed here.

The grain transmission wave generator 12 is connected to a clock generator 16 that supplies a constant clock, and uses its clock output CL (frequency fs) to generate the encoded transmission alcR' by sampling at the sampling frequency Ors. . This Jf sending wave CR' represents a sine wave as an analog.

The output from the multiplier 13 is digital/analog (D/analog).
A) It is converted into an analog output by the conversion 314, and a required band component of this analog output is extracted by the low-pass filter 5 to obtain the target phase modulation output S'. ,
get.

FIG. 7 is a diagram showing the frequency spectrum of the signals appearing at ■ and ■ in FIG. 6, where (1) and (2) correspond to the signals at ■ and ■, respectively.

Each horizontal axis in (1) and (2) of Fig. 7 is the frequency f
As described above, r and (ro represent the frequencies of the clock output CL and the carrier wave CR', respectively.

In (1) of this figure, the center frequency f.

A so-called folded component Q, which is obtained by folding the spectrum of a bandwidth 2f designated as Drc, is shown. This aliasing component Q inevitably appears due to the sampling described above, and in order to remove it, the low-pass filter 5 shown in FIG. 6 is provided. The spectrum appearing in the output of this filter 5 is as shown in (2) of FIG.
The aliasing component is removed as shown by the dotted line.

[Problem that the invention seeks to solve]

As is clear from the frequency spectrum in FIG. 7, the frequency r'o of single-shell transmission is r.

After all, r'o cannot be chosen higher than 1-fB. This is an inherent restriction caused by sampling; for example, f'o is limited to a few M11z at most.

However, such low (ro) is inconvenient.

For example, can it be installed at the end of a data transmission system? In the 1100E, several tens of MHz 7'l< is adopted as the carrier wave frequency, and there is a problem in that a so-called asopcon hearter is required to shift from the above-mentioned several M Ilz to 10 MIIz.

Further, although the circuit shown in FIG. 6 includes the multiplier 1γ multiplier 13 as an essential component, it occupies a considerable amount of hardware in the modulation circuit 10, leading to an increase in cost. It is therefore desirable to obtain a phase modulated output with a higher carrier frequency and to simplify the multiplier.

[Means for solving problems]

FIG. 1 is a diagram showing the principle structure of a digital phase modulation circuit based on the present invention. The digital phase modulation circuit 20 of the present invention includes a digital low-pass filter 21 (same as the conventional digital low-pass filter 11) that receives a digital input signal S in, and a digital/analog (D /A) It has a converter 24, but an exclusive OR gate 23 is provided in place of the conventional multiplier 13, and an oscillator 22 is provided in place of the conventional pair of clock generator 16 and sonic wave generator 12. It will be done.

The oscillator 22 preferably outputs a square wave pulse, which becomes the carrier wave CR (frequency fc). 25 is a bandpass filter that removes unnecessary waves included in the analog output from the converter 24 to obtain a target phase modulation output S. get ut.

[For production]

The output of the digital low-pass filter 21 is a polarity bit output S B representing the polarity of the digital input signal SL, .
(MSB: Mo5t 51gn1ficant
Bit) and LSB (Least 5
1gn1ficant Bit). The exclusive OR gate 23 receives the polarity bit output SB and the carrier wave CR as inputs, and performs a multiplication operation on these. In other words, the logic of SB and CR (“1”
, @0") are equal, and l" if they are different. (This is the opposite of the result in normal arithmetic operations, but a product of the same sign takes one logic, and a product of opposite signs takes the other logic. Logic is multiplication).Thus, the human signal S =
Depending on the positive or negative value of n (1", "0"), the phase of the carrier wave CR is shifted to O or π, and basic two-phase phase modulation is performed.As an extension of this, four-phase phase modulation can also be realized (as described later). ).

In this way, the digital input signal S in and the carrier C
Since direct multiplication with R is not performed, the sampling frequency fs does not intervene as in the conventional case. In other words, the phase of the carrier wave CR is simply shifted to 0 or π depending on the polarity of the signal S in. As a result, the carrier wave f', as in the conventional case. is f.

f'. It is freed from the constraint that ≦−−f. Also, components 12, 13 and 16 in the conventional circuit 10 (FIG. 6) are replaced by the circuit 20 of the present invention.
Components 22 and 23 in FIG. 1 have been changed and are greatly simplified.

〔Example〕

FIG. 2 is a diagram showing a detailed example of a part of the present invention, and components similar to those in FIG. 1 are designated with the same reference numerals or symbols. The digital low-pass filter 21 includes a shift register 31, a multiplier 32, and a ROM (Read 0
33, forming a so-called binary transversal filter as a whole. The clock CLK is multiplied by n and then transferred to the shift register 23.
(Serial acquisition of input signal S in) The shift frequency is determined. The ROM 33 stores data such as tap coefficients in a general transversal filter, and an output with a predetermined band limit added is obtained as shown in the figure (■).

FIG. 3 is an explanatory diagram of each signal that appears at ■ and ■ in FIG. 2, and (1) in FIG. 3 shows the signal that appears at the output side of the digital LPF 21 in an analog state. On the other hand, the same figure (
2) is a signal appearing on the output side (3) of the bandpass filter 25, that is, a two-phase phase modulation output S. Indicates uL. The same figure (1
) changes the polarity (positive above the center level O, negative below the center level). It shows how the phase of uL is reversed, and it can be seen that two-phase phase modulation is performed.

FIG. 4 is a diagram showing the frequency spectrum of each signal appearing at ■ and ■ in FIG. 2, and (1) in FIG. 4 corresponds to the signal appearing at the output side (2) in the diagram
is the signal appearing at the output side (2) of the filter 25, that is, the two-phase phase modulation output S. Corresponds to uL. In this figure, "," is the seventh
Similar to the figure, it represents the baseband band of the input signal Si, , after being band limited, and its center frequency is f, which is the frequency of the carrier wave CR. This f is (1,
is not constrained by the sampling frequency f, and can choose f to be higher than fl.

By the way, the analog output of the D/A converter 24 has a fourth
As shown in Figure (1), f, ±nf.

(where n is the multiplication number of the multiplier 32 (Figure 2)), unnecessary waves R and R' appear, so these are removed by the bandpass filter 25 (Figure 2) and only the required band components are extracted. (Spectrum in Figure 4 (2)).

FIG. 5 is a diagram showing an example of applying the present invention to four-phase phase modulation. In this figure, the digital phase modulation circuit 40 is basically a circuit in which the circuit in FIG. 2 is used as the I (In-phase) channel side, and the oscillation output of the oscillator 22 in the circuit in FIG. 2 is shifted in phase by -. Q (Quadra
(true phase) corresponds to a combination of these on the channel side. ■To distinguish between channel and Q channel, refer to the reference number 1. It is represented by adding Q. The above combination is performed by an adder 41. Sl, , are I-channel digital human input signals, and SQ, , are Q-channel digital input signals.

A □ phase shifter 42 is provided on the Q channel side to shift the phase of the oscillation output by □.

〔Effect of the invention〕

As explained above, according to the present invention, the carrier wave frequency can be set higher than that in the past, and the circuit can be made smaller and simpler.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle configuration of a digital phase modulation circuit based on the present invention, Fig. 2 is a diagram showing a partially detailed example of the present invention, and Fig. 3 is an explanatory diagram of each signal appearing in ■ and ■ in Fig. 2. , Fig. 4 is a diagram showing the frequency spectrum of each signal appearing in ■ and ■ in Fig. 2, and Fig. 5 shows an example in which the present invention is applied to four-phase phase modulation.
, FIG. 6 is a diagram showing an example of a conventional digital phase modulation circuit, and FIG. 7 is a diagram showing the frequency spectrum of the signals appearing in ■ and ■ in FIG. 20... Digital phase modulation circuit, 21... Digital low pass filter, 22... Oscillator, 23... Exclusive OR gate, 24... Digital/analog converter, 25... Band pass filter , S i++... digital input signal, S out...
・Phase modulation output, CR...carrier wave. Fig. 3 is a diagram showing the frequency spectrum of the signal, Fig. 4 is an example of a conventional dinotal phase modulation circuit, and Fig. Figure 7 shows the frequency spectrum of the appearing signal.

Claims (1)

[Claims] 1. Input digital signal to be digitally phase modulated (S
a digital low-pass filter (21) that adds a band limit to the input digital signal (S_i_n) and outputs a polarity bit output (SB) representing the polarity of the input digital signal (S_i_n) and an amplitude bit output group (AB) representing the amplitude; an oscillator (22) that sends out the carrier wave (CR), an exclusive OR gate (23) that multiplies the carrier wave (CR) and the polarity bit output (SB), and the exclusive OR gate (
a digital/analog converter (24) that converts the output of 23) and the amplitude bit output group (AB) into an analog output;
); and a bandpass filter (25) that extracts only required band components from the analog output and sends out a phase modulation output (S_O_U__T).