JPS5870606A - Digital demodulator for fm signal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE PRIOR ART The present invention relates to a digital demodulator according to the subject concepts of claims 1 and 9.

A digital receiver with a digital demodulator is already known from DE 30 07 907 A1. However, this publication does not describe the configuration of the demodulator or its operation. Therefore, a circuit arrangement constituting a digital demodulator is not known.

Effects of the Invention The demodulator for FM signals of the present invention having the features set forth in claims 1 and 9 has the advantage that it can be constructed using known digital elements. Furthermore, digital signal processing has the advantage that the results are absolutely reproducible and independent of temperature and aging.

There is no issue of compensation. Furthermore, it is advantageous that this type of circuit device can be configured to be integrated. This is made possible in particular by not using coils and large capacitances. Another advantage is that the accuracy of the signal resolution can be selected arbitrarily and that the intermediate frequency bandwidth can be controlled depending on the reception quality. This is because this can be easily done with digital signals or digital words.

Advantageous embodiments of the demodulator according to the claims 1 and 9 are possible by means of the configurations described in the implementation section of the patent claims. It is particularly advantageous if the Hilbert transformation is performed approximately by offset sampling and subsequent interpolation. This configuration allows the demodulator to be constructed particularly simply. Furthermore, it is advantageous to provide the amplitude adjustment by means of an acyclic filter. This configuration improves the precise functioning of the demodulator in the case of high frequency deviations.

In another embodiment of the invention, F in digital form
, M signals are each multiplied by 5in- and cos functions. This type of signal processing provides signals that are mutually Hilbert transformed by acyclic filters without the need for interpolation circuits. By using this filter, components with twice the intermediate frequency resulting from multiplication are suppressed. In order to improve the operation of the demodulator, it is advantageous to provide a separate digital acyclic filter in each case. This reduces the sampling rate of the digital signal depending on the respective filter, so that cost-effective components can be used.

The acyclic filter preferably consists of a RAM, which is a shift register or a state memory, in which the coefficients determining the characteristics of the filter are written in storage elements.

Further advantages become clear in connection with the subsequent description of the exemplary embodiments with the aid of the drawings.

Description of examples Next, the present invention will be explained in detail using illustrated embodiments.

The demodulator to be described is particularly suitable for demodulating intermediate frequency signals of very high frequency radio receivers, starting from an intermediate frequency of 10.7 MH2. The demodulator is also suitable for demodulating further FM signals, such as those used for example in carrier frequency communication transmissions. In order to manufacture demodulators at low cost, especially digital modules, -
It is important to consider file density and processing speed. The demodulator was therefore constructed in such a way that each subsystem can in each case operate with the very lowest sampling frequency theoretically possible in the system.

For frequency detection in the intermediate frequency range, zero-crossing discriminators following simple counting methods have the disadvantage of high counting frequencies. On the one hand, high clock frequencies lead to high power losses in the state of the art, and in addition, modules of this type are expensive. Therefore, in the demodulator of the present invention, the high resolution on the time axis corresponding to the accuracy of instantaneous frequency detection is as follows:
This is not possible because the sampling rate must be extremely high. The demodulation principle described below is based on the fact that the intermediate frequency signal is downconverted to the baseband range, so that the demodulator requires only a very low operating frequency. Figure 1 shows digital FM
- a block circuit diagram of the demodulator; The input signal to the demodulator is analog and is extracted up to the intermediate frequency amplification 6. This signal is supplied to AD converter 55. At the output of the AD converter 55 appears a digital word with a length of 1, for example 8 bits. This digital word is fed to multipliers 56 and 57. In multiplier 56, the resulting carrier frequency f after sampling. is multiplied by a cos function, and multiplier 57 multiplies by a sine function. Multipliers 56 and 57 operate digitally.

A digital low-pass filter 58 is connected downstream of the multiplier 56 . A digital low-pass filter 59 is likewise connected downstream of the multiplier 57. Digital low pass filter 58
is followed by a delay circuit 60, which can be constructed, for example, by 16 parallel-connected flip-flops in a 16-bit digital word. Similarly, a delay circuit 61 is connected downstream of the low-pass filter 59. Due to quantization noise, a longer digital word is obtained at the output of the filter than at the input of the filter. In multiplier 62 the digital word at the output of delay circuit 60 is multiplied by the digital word occurring at the output of low-pass filter 59 . A multiplier 63 multiplies the output of the delay circuit 61 and the output of the digital filter 58.

The digital output value of the multiplier 63 is input to the subtracter 64 as
It is subtracted from the digital output value of multiplier 62. Subtractor 6
4 is followed by an arc-, sin table.

A frequency modulated signal having a predetermined carrier frequency is applied to the AD converter 55, the bandwidth of the carrier frequency being determined by the pass characteristic curve of the intermediate frequency filter.

The AD conversion takes place at equidistant time intervals, with the AD converter 55 being clocked by the sampling frequency. The minimum value of the sampling frequency is determined by the 5hannon sampling theorem, with reference to the bandwidth of the intermediate frequency signal, which is substantially equal to It is determined by the filter bandwidth.

In a multiplier 56, the digital word occurring at the output of the AD converter 55 is multiplied by a cos function.

This Co8 function must also be provided in digital form. In this example, one sampling is arbitrarily selected. That is, after the AD converter 55 f0=f
A new intermediate frequency arises which is A/4, with f. is A
This is the center frequency generated at the output side of the D converter 55, and the frequency is the sampling frequency. In general, the conditions for the sampling frequency to be satisfied are 1, where fZF is the intermediate frequency before sampling. If the intermediate frequency is, for example, 10', 7 MHz and N=i is chosen, the above equation yields a sampling frequency of 8.56 M)IZ. The new center frequency f0 then occurring at the output of the AD converter is 2.14 MHz. Based on this selection of the sampling frequency, digital multiplication is performed at the zero crossings or maxima of the cos function. Multiplications in multiplier 56 therefore take place exclusively with the values +1.0 and -1, so that in terms of circuit technology only a polarity inversion is necessary for the multiplications. In other cases, the multiplications must be carried out exactly in time, so that the circuit is considerably simplified. Digital multiplier 57
In , multiplication with the sln function is performed. By choosing the sampling frequency accordingly, as already mentioned, the multiplication only needs to be carried out with the values 1.0 and -1, so that in this case too only a polarity reversal is carried out. Incidentally, on the output side of multipliers 56 and 57, in addition to the pacepan r signal, there is another term including K and twice the carrier frequency.

Before the pull-in, signals containing twice the carrier frequency are suppressed by low-pass filtering by digital low-pass filters 58 and 59. The output signals of filters 58 and 59 are mutually Hilbert transformed.

The output signal of the low-pass filter is a cosine to sin signal whose variables include the integral of the effective signal. That is, it is an FM signal having a carrier wave O. Low pass filter 58
appears on the output side of . In this case ΔΩ is the frequency deviation and V is the dimensionless effective signal controlled by 1 in the range -1 to +1. From this, for example, the output signal of the low-pass filter 58 is arc - cos
It is not uniquely detected due to -7fe formation. This is because the integral value of V arbitrarily exceeds the variable range ±π/2. Therefore, the solution is ambiguous.

Therefore, the difference formation of variables must be performed so that the variables fall within a predetermined range.

This can be done by the following calculation.

(k=1.2....) For sufficiently high sampling frequencies, it can be simplified as follows.

1(T) This simplification results in only linear distortion of low frequency signals (
weak low-pass effects), but they can be easily compensated for by demodulation f.

To achieve this relationship, the digital output signal of low-pass filter 59 is multiplied by a first preceding value of the output signal of low-pass filter 58. Therefore, delay circuit 60 is used to delay the output signal of low pass filter 58 by one clock. This can be done simply by means of a storage element, for example a flip-flop chain circuit, which corresponds to the word length. Similarly, the output signal of the low-pass filter 58 is multiplied by the first preceding value of the output signal of the low-pass filter 59 by a multiplier 63 .

Therefore, the following signal appears on the output side of the multiplier 62, namely g(kT)='-(sinC'v(kT)-T), while the signal g(kT) appears on the output side of the multiplier 63. = Yu(-sin(鴫v(kT)-T)”
appears.

After subtracting both signals of multipliers 62 and 63 by subtraction δ64, the demodulated output signal can be retrieved as a sin function. At this time, the output signal of the subtracter 64 is
It has the form of 5in(''・v''(kTIT).For example, by the arc-sin table stored in the ROM,
An effective signal can be uniquely obtained by performing an arc-sin operation. However, in order to obtain a unique result, it is assumed that the variable of this sin term falls within the range between −π/2 and +π/2, so that arc −s
A valid signal is uniquely obtained from the in operation. This condition results in a car demodulator sample frequency that is not allowed to fall below. For example, with a frequency shift of 75 KHz, as is customary in radio broadcasting, one minimum sampling frequency of the demodulator section is 300 KHz. It is advantageous to select the sampling frequency somewhat higher, for example in the range of 500 KH2. Due to the low sampling frequency after filtering, it is advantageous to reduce the sampling rate at the outputs of the low-pass filters 58 and 59. Specific examples will be given later. To simultaneously satisfy 5hannon's sampling theorem,
The bandwidth of the low-pass filter must not exceed 1/2 the sampling frequency.

Due to the frequency detuning in the analog mixer, a digital in-phase component occurs in the demodulator, which can then optionally be used for tracking control of the tuning (AFO).

A constant amplitude of the FM signal is required for correct functioning of the demodulator. Therefore, the amplitude changes must first be adjusted by an analog adjustment amplifier in the intermediate frequency circuit. Only in this way can the AD converter be optimally controlled. Fast amplitude changes, which appear, for example, as AM noise, are preferably adjusted digitally by a multiplier in the signal path. A reference for the required amplification factor is obtained from the output signal of the low pass filters 5 and 59. The sum of the squares of the output signals of the low-pass filters 58 and 59 corresponds to the square of the instantaneous amplitude for each sampling instant. This makes it possible to correct the amplitude of each sample value. The amplitude distortion caused by multiplication can therefore be quickly adjusted. Filters 58 and 5
For more information on designing digital filters like 9, see
Schussler, “Digital Systems Zur Signal Fair Part-time Job Lang” (Sderin, Berlin,
Heidelberg, New York, 1976).

It is preferable to use an acyclic filter.

This is because an acyclic filter advantageously provides a linear phase. This is very effective because, due to the very constant group delay time, the non-linear distortion of the low frequency signal is reduced and the stereo-channel separation can be significantly improved.

Acyclic filters require high multiplication costs that can only be reduced by: That is, it is
In each subsystem the sampling frequency is chosen as low as possible and additionally a subsampling is carried out on the output side. Similar considerations apply to AD converters. In order to accurately detect the waveformed output signal in the intermediate frequency mixer, a sampling frequency on the order of 50 MHz is required when using the 5hannon sampling theorem. This value can be significantly reduced if the AD converter is preceded by an analog bandpass filter whose center frequency is at the carrier layer' wave number. This is for example the intermediate frequency at 1Q,'7M[(z). This bandpass filter should, on the one hand, have such a bandwidth that the useful signal does not have significant phase distortion in the frequency domain; on the other hand, its The bandwidth is chosen small enough so that an effective reduction in the sampling rate of the AD converter occurs. For ultrashort fatigue radio reception with a frequency deviation of ±75 KHz, for example Bandwidth is advantageous.Using this numerical example, let us explain the block diagram of FIG. 2 of a digital demodulator with an acyclic filter.

An AD converter 70 is connected downstream of an intermediate frequency amplifier (not shown) with a bandpass filter, and multipliers 71 and 72 are connected to the output side of the AD converter. Multiplier 71 performs digital multiplication with a COS function, while multiplier 72 performs digital multiplication with a sine function. By appropriate selection of the sampling frequency of the AD converter, it is possible to make it possible to perform only a polarity reversal in terms of circuit technology. An acyclic filter 73 is connected downstream of the multiplier 71, the output signal of which is sampled at a relatively low frequency by a switch 75. Another acyclic filter 7 is connected to the switch 75.
7 is connected afterward, and its output signal is connected to switch 79.
sampled again using

Switch 79 operates at a lower frequency than switch 75. A switch of this type is technically constituted by a register which is clocked in such a way that only the fourth value of a single data string is transferred in each case, for example with a sub-sampling factor of 4. The output signal of switch 79 is each delayed by one clock time via delay circuit 81.

The output signal of multiplier 72 is processed in a similar manner.

An acyclic filter 74 is connected downstream of the multiplier 72, the output signal of which is sampled by a switch 76. A further acyclic filter 78 is connected downstream of the switch 76, the output signal of which is sampled via a switch 80. The clock frequency of switch 80 is the same as the clock frequency of switch 79. switch 80
The output signal is fed on the one hand to the input side of the digital multiplier 83 and on the other hand to the delay circuit 82.

The delay circuit delays the output signal of switch 80 by one clock pulse. Another input side of the multiplier 83 is supplied with the output signal of the delay circuit 81. The input side of the multiplier 84 is supplied with the output signal of the switch 79 on one side and the output signal of the delay circuit 82 on the other side. The output signal of the multiplier 84 is sent to the multiplier 8 in the digital subtraction circuit.
is subtracted from the output signal of 3. The subtraction circuit 85 can also be connected afterward with an arc-5in surface 86.

Clock generator 67 supplies a clock frequency to AD converter 70 . Clock generator 67 includes a clock generator 1 that supplies a clock frequency to switches 75 and 76.
: A 4-frequency divider 68 is connected. A further frequency divider 69 is connected downstream to the output of the frequency divider 68, which divides the clock signal once again by 1/4. The output signal of frequency divider 69 is used to control switches 79 and 80.

The operation of this circuit device will be explained in detail with reference to FIGS. 6 to 6a to 6c. In Figures 4 and 5,
Digital signal values are illustrated as amplitudes on the ordinate.

The input signal should be sampled by the AD converter 70 at a sampling frequency as low as possible while still satisfying the sampling theorem. Furthermore, the clock generator 67 must generate a signal with a frequency that is at least twice the bandwidth of the analog bandpass filter before the AD converter 70. Another condition that must be taken into account is that the original intermediate frequency 1d is converted into a lower intermediate frequency position fQ by sampling, and because of the simple construction of the multipliers 71 and 72, the intermediate frequency is The point is that it should have a frequency of 174. This can be done by choosing a frequency for the sampling frequency that is, for example, 475 of the input intermediate frequency. If the bandwidth of the preceding intermediate frequency filter is, for example, 1 MHz and the intermediate frequency is 10.7 MHz, a suitable sampling frequency is, for example, 8.56 MH2. In that case, the above? Based on the formula, a lower intermediate frequency position at 174 of the sampling frequency occurs, so that the lower intermediate frequency position is 2.14
It is MH2.

As FIG. 3a) shows, a new FM spectrum arises, in particular at a carrier frequency of 2.14 MHz, with this digital spectrum having a bandwidth of 2 MHz according to the analog prefilter. At this time, in addition to the baseband signals after orthogonal demodulation by the multipliers 71 and 72, spectra centering on twice the carrier frequency are generated, as shown in FIG. 3, respectively. At a carrier frequency of 2.14 MHz, this is 4.28 MHz. This additional spectrum is suppressed by acyclic filters 73 and 74. The frequency characteristics of this acyclic filter are shown by broken lines in FIG. Low pass filter 7
The maximum frequency of the output signals of 3 and 74 is approximately i MHz.
Therefore, the sampling frequency at the output side of the low-pass filter can be reduced to 1/4. Therefore switch 7
5 and 76 sample the output signal of low pass filter 73 and T4 by a frequency of approximately 2.14 MHz.

This process is important in that the cost for downstream selective narrowband filtering is significantly reduced. That is, if this were to be done together with the low-pass filters 73 and 74, the sampling frequency would be four times as high there, so the filter coefficients would be four times as large as in the filters that follow.
It will be more expensive. Acyclic filters 77 and 78
is used to filter the useful signal from a basepan r of 1 MHz width to very high frequency radio waves whose bandwidth is limited to about 150 KH2. The characteristics of these low pass filters are illustrated in FIG. 3C. That is, the minimum required sampling frequency is around 3 Q Q KHz.

This value is equal to arc −sin in the circuit arrangement of FIG.
It also roughly corresponds to the minimum sampling frequency that was necessary for the unambiguousness of the operation. In a specific embodiment, switch 7
The sampling frequency for 9 and 80 was determined by 535 KHz. Subsequent processing of this signal is carried out by multiplier 8
3 and 84 as well as subtractor 85, the same process as already described with reference to FIG. 1 taking place.

- What is important in the circuit arrangement described so far is the construction of the second acyclic filter pair, the details of which are described in the above-mentioned documents. As can be seen in FIG. 6, the slope of the side edges of the first low pass filter is substantially determined by the spacing between the base band and the following band.

A further criterion for the design is the expected cut-off damping. In the first acyclic low-pass diverter, 2.1
For a frequency of 4 MHz, if we choose a cutoff frequency of 6 dB and then calculate the filter using a modified Fourier approximation, then for example 65 Due to the centered Nyquist edge, half of all coefficients are zero. Furthermore, due to the linear phase of the acyclic filter, the filter coefficients are equal pairwise. In total, 5 multiplications each for the digital filter. is carried out, so that for each multiplication the output side of the filter - about 115 of the sampling frequency
is used.

The main cost in this circuit arrangement is the low-pass filter 3
and in low-pass filter pairs 77 and 78, which correspond completely to 4 and 95 and 96. This system is 2.14
It operates with an input sampling frequency of MHz. CO5
In the design of filters in which a frequency profile with roll-off edges is desired, a modified Fourier approximation was also used for calculations. 81] 6dB of KHz
- A fill of a factor of 38 occurs at the pass frequency. In this case, if we establish a symmetrical coefficient, then during clock recitation 1 at a clock frequency of 2.14 MHz, 19
Multiplications are performed.

The configuration for this purpose is the so-called "discrete arithmetic" (discrete arithmetic), where instead of multipliers and adders, fixed-value memories and accumulators are used.
et ik) method.

FIG. 4 shows the digital FM signal appearing in the form of digital words at the output of the AD converter 70. In FIG. 5, the output signal of multiplier 71 is illustrated. Here you can already see the conversion to baseband. Figures 6a to 6c
The figure shows various output signals at the output of the subtractor 85.

FIG. 6a then shows the output signal as it appears at the output during overmodulation of the carrier wave. FIG. 6b shows the output signal present at the output of the demodulator during frequency detuning. The in-phase component, which is optionally used for automatic frequency tracking control, is clearly visible. FIG. 6C shows an FM-band limited low frequency signal.

FIG. 7 shows a specific embodiment of the demodulator of the block diagram in FIG. The input signal reaches the AD converter 8B,
Its output signal is provided to FROM 39 and 90. The output side of FROM 89 is AND element chain circuit 9
1, while the output side of FROM 9 ,Q is led to the input 111+1 of the AND element chain circuit 92. The output side of the AND element chain circuit 91 is
It communicates with an acyclic filter 93 . The output side of this acyclic filter 93 is led to the input side of another acyclic filter 95. The output side of the acyclic filter 95 is
Delay circuit 81 and digital multiplier 84 shown in FIG.
guided by. An acyclic filter 94 is connected to the output side of the AND element chain circuit 92. The output side of this filter is led to the input side of an acyclic filter 96. The output side of the acyclic filter 96 is led on the one hand to the input side of the delay circuit 82 and the multiplier 83 shown in the figure. Clock generator 97 supplies clock signals to AD converter 88 , low pass filter 94 and low pass filter 93 . A frequency divider 98 is connected to the clock generator 97 and reduces the clock frequency to 1/2. The output side of the frequency divider 98 is connected to another input side of the AND element chain circuit 92 and an inverter 100.
It is led to another input side of the D-element chain circuit 91.

Furthermore, a frequency divider 99 is connected downstream of the frequency divider 98, which similarly divides the frequency of one wave number into 1/2. The output of frequency divider 99 is led to the respective clock inputs of PROMs 89 and 90. Furthermore, the output side of the clock generator 97 is led to a frequency divider 101 which reduces the clock frequency to 1/4. By the output signal of frequency divider 101, the output sides of acyclic filters 93 and 94 and the input sides of acyclic filters 95 and 96 are clock-controlled.

Another frequency divider 102 is connected to the output side of the frequency divider 101. The output signals of acyclic filters 95 and 96 are clock-controlled by the output signal of this frequency divider 102, which also divides the frequency into four.

This circuit arrangement is an easily configurable embodiment of the block diagram of FIG. For example, the clock generator 97 has a center frequency of 10.7 MHz and a frequency of 2.
When a signal with a bandwidth of MHz is added, 8.56
It vibrates at a frequency of MHz. The digital signals after AD conversion are supplied to the input sides of PROMs 89 and 90.

A FROM is used to transfer a digital word to the output side unchanged or inverted, depending on the signal at the input side to clock the digital word applied to the input side. The 1/4 VC frequency division by the two frequency dividers 98 and 99 serves to invert every fourth digital word applied to the input side of the FROM.

With this configuration, multiplication with the cos function or multiplication with the sine function can be omitted, and data words at the maximum values 1 and -1 of the cos function and the S1n function and the zero crossing points are generated in each case. That is, AND element chain circuit 9
The digital signal on the output side of 1 is sent to the AD converter 881
C, but the signal sequences are each multiplied by JrL, 1.0, -1.0, . . . .

At the output of the ANU element chain circuit 92, the signal train from the output of the AD converter 88 appears, this signal having been multiplied by the signal train 0.1.0, -1, . . . . In this way, multipliers, which are relatively expensive at high clock frequencies, are omitted. Acyclic filter 9
Examples for numbers 3 to 96 will be described later.

Using a somewhat different form of sampling, filter 73
and 74 to filters 93 and 94 can be completely omitted. In this case, two AD converters are required which are operated at 174 of the sampling frequency of AD converter 88 (fA2=fA/4) and whose sampling is offset by T2/4. A block circuit diagram of an embodiment based on this principle is shown in FIG. The output signal of the intermediate frequency amplifier is led on the one hand to an AD converter 1 and on the other hand to an AD converter 2. Sampling by AD converter 1 is performed with a phase shift of T2/4 compared to AD converter 2.

A low-pass filter 3, which is also designed as an acyclic filter, is connected downstream of the AD converter 1.

The output signal of the low-pass filter 3 is subsampled by the switch 5, the sampling frequency being reduced to 1/4. A delay circuit 7 is connected downstream of the switch 5, and the output side of the delay circuit is led to the input side - of the multiplier 9. A low-pass filter 4 is connected downstream of the AD converter 2 , and the output signal of the filter is read out by a switch 6 . The output signal of switch 6 samples the signal of low-pass filter 4 with a sampling rate reduced by a factor of 4. Switch 5 and switch 6 are operated by the same sampling frequency. The output side of the switch 6 is led on the one hand to the input side of the multiplier 9 and on the other hand to the delay circuit 8. The output side of the delay circuit is a multiplier 10.
The input 1111IVC of is led.

The output side of the switch 5 is connected to the other input side of the multiplier 10. The output signal of the multiplier 10 is sent to the subtraction circuit 11
It is subtracted from the output signal of multiplier 9 at . The output side of the subtracter 11 is shown on the arc-si'n table.

Due to the relative time offset of T/4 in the sampling of the AD converter, the output signals are no longer exactly Hilbert-transformed of each other. This can be compensated for in the downstream low-pass filter 3 or 4. This does lead to a loss of coefficient symmetry at least in one of these two high-order filters, which results in considerable extra costs in the construction of the filter's circuitry. The error caused by staggered sampling is
It can be easily compensated for by linear interpolation.

By omitting one of the low-pass filters, the sampling frequency for the AD converter can be selected to be, for example, 2.14 MHz under the conditions given to the intermediate frequency stage in very short wave radio reception. This sampling provides direct mixing to baseband. The sampling frequency fA2 is
It must be wider than the bandwidth of the upstream analog bandpass filter, and the ratio of intermediate frequency and sampling frequency must be an integer.

If you select an integer of 5, then 2.2 for the sampling frequency fA2.
A frequency of 14 Mn2 occurs. Switches 5 and 6 advantageously sample by 1/4 of the frequency of the AD converter. Therefore, the number of sampled layers is 535 Mn2.

FIG. 9 shows a detailed block diagram of components making up the demodulator of FIG. 8. In this case, to compensate for the temporally offset sampling, a linear interpolation method is used, and for the compensation of the amplitude, the square of the Hilbert-transformed signal is applied. The analog output signal of the intermediate frequency filter is supplied to an AD converter 20 and an AD converter 21. The output signal of the AD converter 20 reaches on the one hand a delay circuit 23 which is configured as a group of flip-flops. On the other hand, the output signal of the AD converter 20 is sent to the adder 25 and the left direction -1-
The signal is supplied to the pit-shifter 24. This corresponds to a multiplication of the digital word by two. The output of the 1-pit shifter 24 is fed to another input of an adder 25. The output side of adder 25 and the output side of delay circuit 23 are each led to the input side of adder 26. A right shifter 27 is connected to the output side of the adder 26. Via this shifter it is shifted to the right by 2 pits, which corresponds to a multiplication of the digital word by 1/4. The input side of an acyclic filter 28 is connected to the shifter 27 . The output side of the acyclic filter 28 is a squarer 30
The output side of the squarer is also connected to the input side of the adder 32. The output of adder 32 is led to the FROM 330 input. FROM
Output side of 33 and acyclic type, output 1 of filter 28
1 are connected to the input side of the multiplier 340, respectively. The output side of the multiplier 34 is led to a delay circuit 36, and the output side of the delay circuit is also led to the input side of the multiplier 3B.

The output signal of the AD converter 21 is led to the input side of an acyclic filter 29, the output side of which is connected on the one hand to a squarer 31 and on the other hand to the input side of a multiplier 350. The output side of the squarer 31 is an adder 3
2 separate inputs. The output side of FROM 33 is also connected to the input side of multiplier 350.

The output signal of multiplier 35 is led on the one hand to the input side of multiplier 38 and on the other hand to the input side of multiplier 39 via delay circuit 37 . Another input of multiplier 39 is connected to the output of multiplier 34 . The outputs of multipliers 38 and 39 are led to subtractor 40. The output of the subtracter 40 is connected to a ROM 41 storing an arc-sin table. arc,
At the output side of the -5in table stage 41, the demodulated digital signal can be taken out.

Clock generator 42 oscillates at four times the maximum sampling frequency. The output signal of the clock generator 42 is passed through the frequency divider 43
The frequency divider provides two output signals offset by T2/4.

The AD converter 21 is clock-controlled by one output signal, and the AD converter 20 is clock-controlled by the other output signal. This clock pulse is further supplied to the transfer inputs of delay circuit 23 and acyclic filters 28 and 29. Furthermore, a frequency divider 44 is connected to the frequency divider 43, and this divider also divides the frequency by 1/.

The output signal of the splitter 44 causes the acyclic filter 28 to
and 29 output clock signals, squarers 30 and 31
0 input and output registers and multipliers 34, 35, 3
8 and 39 and delay circuits 36 and 37 are clocked.

AD converters 20 and 21 convert the applied FM signals into digital words, with AD converter 21 converting the sampling to T/4.
Just shift it. Moreover, AD converters 20 and 21
The signals appearing at the outputs of are themselves mutually Hilbert-transformed, but with a time lag. This error can be compensated for by linear interpolation of the output signal of the AD converter 20 and a corresponding conversion.

This is done by multiplying the first prior value by 174 and adding to that value the real time value multiplied by 3/4. Multiplication is performed by shifts and additions formed by fixed wiring. Coefficient 6 is formed in adder 25 by first multiplying the real-time signal by 2 by a 1-bit left shift in shifter 24 and then adding it with the real-time signal in adder 25. The preceding signal appears at the output of the delay circuit 23. The output signal of adder 25 and the preceding value are added in adder 26 and the result is subsequently added in shifter 27 as
Bits multiplied by 1/4 by right shift. At this time, the output signal of the shifter 27 is subjected to Hilbert transformation with respect to the output signal of the AD converter 21, leaving a slight negligible level. The action of the acyclic filters 28 and 29 is as follows:
As already explained in detail.

It has already been explained that it is desirable to perform amplitude correction for high-speed amplitude noise. For this purpose, an acyclic filter 28
and 29 are squared in squarers 30 and 31 and the results are added in adder 32. The result is a squared value of the instantaneous amplitude. Normalized to 1 -
If we want to obtain a signal that is equal to or less than 100%, the output signal of the filter must be multiplied by the inverse of its amplitude. For this purpose, the function 1/4 is stored in the FROM 33, where X is the input value of the FROM and is therefore in this case the squared amplitude value. FROM 33 output value,
That is, the filter output value is multiplied in multipliers 34 and 35 by the reciprocal value of the amplitude. In this way 1
A Hilbert-transformed signal pair is obtained. In order to obtain a unique valid signal, the first preceding value is multiplied by the Hilbert transformed value in multipliers 38 to 39 and the results of multipliers 38 and 39 are added to adder 4.
Added at 0. Comparison with the arc-sin table stored in ROM 41 yields a demodulated digital useful signal. For subsequent processing, a suitable low-pass filter to limit the noise and the DA
The converter can be supplied to an analog signal amplifier.

However, digital recording or further processing, for example digital stereo decoding of the received signals, is also possible.

Subsequent processing takes place analogously to digital records.

When demodulating intermediate frequency signals in very high frequency radio reception, A
A frequency of 2-14 MHz is suitable as a sampling frequency for the D converter. Acyclic filters 28 and 29
．． , the subsequent processing of the signal appearing at 535 KHz is performed. Squarers 30 and 31, multiplier 34
and 35° 38 and 39 and adders 32 and 4
For example, 0 is the product model name of TRY company TDOi Q 1Q
It can be realized with a commercially available multiplier-accumulator, such as that provided by J. J., with an additional instantaneous memory being required.

The circuit arrangement for generating a clock signal shifted by T/4 can be seen from FIG. The output of clock generator 42 is connected to the input of 2-bit binary counter 460 as well as to A
It is guided to the input side of each of ND elements 49 and 50. A first output of the binary counter is led to the respective inputs of a NOR element 47 and an AND element 48. A second output of the binary counter is led to a further input of the NOR element 47. The inverting output of the binary counter 46 is connected to another input of an AND element 48 . NO
The output side of R element 47 is led to the second input side of AND element 49 , and the output side of AND element 48 is led to the second input side of AND element 50 . The output side of the AND element 49 is connected to the clock input side of the AD converter 21, and the output side of the AND element 50 is connected to the clock input side of the AD converter 21.
The clock input side of is connected.

10. The operation of the circuit device shown in FIG. 10 will be explained in detail based on the diagram shown in FIG. 11. The clock signal of the clock generator 42 supplied to the input side of the frequency divider is shown in FIG.
Illustrated in. By means of a binary counter with logical dates, the signal of FIG. 11 appears at the output of AND element 49, and the signal of FIG. 11C appears at the output of AND element 50. The pulses in Figures 11 and 11C,
It is off by T/4. A pulse is generated by every fourth clock pulse of pulse generator 42. 2.
In order to obtain a clock frequency of 14 MHz, it is necessary to operate the clock generator with a frequency of EL56 MHz.

FIG. 12 shows an acyclic filter such as is used, for example, in the block circuit diagrams described so far.

The input signal reaches a four stage shift register 105, with each shift register location connected to a RAM 106.

The shift register is clocked by an input clock TE. RAM 106 has two outputs which are led to adder 109. Adder 10
The output side of 9 is led to the input side of multiplier 1100.

The output of another RAM 108 is connected to another input of a multiplier 110. RAMs 106 and 108 are
Controlled by FROM107. The output of the multiplier 110 is an adder 111 connected as an accumulator.
The output side of the adder is connected to an output switch or register 112. An output signal is available at the output side of this switch. Output switch 112 is clocked by clock TA.

A digital acyclic filter essentially has the following characteristics. That is, the real-time value as well as the preceding value are multiplied by a predetermined coefficient, the coefficient value being determined by the desired properties of the filter. These multiplied values are summed and taken at the output of the filter. Acyclic filters can be constructed in linear phase, so that the coefficients are mirror-symmetrically equal to each other. This has the advantage that the number of time-consuming multiplications is halved. For an 18th order filter, for example, 19 multiplications are required. For linear phase filters, the number of multiplications is reduced to 10. However, for this purpose, the stored state changes must be added to the can beforehand. In addition, special sampling reduction occurs in the acyclic filter shown in FIG. With the clock pulses of clock TE, the values present at the respective inputs of shift register 105 are transferred in the shift register and the preceding value is further shifted by one. Since four values have been written, the entire contents of shift register 105 are transferred to RAM 106 and the four stored values are transferred to RAM 106.
1Q 5 are written to four predetermined memory locations. Four further values are then written to shift register 105 and these are also stored in other memory locations in RAM1Q6. The values already previously written and stored corresponding to the number of coefficients in RAM 1Q 5 are stored in FROM 1Q
7 and as a result is sent to the output of the RAM 106 one after the other, in each case the first value and the last value, the second value and the penultimate value, and so on. and are added in adder 109. At the same time, RAM i Q 8 via FROM 107
, the corresponding coefficients are called and the first
and the last value are multiplied in multiplier 110 and multiplied by the penultimate value and the second value. The results of multiplier 110 are summed in accumulator 111. Since the two state changes are pre-added in adder 109, the number of multiplications in multiplier 110 is reduced. If you should not change the filter coefficients,
The coefficients can also be stored in FROM 107.

However, if the coefficients are to be changed, ie the characteristics of the filter are to be changed depending on the received signal, for example, it is advantageous to store the coefficients in a RAM, since their values can be changed in the RAM. The summed value is written in output register 112 where it is retrieved during the sampling clock period for subsequent processing.

The addition of the second state change and the multiplication with the coefficient are carried out each time as soon as the new value is transferred to the RAM 106 by the shift register 105, so that a new output value can be determined after each transfer. Sampling is reduced by carrying out the transfer of all values written to shift register 105 only according to the respective fourth value present at the input of shift register 105. The sampling reduction factor therefore determines the length of shift register 105. The demands on multipliers and adders are significantly higher.

For an 18th order filter, 100 multiplications and additions are performed per clock unit. A 68th order filter performs 20 multiplications and additions per clock unit. Furthermore, shift register 105 and RAM 106 and 10
It is also taken into account that the calculation modules 109 to 111 have to be configured corresponding to the length of the data word, for example for 8 bits on the input side and 16 bits on the output side. Depending on the required precision, the number of bits per word can be increased. This is because relatively high binary numbers can be used during multiplication.

For example, to configure the demodulator shown in FIG.
In addition to the 5in conversion, two multiplications, one addition, and two registers are required as delay circuits. Furthermore, as described above, some calculations are required for amplitude adjustment. Two squares, one addition, a table to form 1/β, then two further multiplications to correct the AM-noise impaired signal. The sequence of necessary arithmetic operations is advantageously carried out in the document 1 Multi-Silier Accumulator, TRY -
be Products, TRW Engineering, Inc., 1979. Therefore, in FIG. The calculation unit of the configuration is shown. The internal registers of this module are not sufficient to perform all the necessary temporary storage functions, so separate external registers are required. Then the calculation of the instantaneous amplitude and the arc-5iri Two FROM modules are additionally connected for the conversion.

On the input side of the circuit arrangement there are two registers 115 and 11.
6 is connected. In these registers, filter output signals, for example the output signals of filters 28 and 29 in FIG. 9, are taken out. The outputs of registers 115 and 116 are led to data bus 117. Data bus 117 includes registers 118, 126, 127 and 1
23 are connected. The outputs of registers 118 and 126 are led to path 119. register 127
The output side of is connected to FROM 1 'l 8 for plate formation. The output side of register 123 is connected to data bus 129. Multiplier-accumulator 120 is
It has two input registers 121 and 122, one register being connected to path 119 and the other register being connected to path 129. The outputs of the two registers are led to a multiplier 124. The output signal of multiplier 124 is directed to accumulator register 125. The output of the multiplier-accumulator is also connected to the data bus 117, to which an output register 132 is also connected. A FROM 133 having an arc-8]T1 table is connected downstream to the output register 132. F.R.O.
M 133 is followed by an output register 134 in which the demodulated digital signal can be extracted. An analog output signal can also be taken out via the DA converter 135.

The stored values in input registers 115 and 116 are such that the contents of register 115 reach MAO's input register 121 via register 118, and at the same time also register 12.3.
is first squared for amplitude correction. Multiplier 124
After the multiplication in , the corresponding thing is done on the signal in register 116 . After the accumulation step, the squared sum value appears in the accumulation register 12.5, from where it reaches FROM 12'8 via register 127, in which the root of the equation is formed. In this way 1. The calculated amplitude correction coefficient is sent to the MAQ register 12 via the data bus 129.
Reach 2. The input values at registers 115 and 116 are then passed sequentially through register 118 to MAC!
120 input register 121, multiplied and thereby normalized to one. The normalized signal in accumulator register 125 is sequentially transferred to registers 118 and 1.
26. This ends the amplitude -1 adjustment and the original demodulation continues.

Furthermore, the signal values written in registers 130 and 131 in the previous calculation cycle are stored in registers 118 and 1.
26 and both products are subtracted in an accumulator. The result is transferred via register 132 to FROM 13 which performs arc-sin equalization.
Appears at address 3. arc -5in- table shows maximum control at a deviation of 100KH2, i.e. amplitude 1
is constructed so that it occurs on the output side. This completes the demodulation cycle. The obtained FM signal can be subsequently processed digitally or output in analog form via the DA converter 135. Before a new cycle begins, the contents of memories 118 and 126 are stored in register 1.
30 and 131.

The sequence described so far requires a total of 16 clock cycles. That is, using the above example, 1
．． 116 ns are used for each basic operation in a total time of 87 μs. It must be noted that since the typical multiplication time of an instantaneously available multiplier-accumulator is 150 ns, two elementary cycles are used for each of the six multiplication processes.

Sequence control of the calculations is carried out by a control FROM, not shown, which is addressed by a 4-bit counter with a clock frequency of 8-65 MHz. Control signals are transferred to the calculation unit via pipeline registers, not shown.

The entire demodulator can advantageously be manufactured as an integrated circuit.

All memory units and computing units can be housed on one chip. Since the characteristics of the demodulator are substantially determined by the filter characteristics, the RAM
By simple modification of the coefficients in 108 to FROM IQ 7, the characteristics of the demodulator can be changed to adapt it to different applications. The sampling frequency is also the same (chosen depending on the application. The sampling frequency can be selected accordingly if the carrier frequency changes or if the analog prefilter bandwidth is different. The accuracy of the demodulator is essentially It depends essentially on the number of bits of the word and the number of pits of its subsequent processing, which allows the precision to be varied arbitrarily.

[Brief explanation of drawings]

1 is a block circuit diagram of a digital FM-demodulator, FIG. 2 is a detailed block circuit diagram of the digital FM-mill shown in FIG. 1, and FIGS. 6a-c show various types of the demodulator shown in FIG. waveform diagrams showing the course of the signal spectrum at different points,
FIG. 4 is a waveform diagram showing an example of a digital output signal generated on the output side of the AD converter of the demodulator shown in FIG. 2, and FIG. FIGS. 6a to 6c are waveform diagrams of the various digital output signals appearing at the output of the subtracter of the demodulator of FIG. 2, and FIG. 7 is a diagram of the waveforms of the resulting signals, respectively. FIG. 8 is a block circuit diagram showing a specific embodiment of the invention. The block circuit diagram of another variant embodiment of the demodulator, FIG.
Block circuit diagram of a detailed embodiment of the demodulator of FIG.
0 is a detailed diagram of the demodulator circuit portion (frequency divider 43) in FIG. 9, FIGS. 11a to 11C are pulse waveform diagrams for explaining the functions of the circuit in FIG. 10, and FIG. , a block circuit diagram showing one embodiment of the circuit configuration of an acyclic filter for a digital demodulator. FIG. 16 is a block circuit diagram of another embodiment for configuring a demodulator.

Claims (1)

[Claims] 1. The F'M signal in digital form is in each case fed to at least one acyclic filter (3, 4), the sampling rate of which at the output side is equal to the sampling rate at the input side of the filter. speed, and the acyclic filter (3
, 4) are at least approximately Hilbert-transformed and each fed to a delay circuit (γ, 8), and the delayed signal in each case is multiplied by the Hilbert-transformed signal and the two multiplied signals are Demodulator of Il'M signals in digital form, characterized in that a difference is formed. 2. An arc-sin converter (
12) is downstream connected. 3. Demodulator according to claim 1, in which the sampling for both filters (3, 4) is carried out offset and thereby also approximately a Hilbert transform is carried out by subsequent interpolation. 4. A demodulator according to claim 6, wherein the interpolation is performed by shifting in shifters (24, 27) and forming an average value with the first preceding value. 5. Amplitude adjustment section in acyclic filter (28, 29)...
5. A demodulator as claimed in claim 4, in which the demodulator is downstream connected. 6. The output signals of the acyclic filters (28, 29) are squared and summed, and the signal -1: or its function is multiplied with the output signal of the acyclic filters (28, 29) for normalization. A demodulator according to claim 5. 2 AD converter (1,2゜20.21
) is pre-connected. 8. Demodulator according to claim 7, characterized in that a bandpass filter is pre-connected to the AI) converter. 9. The FM signal in digital form is multiplied by the si, n and cos functions and respectively supplied to at least digital acyclic filters (58, 59), and the output signals of the filters are mutually Hilbert transformed and each delayed and Demodulation of the FM signal in digital form, characterized in that the delayed signal is multiplied with the respective Hilbert-modified signal at the output of the filter (58, 59) and the difference of the two multiplied signals is formed. vessel. 10. Demodulator according to claim 9, in which the difference former (64) is followed by an arc-5in converter (65). 11. A demodulator as claimed in claim 9, in which separate digital acyclic filters are provided. 12. The demodulator according to claim 9, wherein the sampling of the multipliers (56, 57, 71, 72) is performed at zero passing points and maximum values of the sin to cos functions, respectively. 13. Sin-cos-multiplication is performed using fixed value memory (
89°90) Claim 12
Demodulator as described in section. 14. A demodulator according to claim 9, wherein the sampling rate at the output side of the acyclic filter is lower than the signal repetition rate at the input side of the filter. 15. The acyclic filter is composed of a shift register (105), and the signal sequence of the acyclic filter is memo! stored as a state change in J (106),
Demodulator according to claim 9, in which the state change is multiplied by a coefficient determining the characteristics of the filter stored in a separate memory (108) and the result is added in an accumulator (111). . 16. A demodulator as claimed in claim 15, in which state changes to be multiplied by the same coefficient are called up simultaneously, summed and then multiplied. 1z The shift register (105) has at least a number of locations corresponding to the sampling reduction.
Demodulator as described in section. 18. Filter! 16. A demodulator according to claim 15, wherein the coefficient determining the quality can be varied, for example, depending on the reception strength or manually. 19. The demodulator according to claim 9, wherein an equalization filter having a slowly increasing characteristic is connected downstream of the demodulator, and the characteristic decreases when the cutoff frequency of the transmission signal is exceeded. 20, AD converter (55, 70yJf) on the input side of the demodulator
10. A demodulator according to claim 9, which is pre-connected. 21. The demodulator according to claim 20, wherein a bandpass filter is pre-connected to the AD converter.