JPS6376456A - Semiconductor device using copper electrode - Google Patents

Semiconductor device using copper electrode

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Publication number
JPS6376456A
JPS6376456A JP61219550A JP21955086A JPS6376456A JP S6376456 A JPS6376456 A JP S6376456A JP 61219550 A JP61219550 A JP 61219550A JP 21955086 A JP21955086 A JP 21955086A JP S6376456 A JPS6376456 A JP S6376456A
Authority
JP
Japan
Prior art keywords
copper
film
electrode
type
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61219550A
Other languages
Japanese (ja)
Inventor
Isao Yoshida
功 吉田
Masatoshi Morikawa
正敏 森川
Hiroshi Miyazaki
博史 宮崎
Yuzuru Oji
譲 大路
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61219550A priority Critical patent/JPS6376456A/en
Publication of JPS6376456A publication Critical patent/JPS6376456A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0554—External layer
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
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    • H01L2924/01—Chemical elements
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    • H01L2924/01022—Titanium [Ti]
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    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To assure sufficient reliability upon structure while increasing the current capacity of semiconductor element preventing the wiring resistance from reducing as well as the electromigration from occurring by a method wherein a copper electrode is used as a wiring material for a power MOSFET, etc. CONSTITUTION:Copper electrode is used as a wiring material for an insulating gate type power field effect transistor and an integrated circuit device including the FET. This wiring comprising copper is to be completely covered with, e.g., another metal or a semiconductor or an insulating layer. An N channel type power MOSFET is composed of, e.g., an N type high concentration substrate 1, and N type low concentration epitaxial layer 2, a P type pace region 3, an N type high concentration source region 4, a gate oxide film 5, a gate electrode 6 comprising a polycrystalline silicon film, a stabilized protective film 7, a source electrode 8 comprising a copper film, a Ti film 8' as a barrier metal, a drain electrode 9 comprising a metallic film, a resin based insulating film 10, etc.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の構造に係り、特に大電流を扱うの
に好適な銅電極を用いた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor device, and particularly to a semiconductor device using copper electrodes suitable for handling large currents.

〔従来の技術〕[Conventional technology]

一般に半導体装置の配線材料としては、主としてアルミ
ニウムが用いられている。縦形構造を有するパワーＭＯ
８士’ｆＥＴのｊＩｈ台にも１％公昭６０−４１８７６
号に記載のよりに、半導体表面に位置するソース電極材
料としてはアルミニウムが用いられていた。一方、％開
昭５６−１１４３５８号に記載のように銅が配線材料と
して半導体装置に用いられた例はあるが、大電流を扱う
パワーＭＯ８ＦＥＴのソース電極に鋼が用いられた例は
なかった。Generally, aluminum is mainly used as a wiring material for semiconductor devices. Power MO with vertical structure
1% Kosho 60-41876 for the jIh level of 8th Shi'fET
As described in the above issue, aluminum was used as the source electrode material located on the semiconductor surface. On the other hand, although there are examples of copper being used as a wiring material in semiconductor devices as described in % Japanese Patent Publication No. 56-114358, there have been no examples of steel being used for the source electrode of power MO8FETs that handle large currents.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術は、配線電画としてアルミニウムが用いら
れているが、例えば大゛成流を扱うパワーＭＯ，１ＦＥ
Ｔの場合には、その配ａ抵抗やアルミニウム膜中で生ず
るエレクトロマイグレーションが素子の域流容量を制限
するなどの問題があった。In the above conventional technology, aluminum is used as the wiring pattern, but for example, power MO, 1FE, which handles large currents, etc.
In the case of T, there are problems such as the resistance of its aluminium and electromigration occurring in the aluminum film, which limits the current capacity of the element.

本発明の目的は、配線抵抗の低減やエレクトロマイグレ
ーションの防止などにより、半導体素子の電流容量分増
大することにある。また、電気的特性の向上だけでなく
、信頼性に１関しても十分な構造を提供することが１本
発明の目的である。An object of the present invention is to increase the current capacity of a semiconductor element by reducing wiring resistance and preventing electromigration. Another object of the present invention is to provide a structure that not only improves electrical characteristics but also has sufficient reliability.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

上記目的は、配線を極材料であるアルミニウムを鋼に替
えることにより、まず達成される。そして、銅電極が酸
化しやすいという信頼性の問題に対して、その銅を大気
中に露出させない構造、すなわち、その銅を他の金属も
しくは絶縁物で覆うことにより解決を図っている。The above objective is first achieved by replacing the pole material of aluminum with steel for wiring. The reliability problem of copper electrodes being easily oxidized has been solved by a structure that does not expose the copper to the atmosphere, that is, by covering the copper with another metal or an insulator.

〔作用〕[Effect]

鋼を配線に用いた電極は、従来のアルミニ９ム電極に較
べて、抵抗が小さく、大電流動作時に生ずるエレクトロ
マイグレーションの発生も少ない。Electrodes using steel for wiring have lower resistance than conventional aluminum 9mm electrodes, and less electromigration occurs during high current operation.

また、その銅電極は、他の金属もしくは絶縁物で完全に
覆われているので、酸化などによる特性の劣化が生じな
い。したがって、本発明の銅電極を用いたパワーＭＯ８
ＰＥＴは、高性能化および高信頼化される。Further, since the copper electrode is completely covered with another metal or an insulator, its characteristics do not deteriorate due to oxidation or the like. Therefore, the power MO8 using the copper electrode of the present invention
PET is becoming more sophisticated and reliable.

〔実施例〕〔Example〕

以下１本発明の一実施例を第１図により説明する。第１
図は、ｎチャネル形パワーＭＯ８ＦＥＴの主要部セル部
の断面構造図である。１は抵抗率が０．０１９・個のｎ
形高濃度基板、２は抵抗率が０．５Ω・国、厚さが５μ
ｍ　（Ｄ　ｎ形低濃度エピタキシャル層、３はシート抵
抗が７００め勺、深さが１．５μｍのｐ形ベース領域、
４はシート抵抗が３０Ω／口、深さが０，５μｍのｎ層
高濃度ソース領域、５は厚さが５０μｍのゲート酸化膜
、６は厚さが０，３μｍの多結晶シリコン膜によるゲー
ト電極、７は厚さが０．６μｍの安定化保護膜、８は厚
さが３μｍの銅膜によるソース電極、また８′はバリア
メタルとしてのｒ１膜、９は厚さが２μｍ金属膜による
ドレイン電極、そして１０が樹脂系絶縁膜である。本構
造の特徴は、ソース電極の材質が銅であること、そして
、その銅が外部雰囲気にさらされないように他の金属も
しくは絶縁膜で覆われていることである。An embodiment of the present invention will be described below with reference to FIG. 1st
The figure is a cross-sectional structural diagram of the main cell portion of an n-channel power MO8FET. 1 has a resistivity of 0.019・n
Highly concentrated substrate, 2 has a resistivity of 0.5Ω, and a thickness of 5μ.
m (D n-type low concentration epitaxial layer, 3 is a p-type base region with a sheet resistance of 700 mm and a depth of 1.5 μm,
4 is an n-layer high concentration source region with a sheet resistance of 30 Ω/gate and a depth of 0.5 μm, 5 is a gate oxide film with a thickness of 50 μm, and 6 is a gate electrode made of a polycrystalline silicon film with a thickness of 0.3 μm. , 7 is a stabilizing protective film with a thickness of 0.6 μm, 8 is a source electrode made of a copper film with a thickness of 3 μm, 8′ is an R1 film as a barrier metal, and 9 is a drain electrode made of a metal film with a thickness of 2 μm. , and 10 is a resin-based insulating film. The feature of this structure is that the material of the source electrode is copper, and that the copper is covered with another metal or an insulating film so as not to be exposed to the external atmosphere.

本実施例によれば、５寵角チツプのパワーＭＯ８ＦＥＴ
のオン抵抗が、１０ｍΩ、ドレイン耐圧が６０Ｖ得らｎ
た。このデバイスは、従来のアルミニ９ム電極によるパ
ワーＭＯ８ＦＥＴに比べて。According to this embodiment, the power MO8FET of 5-angle chips
The on-resistance is 10 mΩ, and the drain breakdown voltage is 60 V.
Ta. This device is compared to a power MO8FET with a conventional aluminum 9M electrode.

オン抵抗が約１０チ改善でき、また、大電流動作時のエ
レクトロマイグレーションの発生が格段に減少した。The on-resistance was improved by about 10 inches, and the occurrence of electromigration during high current operation was significantly reduced.

次に１本発明の他の実施例を第２図により説明する。第
２図は、パワーＭＯｄＦＥＴの断面構造図で、能動領域
上にポンディグを行ったものである。Next, another embodiment of the present invention will be described with reference to FIG. FIG. 2 is a cross-sectional structural diagram of a power MOdFET, in which ponding is performed on the active region.

８のソースｓｅｔ極上に、１１のアルミニウム［−重ね
ているのが特徴である。そして、１２のアルミニウムワ
イヤが取出し電極としてボンディングされている。この
構造に２いても銅電極は、他の金属もしくは絶縁膜で完
全に覆われている。そのため、鋼の酸化による特性劣化
など信頼性の上での問題も生じない。It is characterized by layering aluminum layer 11 on top of source set 8. Twelve aluminum wires are bonded as extraction electrodes. Even in this structure, the copper electrode is completely covered with another metal or an insulating film. Therefore, reliability problems such as deterioration of characteristics due to oxidation of the steel do not occur.

次に１本発明の他の実施例を＠３因により説明する。第
３図（ａ）は、３Ωｍ角パワーＭＯ８ＰＥＴの平面図、
（ｂ）は七〇Ａ−Ａ’線上の断面構造図である。Next, another embodiment of the present invention will be explained using @3 causes. FIG. 3(a) is a plan view of a 3Ωm square power MO8PET,
(b) is a cross-sectional structural diagram taken along line 70A-A'.

１３がパワーん１０　Ｓ　Ｆ　ｇＴのチップ、１４が銅
を用いたソース電極、１５がゲート電極、１６がンース
ボンデイングバット部、１７がゲートポンディングパッ
ド部である。この構造においても、大電流を扱う銅電極
は、大気中に露出しない構造となっており高信頼性を有
する。また、銅が直接シリコン基板に被着されている構
造をゼしているため、高温の熱処理によって、銅が／リ
コン中に拡散する。でして、この鋼がライフタイムキラ
ーとして動作する。このライムタイムキラーは、パワー
ＭＯ８ｉ’ＥＴのドレイン−基板間に存在するダイオー
ドの逆回復時間を著しく減少させる。本実施例によれば
、逆回復時間が、熱処理前の０．８μｓから０．２μｓ
と約１／４に減少したつこの結果、低損失で高速、かつ
高信頼性？有するパワーＭＯ８１ｉ’ｇＴが裏作できた
。Reference numeral 13 designates a power 10 SF gT chip, 14 a source electrode using copper, 15 a gate electrode, 16 a ground bonding butt portion, and 17 a gate bonding pad portion. Even in this structure, the copper electrode that handles a large current is not exposed to the atmosphere and has high reliability. Furthermore, since the structure is such that copper is directly deposited on the silicon substrate, copper diffuses into the silicon by high-temperature heat treatment. So this steel works as a lifetime killer. This time killer significantly reduces the reverse recovery time of the diode present between the drain and substrate of the power MO8i'ET. According to this example, the reverse recovery time is 0.2 μs from 0.8 μs before heat treatment.
The result is low loss, high speed, and high reliability. I was able to produce the power MO81i'gT.

次に１本発明の他の実施例を第４図により説明する。第
４図は、制御用論理回路や保護回路などの小信号回路と
集積しやすいパワーＭＯｄｉ’ＥＴの主要部の断面構造
図である。１８は低濃度ｐ形半導体基板、１９がｎ形低
濃度ドレイン領域、２０が高濃度ｐ＃埋込み層、２１が
ｐ形ベース層。Next, another embodiment of the present invention will be described with reference to FIG. FIG. 4 is a cross-sectional structural diagram of the main parts of a power MODi'ET that is easy to integrate with small signal circuits such as control logic circuits and protection circuits. 18 is a lightly doped p-type semiconductor substrate, 19 is an n-type lightly doped drain region, 20 is a heavily doped p# buried layer, and 21 is a p-type base layer.

２２が高濃度ｎ形ソース領域、２３が高濃度ｎ形ドレイ
ン煩域、２４がゲ・−１・酸化膜、２５が多結晶シリコ
ンのゲート電極、２６がリンガラス膜、２７．２８がそ
れぞれ鋼のンース、ドレイン電極でのる。２９が保護用
絶縁膜である。このように集積化に適する横形構造のパ
ワーＭＯ８ＦＥＴにおいても、ｊｌｊｌ電極を用いるこ
とにより、オン抵抗の５ｆｂの低減と高信頼性化が達成
された。22 is a high concentration n-type source region, 23 is a high concentration n-type drain region, 24 is a Ga-1 oxide film, 25 is a polycrystalline silicon gate electrode, 26 is a phosphorus glass film, and 27 and 28 are steel, respectively. The source and drain electrodes are connected. 29 is a protective insulating film. In this way, even in the power MO8FET with a horizontal structure suitable for integration, by using the jljl electrode, a reduction of 5fb in on-resistance and high reliability were achieved.

以上の実施例では、銅電極を用いる場合、シリコン基板
との接着に際し、他の金属をはさまないで直接被着した
が、接着性を改善する手法としてクロムやチタン、チタ
ンナイトライドなどの金属金はさむ構造についても実施
した。In the above examples, when using a copper electrode, it was directly attached to the silicon substrate without sandwiching other metals. Tests were also carried out on the gold sandwiched structure.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、従来のアルミニクム戒極の場合に比較
して、配線抵抗が約５０％低減できると共に大電流動作
時に生ずるエレクトロマイグレーションの発生が約１桁
低減できるので、パワーＭＯ８ＦＥＴの高性能化、高信
頼化に大きな効果がめる。According to the present invention, the wiring resistance can be reduced by about 50% compared to the case of conventional aluminum conductors, and the occurrence of electromigration that occurs during high current operation can be reduced by about one order of magnitude, thereby improving the performance of power MO8FETs. , which has a great effect on improving reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は不発明の一実施例の断面構造図、第２図は本発
明の他の実施例の断面構造図、第３図は本発明の他の実
施例で、（ａ功：平面図、（ｂ）が（４のＡＡＺ線断面
構造図、第４図は１本発明の他の実施例の断面構造図で
ある。 ｌ・・・高濃度半導体基板、２・・・低濃度ｎ形ドレイ
ン領域、３・・・ｐ形ベース領域、４・・・ｎ形ソース
領域。 ５・・・ゲート酸化膜、６・・・ゲート屯極、７・・・
安定化保護膜、８，２７．２８・・・＠電極、ｌＯ・・
−絶縁膜。 １４・・・鋼のンースを極、１５・・・ゲート取り出し
電ｆｆ１．１６．１７・・・ポンディングパッド部。　
　　　７−０２１、妬１図 ２〜竹ｔ１トレイン４１域 ｔ　　　＋Ｔ゛−１シ極 ７　　ｆ！定ダイ８盲１１ ＃　側電極 ｌＱ　　Ｃ色豪衾用（ 第　２　図 ２　＠電４セ ／／　　了ルミニウム ／Ｚ　　禾ね電極 第　３　図 （（Ｌ） １７　　ヶ′−）オＣ；ｆ″４−りξｐＹ　４　図 ／８イＣ（１彦−１４型１儲ネ及 ｚｔ　　ｒｆｔｊへ゛−ス領域 ２７　　ンー又金目電才西 ２？　ｋ１イシ４月電不シFig. 1 is a sectional structural diagram of one embodiment of the invention, Fig. 2 is a sectional structural diagram of another embodiment of the invention, and Fig. 3 is a sectional structural diagram of another embodiment of the invention. , (b) is a cross-sectional structural diagram taken along the AAZ line of (4), and FIG. Drain region, 3... P-type base region, 4... N-type source region. 5... Gate oxide film, 6... Gate electrode, 7...
Stabilizing protective film, 8, 27. 28...@electrode, lO...
-Insulating film. 14... Steel base as a pole, 15... Gate extraction voltage ff1.16.17... Bonding pad part.
7-021, envy 1 figure 2 ~ bamboo t1 train 41 area t +T゛-1 sea pole 7 f! Constant die 8 blind 11 # side electrode lQ C color rich (Fig. 2 Fig. 2 @electronic 4th// completed luminium/Z wire electrode Fig. 3 ((L) 17 months'-) OC; f″4 -ri ξpY 4 Figure/8iC (1hiko-14 type 1 profit and zt rftj space area 27 N-Matakinme Denzai Nishi 2? k1 Ishi April Denfusi

Claims (1)

【特許請求の範囲】 １、電力用絶縁ゲート形電界効果トランジスタおよびそ
れを含む集積回路装置において、配線材料として銅電極
を用いた半導体装置。 ２、特許請求の範囲第１項において、上記銅からなる配
線が他の金属又は半導体もしくは絶縁膜で完全に覆われ
ていることを特徴とする銅電極を用いた半導体装置。 ３、特許請求の範囲第１項において、銅電極の一部が半
導体基板に接着していることを特徴とする銅電極を用い
た半導体装置。 ４、特許請求の範囲第１項において、銅電極より銅を半
導体基板中に拡散し、その銅をライフタイムキラーとし
て利用したことを特徴とする銅電極を用いた半導体装置
。[Claims] 1. A semiconductor device using a copper electrode as a wiring material in a power insulated gate field effect transistor and an integrated circuit device including the same. 2. A semiconductor device using a copper electrode according to claim 1, wherein the wiring made of copper is completely covered with another metal, a semiconductor, or an insulating film. 3. A semiconductor device using a copper electrode according to claim 1, characterized in that a part of the copper electrode is adhered to a semiconductor substrate. 4. A semiconductor device using a copper electrode according to claim 1, characterized in that copper is diffused into the semiconductor substrate from the copper electrode and the copper is used as a lifetime killer.
JP61219550A 1986-09-19 1986-09-19 Semiconductor device using copper electrode Pending JPS6376456A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61219550A JPS6376456A (en) 1986-09-19 1986-09-19 Semiconductor device using copper electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61219550A JPS6376456A (en) 1986-09-19 1986-09-19 Semiconductor device using copper electrode

Publications (1)

Publication Number Publication Date
JPS6376456A true JPS6376456A (en) 1988-04-06

Family

ID=16737258

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61219550A Pending JPS6376456A (en) 1986-09-19 1986-09-19 Semiconductor device using copper electrode

Country Status (1)

Country Link
JP (1) JPS6376456A (en)

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Publication number Priority date Publication date Assignee Title
JPH0231448A (en) * 1988-07-20 1990-02-01 Toshiba Corp Manufacture of semiconductor device
EP0971418A3 (en) * 1998-06-30 2001-11-07 Harris Corporation Semiconductor device having reduced effective substrate resistivity and associated methods
JP2004079988A (en) * 2002-06-19 2004-03-11 Toshiba Corp Semiconductor device
JP2006005325A (en) * 2004-05-20 2006-01-05 Denso Corp Power composite integrated semiconductor device and manufacturing method of the same
DE102004036142A1 (en) * 2004-07-26 2006-03-23 eupec Europäische Gesellschaft für Leistungshalbleiter mbH Semiconductor component, used in power semiconductor applications, comprises a semiconductor substrate having a metallization with a barrier layer arranged between metallization layers
WO2012169053A1 (en) * 2011-06-09 2012-12-13 トヨタ自動車株式会社 Semiconductor device and method for producing semiconductor device
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Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0231448A (en) * 1988-07-20 1990-02-01 Toshiba Corp Manufacture of semiconductor device
JPH077765B2 (en) * 1988-07-20 1995-01-30 株式会社東芝 Method for manufacturing semiconductor device
EP0971418A3 (en) * 1998-06-30 2001-11-07 Harris Corporation Semiconductor device having reduced effective substrate resistivity and associated methods
JP2004079988A (en) * 2002-06-19 2004-03-11 Toshiba Corp Semiconductor device
JP2006005325A (en) * 2004-05-20 2006-01-05 Denso Corp Power composite integrated semiconductor device and manufacturing method of the same
JP4696532B2 (en) * 2004-05-20 2011-06-08 株式会社デンソー Power composite integrated semiconductor device and manufacturing method thereof
DE102004036142B4 (en) * 2004-07-26 2009-04-09 Infineon Technologies Ag Semiconductor device having a metallization with a plurality of separated by at least one barrier layer metallization layers and method for its preparation
DE102004036142A1 (en) * 2004-07-26 2006-03-23 eupec Europäische Gesellschaft für Leistungshalbleiter mbH Semiconductor component, used in power semiconductor applications, comprises a semiconductor substrate having a metallization with a barrier layer arranged between metallization layers
WO2012169053A1 (en) * 2011-06-09 2012-12-13 トヨタ自動車株式会社 Semiconductor device and method for producing semiconductor device
JP5630579B2 (en) * 2011-06-09 2014-11-26 トヨタ自動車株式会社 Semiconductor device and manufacturing method of semiconductor device
US9064711B2 (en) 2011-06-09 2015-06-23 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method for fabricating semiconductor device
WO2017169086A1 (en) * 2016-03-30 2017-10-05 三菱電機株式会社 Semiconductor device, method for manufacturing same, and power conversion device
JP6253854B1 (en) * 2016-03-30 2017-12-27 三菱電機株式会社 Semiconductor device, method for manufacturing the same, and power conversion device
CN108886055A (en) * 2016-03-30 2018-11-23 三菱电机株式会社 Semiconductor device and its manufacturing method, power-converting device
US11158511B2 (en) 2016-03-30 2021-10-26 Mitsubishi Electric Corporation Semiconductor device and power converter including a copper film with a small grain size stress relaxtion layer

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