JPS6376321A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS6376321A
JPS6376321A JP22129486A JP22129486A JPS6376321A JP S6376321 A JPS6376321 A JP S6376321A JP 22129486 A JP22129486 A JP 22129486A JP 22129486 A JP22129486 A JP 22129486A JP S6376321 A JPS6376321 A JP S6376321A
Authority
JP
Japan
Prior art keywords
wafer
vacuum chamber
vacuum
nitrogen
target
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22129486A
Other languages
Japanese (ja)
Inventor
Fumisato Tamura
文識 田村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22129486A priority Critical patent/JPS6376321A/en
Publication of JPS6376321A publication Critical patent/JPS6376321A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To carry out an Al sputtering process and an Al deposition process by keeping the ratio of partial pressure of an undesirable gas component, such as nitrogen or the like, at an extremely low level in such a way that a metal material such as Ti, Ta, Zr, Nb, Mo, W, La or the like is sputter-etched. CONSTITUTION:While a wafer 3 is put on the side of a Ta target 6, a vacuum chamber 2 is evacuated by means of a cryopump 4 until, e.g., 4X10<-7> Torr can be reached. As soon as a prescribed degree of vacuum has been reached, an Ar gas of high purity is introduced into the vacuum chamber 2 through an Ar supply pipe 5, and the Ta target is sputter-etched by glow discharge. During this process Ta is not deposited because the wafer 3 is put at the position as shown in the figure. If, after completion of a Ta sputtering process, the Ar supply pipe 5 is closed, the degree of vacuum inside the vacuum chamber 2 reaches the level of 1X10<-7> within a few minutes. This occurs because the partial pressure of these gases is lowered due to the reaction of Ta with nitrogen and oxygen. Through this constitution, it is possible to reduce the content of undesirable impure chemical elements such as nitrogen or the like to be contained in an Al (alloy) film, and to improve the life of electromigration and the resistance to a hillock.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、物にウェーハに
電極・配線のAt或はA4合金薄膜を成膜する、半導体
装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which an At or A4 alloy thin film for electrodes and wiring is formed on a wafer.

〔従来の技術〕[Conventional technology]

従来、この樵の半導体装置の製造方法は、ウェーハ’k
X全チェンバ内に搬入し、クライオポンプや油拡散ポン
プで真空チェンバを排気しt後、AtやAt合会をスパ
ッタ法や真空蒸着法でクエーハに付着するようになって
いた。
Conventionally, this method of manufacturing semiconductor devices is based on wafers.
After transporting the entire X into the chamber and evacuating the vacuum chamber with a cryopump or oil diffusion pump, At and At agglomerates were attached to the quafer by sputtering or vacuum evaporation.

〔発明か解決しようとする問題点〕[The problem that the invention attempts to solve]

上述した従来の半導体装置の製造方法では、真壁チェン
バを排気する際油拡散ポンプを用いると、真空度が10
−  Torr台に到達しても、排気前の窒素やm素や
水分の分圧比はほぼその1)維持ちれる。lたクライオ
ポンプを用いる場合も、併気後は排気前に比べて水素な
ど蒸気圧の高い取分の分圧比が高くなり水分など蒸気圧
の比較的低い成分の分圧比は低くなるが、やはりかなり
高い分圧比で窒素や酸素が存在する。
In the conventional semiconductor device manufacturing method described above, when an oil diffusion pump is used to evacuate the Makabe chamber, the degree of vacuum is 10.
- Even if the temperature reaches the Torr range, the partial pressure ratios of nitrogen, hydrogen, and water before exhaust are almost maintained. Even when using a cryopump, the partial pressure ratio of fractions with high vapor pressure such as hydrogen will be higher after co-airing compared to before evacuation, and the partial pressure ratio of components with relatively low vapor pressure such as water will be lower. Nitrogen and oxygen exist at fairly high partial pressure ratios.

ロードロックタイプのスパッタ装置を用いて、真空チェ
ンバ内を4.0XIOTorrまで排気してからスパッ
タし之At膜やAt/Cu合金膜中には、オージェ電子
分光分析の結果〜5at%の窒素が薄膜中全域にわたっ
て存在してい友。
Using a load-lock type sputtering device, the vacuum chamber is evacuated to 4.0XIO Torr and then sputtered.As a result of Auger electron spectroscopy, ~5 at% nitrogen is found in the At film or At/Cu alloy film. A friend who exists throughout the entire country.

At膜やAt/Cu合金膜のエレクトロ・マイグレーシ
雷ン寿命やヒロック耐性に影響を及ばず残留不純物ガス
は窒素、酸素、水素、水分などでめり、影舎の大ささも
この順でるる。すなわち膜質に大きな影41を及ばずの
は大気の成分でろり、従来の半導体装置の製造方法では
これらの不純物成分を十分に取除けないという欠点かめ
る。
The remaining impurity gases are dissolved in nitrogen, oxygen, hydrogen, moisture, etc. without affecting the electro-migration lightning life or hillock resistance of the At film or At/Cu alloy film, and the size of the shadow is determined in this order. That is, it is the components of the atmosphere that do not have a large influence on the film quality, and the conventional semiconductor device manufacturing method has the disadvantage that these impurity components cannot be sufficiently removed.

上述した従来の半導体装置の製造方法に対し、本発明は
真空チェンバ内の窒素などの好ましくないガス成分の分
圧比を極めて低い状態にしてAtスパッタやAt蒸着を
行なうという独創的内容を有する。
In contrast to the conventional semiconductor device manufacturing method described above, the present invention has an original content in that At sputtering or At vapor deposition is performed while keeping the partial pressure ratio of undesirable gas components such as nitrogen in a vacuum chamber extremely low.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の製造方法は、ウェーハを真空チェ
ンバ内に搬入しクライオポンプにより前記真空チェンバ
内をIX I O−’ Torrよりも高真空になるよ
うに排気する排気工程と、前記真空チェンバ内に高純度
Arガスを導入し、Ti、Ta。
The method for manufacturing a semiconductor device of the present invention includes an evacuation step of carrying a wafer into a vacuum chamber and evacuating the inside of the vacuum chamber to a higher vacuum than IX I O-' Torr using a cryopump; High-purity Ar gas is introduced into Ti and Ta.

zr、Nb1M00W、Laなど大気成分ガスと活性に
反応する金属か或はこれら金属のうち少なくとも1つを
含む合金材を前記ウェーハに付着しないようにスパッタ
エツチングするスバッタエッチング工程と、前記高純度
Arガスを用い几スパッタ法か或は真空蒸着法によりA
t”!たはA/、合金を前記ウェーハに付着させる付着
工程とを有している。
a sputter etching step of sputter etching a metal that actively reacts with atmospheric component gas such as zr, Nb1M00W, La or an alloy material containing at least one of these metals so as not to adhere to the wafer; and A by using gas sputtering method or vacuum evaporation method
t"! or A/, a deposition step of depositing the alloy onto the wafer.

〔実施例〕〔Example〕

次に、本発明について図面tS照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1)gは本発明の第一の実施例を説明する几めの説明
図でろり、スパッタ装置のロードロック室lから真空チ
ェンバ2の中にウェーハ3を搬入したところを図示して
いる。
1) g is a detailed explanatory diagram for explaining the first embodiment of the present invention, and shows a wafer 3 being carried into a vacuum chamber 2 from a load lock chamber l of a sputtering apparatus.

ウェーハ3を第1図に図示するようにTaターゲット6
の側方の位置におい友まま、クライオポンプ4により真
空チェンバ2内を例えは4×1o−7Torr に到達
するまで排気する。
The wafer 3 is attached to a Ta target 6 as shown in FIG.
At a side position, the inside of the vacuum chamber 2 is evacuated by the cryopump 4 until the pressure reaches, for example, 4×10-7 Torr.

所定の真空度に達したらAr配管5から高純度Arガス
を真空チェンバ2内に導入し、Taターゲット6をグロ
ー放電にょクスバッタエッチングする。このとき、ウェ
ーハ3は第1図に図示する位置にあるのでTaは付着さ
れない。Taスパッタ終了後Ar配管5を閉じれは数分
以内に真空チェンバ2F3の真空度はlXl0−’ T
orr台に到達する。これはTaと窒素、酸素との反応
にょフこれらガスの分圧が下がったためでおる0次に、
ウェーハ3をAtターゲット7或はAt/Cu合金ター
ゲット8の正面に移動させ、高純度Arガx2導入して
スパッタ法にょクウェーハ3に所定の膜厚のAt或はA
 t/ Cu合金薄膜を堆積する。
When a predetermined degree of vacuum is reached, high-purity Ar gas is introduced into the vacuum chamber 2 from the Ar pipe 5, and the Ta target 6 is subjected to glow discharge sputter etching. At this time, since the wafer 3 is in the position shown in FIG. 1, Ta is not attached. After the Ta sputtering is completed, the Ar pipe 5 is closed and the vacuum level of the vacuum chamber 2F3 reaches lXl0-'T within a few minutes.
Reach the orr platform. This is due to the reaction between Ta, nitrogen, and oxygen, and the partial pressure of these gases has decreased.
The wafer 3 is moved in front of the At target 7 or the At/Cu alloy target 8, and high-purity Ar gas x2 is introduced to coat the wafer 3 with a predetermined thickness of At or Al using sputtering.
Deposit a t/Cu alloy thin film.

以上説明したように真空チェンバ2’t 4.0XIO
”−7Torrまで高真空にしてからTaターゲット6
を3分間スパッタエツチングした後、8i(J2が形成
されているSt基板でるるウェーハ3上にスパッタ法に
より1μm厚のAt膜を堆積し友サンプルを、30分間
460℃に加熱したところ、3000A以上の高さのヒ
ロックの発生は線密度で〜15個/c!ILに抑えるこ
とができた。
As explained above, vacuum chamber 2't 4.0XIO
” After creating a high vacuum to -7 Torr, Ta target 6
After sputter etching for 3 minutes, a 1 μm thick At film was deposited by sputtering on the St substrate wafer 3 on which 8i (J2 was formed) and the sample was heated to 460°C for 30 minutes. The occurrence of hillocks with a height of 200 mm could be suppressed to a linear density of ~15 pieces/c!IL.

尚、従来法で作成し友サンプルのヒロック線密度は〜2
8個/crrLでるる。
In addition, the hillock linear density of the sample prepared using the conventional method is ~2
8 pieces/crrL.

第2図は本発明の第二の実施例を説明するための説明図
である。
FIG. 2 is an explanatory diagram for explaining a second embodiment of the present invention.

前記した第一の実施例では現在一般に使用されているス
パッタ装置に本発明を適用した例を示し友が、窒素など
を吸着するためにスパッタすることを目的とするTaタ
ーゲットはウェーハに均一に薄膜を付着させる目的のタ
ーゲットと異なり、大きな面積を必要としない。
The first embodiment described above shows an example in which the present invention is applied to a sputtering apparatus that is currently in general use.A Ta target, which is intended for sputtering to adsorb nitrogen, etc., is used to form a thin film uniformly on a wafer. Unlike the target to which it is attached, it does not require a large area.

第2図において、窒素などの不純物ガス吸着用のTaタ
ーゲット6は比較的小型のものを用いており、ウェーハ
3に付着させないTaスパッタはウェーハ3にAt(合
金)を付着させるスパッタの直前に行なうとともにAt
(合金)スパッタ中も同時に行なう。
In FIG. 2, a relatively small Ta target 6 is used for adsorbing impurity gases such as nitrogen, and Ta sputtering without adhering to the wafer 3 is performed immediately before sputtering to adhere At (alloy) to the wafer 3. With At
(Alloy) This is also done at the same time during sputtering.

尚、第1図争第2図において、本発明の説明に直接関係
のない、各ターゲットのカンード電極や油回転ぎンプや
ロードロック室の配管系やウェーハ搬送機構などは省略
してめる。
In addition, in FIG. 1 and FIG. 2, the canned electrodes of each target, the oil rotary pump, the piping system of the load lock chamber, the wafer transport mechanism, etc., which are not directly related to the explanation of the present invention, are omitted.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明はs T i * ’ra*
 z+rINb、Mo、W、Laなどの金属材を真空チ
ェンバ内でスパッタエッチングし、窒素などの不純物ガ
スの分圧比を低くしてAtまたはA4合金をウェーハに
堆積することにより、AL(合金)膜中の窒素などの好
ましくない不純物元素の含有量を低減でき、エレクトロ
・マイグレーシ冒ン寿命ヤヒロック耐性を向上させるこ
とができる効果がるる。
As explained above, the present invention provides s T i *'ra*
By sputter etching metal materials such as z+rINb, Mo, W, and La in a vacuum chamber and depositing At or A4 alloy on the wafer with a low partial pressure ratio of impurity gas such as nitrogen, The content of undesirable impurity elements such as nitrogen can be reduced, and the electro-migration resistance and corrosion resistance can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第一の実施例を説明するための説明図
、第2図は本発明の第二の実施例を説明するための説明
内である。 l・・・・・・ロードロック室、2・・・・・・真空チ
ェンバ、3・・・・・・ウェーハ、4・・・・・・クラ
イオポンプ、5・・・・・・Ar配管、6・・・・・・
Taターゲット、7・・・・・・A/、ターゲット、8
・・・・・・At/Cu合金ターゲット。 代理人 弁理士  内 原   晋 ゛ニー”ゝ゛)゛
・     二パ づ−+/
FIG. 1 is an explanatory diagram for explaining a first embodiment of the present invention, and FIG. 2 is an explanatory diagram for explaining a second embodiment of the present invention. 1...Load lock chamber, 2...Vacuum chamber, 3...Wafer, 4...Cryopump, 5...Ar piping, 6...
Ta target, 7...A/, target, 8
...At/Cu alloy target. Agent Patent Attorney Susumu Uchihara

Claims (2)

【特許請求の範囲】[Claims] (1)ウェーハを真空チェンバ内に搬入しクライオポン
プにより前記真空チェンバ内を1×10^−^6Tor
rによりも高真空になるように排気する排気工程と、 前記真空チェンバ内に高純度Arガスを導入し、Ti、
Ta、Zr、Nb、Mo、W、Laなど大気成分ガスと
活性に反応する金属か或はこれら金属のうち少なくとも
一つを含む合金材を前記ウェーハに付着しないようにス
パッタエツチングするスパッタエッチング工程と、前記
高純度Arガスを用いたスパッタ法か或いは真空蒸着法
によりAlまたはAl合金を前記ウェーハに付着させる
付着工程とを有することを特徴とする半導体装置の製造
方法。
(1) Transport the wafer into a vacuum chamber and use a cryopump to pump the inside of the vacuum chamber to 1 x 10^-^6 Torr.
an evacuation process to achieve a high vacuum even by r, and introducing high-purity Ar gas into the vacuum chamber to remove Ti,
a sputter etching step of sputter etching a metal that actively reacts with atmospheric component gases such as Ta, Zr, Nb, Mo, W, La, or an alloy material containing at least one of these metals so as not to adhere to the wafer; . A method for manufacturing a semiconductor device, comprising the steps of: adhering Al or an Al alloy to the wafer by a sputtering method using the high-purity Ar gas or a vacuum evaporation method.
(2)前記付着工程中に前記スパッタエッチング工程を
同時に行う特許請求の範囲第1項記載の半導体装置の製
造方法。
(2) The method of manufacturing a semiconductor device according to claim 1, wherein the sputter etching step is performed simultaneously during the adhesion step.
JP22129486A 1986-09-18 1986-09-18 Manufacture of semiconductor device Pending JPS6376321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22129486A JPS6376321A (en) 1986-09-18 1986-09-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22129486A JPS6376321A (en) 1986-09-18 1986-09-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6376321A true JPS6376321A (en) 1988-04-06

Family

ID=16764531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22129486A Pending JPS6376321A (en) 1986-09-18 1986-09-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6376321A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5780357A (en) * 1994-12-14 1998-07-14 Applied Materials, Inc. Deposition process for coating or filling re-entry shaped contact holes
KR100404895B1 (en) * 2000-03-29 2003-11-10 주식회사 세너그린 divice for molding embossing lug of steel pipe
US6844628B2 (en) 1996-07-16 2005-01-18 Semiconductor Energy Laboratory Co., Ltd. Electronic device and method for manufacturing the same
JP2010084211A (en) * 2008-10-01 2010-04-15 Ulvac Japan Ltd Sputtering method
CN109666887A (en) * 2018-12-28 2019-04-23 广东工业大学 A kind of TiAlN hard coat and its preparation method and application

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5780357A (en) * 1994-12-14 1998-07-14 Applied Materials, Inc. Deposition process for coating or filling re-entry shaped contact holes
US6033541A (en) * 1994-12-14 2000-03-07 Applied Materials, Inc. Deposition process for coating or filling re-entry shaped contact holes
US6844628B2 (en) 1996-07-16 2005-01-18 Semiconductor Energy Laboratory Co., Ltd. Electronic device and method for manufacturing the same
US6940094B2 (en) 1996-07-16 2005-09-06 Semiconductor Energy Laboratory Co., Ltd. Electronic device and method for manufacturing the same
US6979882B1 (en) 1996-07-16 2005-12-27 Semiconductor Energy Laboratory Co., Ltd. Electronic device and method for manufacturing the same
US7298021B2 (en) 1996-07-16 2007-11-20 Semiconductor Energy Laboratory Co., Ltd. Electronic device and method for manufacturing the same
US7446392B2 (en) 1996-07-16 2008-11-04 Semiconductor Energy Laboratory Co., Ltd. Electronic device and method for manufacturing the same
KR100404895B1 (en) * 2000-03-29 2003-11-10 주식회사 세너그린 divice for molding embossing lug of steel pipe
JP2010084211A (en) * 2008-10-01 2010-04-15 Ulvac Japan Ltd Sputtering method
CN109666887A (en) * 2018-12-28 2019-04-23 广东工业大学 A kind of TiAlN hard coat and its preparation method and application
CN109666887B (en) * 2018-12-28 2021-04-06 广东工业大学 TiAlN hard coating and preparation method and application thereof

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