JPS637630B2 - - Google Patents

Info

Publication number
JPS637630B2
JPS637630B2 JP56054235A JP5423581A JPS637630B2 JP S637630 B2 JPS637630 B2 JP S637630B2 JP 56054235 A JP56054235 A JP 56054235A JP 5423581 A JP5423581 A JP 5423581A JP S637630 B2 JPS637630 B2 JP S637630B2
Authority
JP
Japan
Prior art keywords
circuit
input
diagnosed
bilbo
decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56054235A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56157877A (en
Inventor
Patsudo Fueezangu Patoritsuku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of JPS56157877A publication Critical patent/JPS56157877A/ja
Publication of JPS637630B2 publication Critical patent/JPS637630B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318569Error indication, logging circuits
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555Control logic
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/27Built-in tests

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
JP5423581A 1980-04-11 1981-04-10 Diagnosis apparatus for digital electronic circuit Granted JPS56157877A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13920780A 1980-04-11 1980-04-11

Publications (2)

Publication Number Publication Date
JPS56157877A JPS56157877A (en) 1981-12-05
JPS637630B2 true JPS637630B2 (enrdf_load_stackoverflow) 1988-02-17

Family

ID=22485562

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5423581A Granted JPS56157877A (en) 1980-04-11 1981-04-10 Diagnosis apparatus for digital electronic circuit

Country Status (3)

Country Link
EP (1) EP0037965B1 (enrdf_load_stackoverflow)
JP (1) JPS56157877A (enrdf_load_stackoverflow)
DE (1) DE3176315D1 (enrdf_load_stackoverflow)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8501143D0 (en) * 1985-01-17 1985-02-20 Plessey Co Plc Integrated circuits
GB2178175A (en) * 1985-07-18 1987-02-04 British Telecomm Logic testing circuit
DE3526485A1 (de) * 1985-07-24 1987-02-05 Heinz Krug Schaltungsanordnung zum pruefen integrierter schaltungseinheiten
JPH07122653B2 (ja) * 1986-04-21 1995-12-25 ソニー株式会社 試験回路
FR2611052B1 (fr) * 1987-02-17 1989-05-26 Thomson Csf Dispositif de test de circuit electrique et circuit comportant ledit dispositif
US4817093A (en) * 1987-06-18 1989-03-28 International Business Machines Corporation Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3716783A (en) * 1969-10-30 1973-02-13 E Systems Inc Sequential check-out system including code comparison for circuit operation evaluation
US3784907A (en) * 1972-10-16 1974-01-08 Ibm Method of propagation delay testing a functional logic system
US3761695A (en) * 1972-10-16 1973-09-25 Ibm Method of level sensitive testing a functional logic system
US3783254A (en) * 1972-10-16 1974-01-01 Ibm Level sensitive logic system
FR2330014A1 (fr) * 1973-05-11 1977-05-27 Ibm France Procede de test de bloc de circuits logiques integres et blocs en faisant application
US3921139A (en) * 1974-03-08 1975-11-18 Westinghouse Electric Corp Test system having memory means at test module

Also Published As

Publication number Publication date
EP0037965A3 (en) 1982-01-20
JPS56157877A (en) 1981-12-05
EP0037965B1 (de) 1987-07-15
DE3176315D1 (en) 1987-08-20
EP0037965A2 (de) 1981-10-21

Similar Documents

Publication Publication Date Title
US4340857A (en) Device for testing digital circuits using built-in logic block observers (BILBO's)
US4293919A (en) Level sensitive scan design (LSSD) system
US3783254A (en) Level sensitive logic system
EP0196171B1 (en) Digital integrated circuits
JP4177807B2 (ja) 回路テストシステム
JPS5988664A (ja) 自己試験可能な論理回路装置
EP0388001A2 (en) Testing method and apparatus for an integrated circuit
US3924109A (en) Automatic circuit card testing system
US4291386A (en) Pseudorandom number generator
JPS5975346A (ja) ラッチ列制御システム
JP2008096422A (ja) チップテスト装置とシステム
JPH0760400B2 (ja) 論理回路の診断方法
WO1980000375A1 (en) Hybrid signature test method and apparatus
US4680761A (en) Self diagnostic Cyclic Analysis Testing System (CATS) for LSI/VLSI
EP0020714B1 (en) Digital tester
US5278841A (en) Method and apparatus for diagnosing net interconnect faults using echo pulsed signals
JPS6232511B2 (enrdf_load_stackoverflow)
JPS637630B2 (enrdf_load_stackoverflow)
US5166937A (en) Arrangement for testing digital circuit devices having tri-state outputs
US7895489B2 (en) Matrix system and method for debugging scan structure
EP0209982A2 (en) Digital integrated circuits
US4471484A (en) Self verifying logic system
CN101191816B (zh) 芯片测试系统
US20210279391A1 (en) Semiconductor integrated circuit, circuit designing apparatus, and circuit designing method
JPS60253985A (ja) 集積回路試験装置