JPS6376200A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To easily extract a chip including a bit having a narrow action allowance by changing the internal voltage of a discharging circuit forcibly from an external part at the time of non-selection, preventing a discharging current from conducting, changing forcibly the internal potential of an information holding current generating circuit from the external part, decreasing an information holding current to execute a functional test. CONSTITUTION:At the time of the functional test, a current operating as a holding current, for example, a discharging current is controlled from an external part and decreased. Namely, it is realized by driving a terminal 13 for supplying the source voltage of an internal power source circuit 12 by the voltage lower than the terminal 7 of other circuit. This can easily add DELTAVEE (forward direction voltage of transistor) by providing respectively independently a power source terminal 7 and terminals 6 and 13 on a chip, connecting the 6 and 13, separating from the terminal 7, providing them and connecting them to the same terminal at the time of loading to a package. Thus, at the time of the functional test, the action allowance of a memory cell can be measured while the holding current is decreased, therefore, the detection of the memory cell having the narrow action allowance can be easily executed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory device, and in particular to a circuit system for easily evaluating the operating margin of a memory cell and obtaining a semiconductor memory device with stable operation. Related [Prior Art] The method generally used for circuit design of semiconductor integrated circuits is to
Integrated circuits designed in this way are designed so that the internal potential is constant or changes by the same value as 1. It is difficult to measure the operating margin of the circuit by changing the power supply voltage, so As described in No. 58-8079, the operating margin could be measured by changing the internal potential from the outside. However, when considering the information retention current of a memory cell, for example, the discharge current described in Patent Publication No. 12234/1980 constantly flows due to variations in element characteristics during R manufacturing, and as a result, it becomes a clear information retention current. In order to act,
However, the method described above does not take into consideration the fact that the information retention level of the memory cell cannot be reduced to the desired value for testing.

[The LA point that the invention attempts to solve] The above-mentioned conventional technology does not take into account the fact that the discharge current to drive the word line to the non-selected potential at high speed flows even when the word line is not selected, and the information Even if the holding current is reduced and tested, a part of the free current acts as an information holding current, which reduces the operating margin. There was a problem that the chip containing the Q bit could not be extracted.

An object of the present invention is to prevent bits with narrow operating margins from flowing during a functional test of a semiconductor integrated circuit including a memory by reducing the information retention current by preventing a free current from flowing when non-selected. The purpose is to facilitate chip extraction.

[Means to solve all problems]

The above purpose is to forcibly change the internal voltage of the discharge circuit from the outside when it is not selected, so as to prevent the free current from flowing.
This is achieved by forcibly changing the internal magnetic potential of the information retention current generating circuit from the outside, reducing the information retention current, and performing a functional test.

[Effect]

By forcibly changing the internal voltage of the discharge circuit from the outside, it is possible to completely prevent a part of the discharge current during non-selection from acting as an information retention current.For this reason, the information retention operation of the memory cell is , than i determined only by the information retention current
Therefore, by reducing the total information holding current, it is possible to easily detect steps including narrow pits (with sufficient operating margin).

[Implementation row]

An embodiment of the present invention will be described below with reference to FIG. In Part 1 of Kazuko Kazuko, I will discuss the problems of the conventional method. Storage information in the free-lag flop type memory cells IA to ID is held as follows. The holding current is the holding current of two current supply lines and two
Current flows to each memory cell through Bi. In each memory cell, a holding current flows from a pair of transistors whose emitters are commonly connected and whose base potential is higher.

This holding current causes the potential drop in the resistor connected to the collector of the transistor to drop, and the stored information is held.

This maintenance and flow generation is performed in the following manner. A current source circuit consisting of transistors 38 and 3B and resistors 4A and 4B, and an internal circuit that drives the pace of these transistors.
The source circuit 5 constitutes a constant current source circuit. When the output voltage of the internal power supply circuit 5 is set to 2Vmx (here, V a z is the forward voltage of the transistor) higher than the voltage applied to all terminals 6, and the same voltage as that of the terminal 6 is applied to the terminal 7, the holding t
The current IH supplied to this supply line is determined by setting the forward voltage of the transistor as Vat, and the resistance value of the four resistors and 4B as R4.
Then, it can be obtained by the following formula.

Therefore, IH does not depend on the power supply voltage supplied from the terminal 6 to the internal power supply circuit. On the other hand, in a slip-flop type memory cell as shown in this figure.

The operating margin of a memory cell largely depends on the holding current flowing from each memory cell. However, as mentioned above, even if the power supply voltage is changed, the holding current is changed (- is not possible).

Therefore, in the past, the terminals 6 and 7 were separated and a voltage of A was applied thereto to reduce the above-mentioned holding current for functional testing. That is, when a power supply voltage with a small absolute value is applied to 4f6 only at terminal 7: ΔVF, the detour flow Ia is obtained by the following equation.

By separating it from the power supply terminal in this manner, the current In flowing through the holding current supply line can be increased or decreased by changing the power supply voltage. According to this embodiment, in the glove inspection before one assembly.

It becomes possible to select memory cells with narrow operating margins and reject chips containing them as defective products.

However, when a discharge circuit as described in the first section is provided, it becomes difficult to reduce the holding current by controlling only the internal power supply circuit 5. Regarding the operation of this discharge circuit, as described in Japanese Patent Publication No. 57-12234, level shift circuits 9A and 9B"'r: level shift the potentials of word lines 8A and 8B when selected, and IOA
In addition to the current source circuit composed of IOB and resistors 11A and IIB, a stream of discharge is generated. When not selected,
Both transistors are made non-conductive to prevent discharge from flowing. However, due to the difference in level shift amount,
Transistors IOA and IOB even when word line is not selected
If the current does not become non-conductive and there is a current flowing that interferes with the holding direct current, it becomes difficult to reduce the holding current by controlling only the internal current cooling circuit 5, and the same control method will reduce the holding current. It is also necessary to reduce direct flow at the same time.

The present invention provides a current 1 that acts as a holding current during a functional test.
For example, it reduces the electrical discharge current by controlling it from the outside.
This is achieved by driving the power supply voltage supply terminal 13 of the internal power supply circuit 12 at a lower voltage than the terminals 7 of other circuits.

This can be done by providing power supply terminal 7 and terminals 6 and 13 independently on the chip, or by connecting 6 and 13 and providing them separately from terminal 7 so that they are connected to the same terminal when mounted on the pan cage. By doing so, △V■ can be easily added.

Various methods such as a bonding method and a CCB method can be used for mounting.

FIG. 2 shows a method for reducing the holding current described in Japanese Patent Application Laid-Open No. 58-8079. This circuit has a percentage characteristic that can be changed by applying an external buffer voltage to the terminal 14 and the output voltage of the internal power supply circuit 5 during a functional test. That is, by applying a voltage that is lower than the internally determined voltage to the terminal 14, it is possible to perform a functional test by reducing only the holding current.

FIG. 3 shows another embodiment of the invention. In this figure, when the word line is in the non-selected state, the holding current flows from the holding current supply line without completely turning off the transistors IOA and tOB, and acts as a holding current. Therefore, during one function test, the base potential of both transistors is Since it is possible to make the terminal 15 completely non-conductive by applying a voltage externally, the holding current f is reduced by externally changing the output voltages of the internal power supply circuits 5 and 12. , the same effect can be obtained by providing a means for externally applying a voltage to the internal potential of internal power supply circuits 5 and 12 (for example, node 16).Furthermore, three or more holding current supply lines 2 and 2B are provided. When two current sources are connected, it is preferable to take the above measures for each current source. However, the effect of the present invention can be sufficiently obtained even if it is not applied to all areas, so it is preferable to apply it in Q5 order starting from the one with the highest effect.

Also, although we have explained the bipolar type, the memory of the memory cell ('
This is effective for all memories in which the W signal is carried out by constantly flowing a holding current through the memory cells. In particular, in the case of a memory with logic that includes the entire logic, it is difficult to perform a functional test similar to that of a memory alone, so the effects of the present invention are more pronounced than when the memory is alone.

〔Effect of the invention〕

According to the present invention, since the operating margin of a memory cell can be measured with the holding current reduced during a performance test, it is easy to detect memory cells with a narrow operating margin, and this increases the This has the effect of reducing the test time associated with memory with logic (memory with logic, etc. in which logic circuits are integrated on the same chip).

[Brief explanation of the drawing]

FIG. 1 is a diagram of an internal power supply circuit of a memory cell according to an embodiment of the present invention, FIG. 2 is a diagram of a holding current generation circuit, and FIG. 3 is a diagram of a discharge current generation circuit. IA~11)...-Memory cell, 2A, 2B...Holding current supply line, 14.15...Terminal, 5...Internal power supply circuit.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit having a cell array consisting of memory cells that store information by constantly flowing a holding current and signal lines that supply the holding current to the memory cells, a cell array that is connected to the signal line that supplies the holding current 1. A semiconductor integrated circuit characterized in that conductive terminals to which voltages can be applied independently from the outside are provided at nodes of two or more current source circuits containing holding currents.