TW514929B - Method and apparatus thereof for burn-in testing of a static random access memory - Google Patents

Abstract

A apparatus uses a test method to burn-in testing of a static random access memory that has a plurality of word lines, a plurality of first bit lines, a plurality of second bit lines, and a plurality of memory cells for storing data. Each of the memory cells is coupled to a corresponding word line, a corresponding first bit line, a corresponding second bit line, and a power supply that is used to apply a working voltage to the memory cell to drive the memory cell. When the apparatus tests the static random access memory, the apparatus adjusts the working voltage according to a potential of the word lines and voltage gaps between the first bit lines and the second bit lines.

Description

514929 V. Description of the invention (1) [Field of the invention] The present invention provides a method and device for burn-in test, especially a method and device for burn-in test of static random access memory. [Background of the Invention] When the manufacture of static random access memory (SRAM) is completed, a burn-in is usually performed on the static random access memory to determine the static random access memory. Whether the body can function normally. Generally speaking, static random access memory contains a plurality of memory cells for storing data, and the purpose of pre-burning static random access memory is to make the static random access memory Some of the bad memory cells accelerate aging. Traditionally, during the burn-in test, the test is performed by sequentially selecting the memory cells. The selected memory cells are continuously applied with a voltage to perform a predetermined number of data writing and reading operations. . After the memory unit performs several data writing and reading operations continuously, if it can still operate normally, the memory unit is deemed to have no problem. On the contrary, if any of the memory cells in the static random access memory fails the burn-in test, the static random access memory will be considered as a defective product. Please refer to Fig. 1. Fig. 1 shows a conventional test device.

Page 5 514929

V. Description of the invention (2) Schematic diagram when accessing memory 20. 2 people in the static random access memory, a plurality of memory cells 22 for storing data, a complex number =, ^ neS) 24, a plurality of first bit lines (blt Hnes) 26a, and a first bit line 28, and Each memory unit 22 is electrically connected to—corresponding: a line 24, a corresponding first bit line 26, and a corresponding second bit. The green device 10 includes a control circuit 12 for controlling the test device. In operation, a power source 14 is used to supply power to each component of the test device 10, a row decoder 16 and a row of decoders.

Device (/ 〇W ^ deＣＯDER) 18, the test device 10 can select the memory unit 2 to be tested by the row decoder 16 and the "column decoder 18". Each memory unit 22 is electrically Connected to the power supply i 4, when the test device 丨 〇 tests static random access, when the body 20 is memorized, the power supply 14 will continue to apply a working power f Vcc maintained at positive five ^ to each memory unit 22 until the test is completed Up to static random access memory 20, and the control circuit 12 will select the memory unit 2 2 one by one by the row decoder 丨 6 and the column decoder 18 to perform the operations of writing and extracting data. ', Refer to Figure 2' Figure 2 is a circuit diagram of the memory unit 22 of Figure 1. As shown in Figure 2, each memory unit 22 includes a storage circuit 3 2, a first switch circuit 34 and a second switch circuit. 36. The storage circuit 32 is electrically connected to the power source 14 'to store one-bit data, and the first and second switch circuits 34 and 36 are electrically connected to a corresponding word line 24 and electrically connected respectively. Corresponding to the first and second bit lines 26, 28. As shown in FIG. 2, the memory unit 2 2 is composed of six A metal oxide semiconductor field effect transistor °

Page 6 514929 V. Description of the invention (3) (metal-oxide-semiconductor field-effect transistor (MOSFET) H, T2, T3, T4, T5, T6), wherein the storage circuit 32 is composed of transistors Π, Τ2, Τ3 And T4, the first switching circuit 34 and the second switching circuit 36 are respectively composed of a transistor T5 and a transistor T6. Among these six transistors, the transistors T1, T2 T5 and T6 are N-type metal-oxide semiconductors (NM0S), and transistors T3 and T4 are P-type metal-oxide semiconductors (PM0S), so the storage circuit 3 2 is a complementary metal-oxide semiconductor (〇111131611 ^ 111 ^ 1 ^ metal-oxide semiconductor, CMOS) circuit. When the test device 10 tests the static random access memory 2 0, the working voltage V cc supplied by the power supply i 4 is maintained at positive five volts, and the control circuit 12 selects an appropriate number by the column decoder 18 Word line 24 and private pressure on the selected word f 2 4%. After that, the control circuit 2 will test the memory unit 22 tested by $ f through the row decoder, and make the selected memory = ΐ the first bit line 2 6 to which it is electrically connected. And the second bit line 2 8 between the two etched six Γ pre- 疋 voltage value 'Finally the storage circuit 3 2 can be corresponding: ϊ ί: two V ± For example, when you want to set the logical value τ The data write plus #] The zigzag line 24 electrically connected to the second memory unit 22 will be applied with an encapsulation, so that the transistor 5 and T6 are electrically non-conductive, and the electrical connection = device 16 = selected Memory unit ^ Bit Fan Green 2 6 applies voltage to make the first bit

514929 V. Description of the invention (4) The voltage difference between the line 26 and the second bit line 28 is greater than a predetermined voltage value. When a voltage is applied to the first bit line 26, the voltage at the connection point A is increased (go high). When the voltage at point A is increased, transistor T2 will become conductive, and transistor T6 will become non-conductive, and the voltage at connection point B will go low. When the voltage at point B decreases, transistor T 3 will become conductive and transistor T 1 will become non-conductive. This will cause the voltage at point A to be raised again and cause the voltage at point B again. The value drops. Finally, the voltage at point A will be maintained at a predetermined high voltage value, and the voltage at point B will be maintained at a predetermined low voltage value. The storage circuit 32 will maintain the two points A and B at different voltages. To represent a bit of metadata (0 or 1) it stores. Similarly, when it is desired to write data with a logic value of `` 0 π '' into the storage circuit 32, the word line 24 electrically connected to the memory cell 22 will be applied with a voltage first, and then the memory cell 22 will be electrically charged. A voltage is applied to the connected second bit line 28 so that the voltage at point B is increased and the voltage at point A is decreased. Finally, the voltage at point A is maintained at a predetermined low voltage value, and the voltage at point B is maintained at a predetermined high voltage value. Therefore, when the test device 10 is pre-burned to test the static random access memory 20, it can generally be expressed by the following steps: (a) Select the memory unit 22 to be tested, and supply the operating voltage V cc to the selected Until the test is completed; (b) applying a voltage to the bit line 24 to which the selected memory cell 22 is electrically connected; (c) causing the memory cell 2 2 to be tested to The voltage difference between the electrically connected first and second bit lines 26, 28 is greater than a predetermined voltage value, so that

Page 8 V. Description of the invention (5) The corresponding data officer; 隹 ^ + 冩 is stored in the storage circuit 32. In addition, there is an electric current through bit 飧 4 ^ to Myiao Liu. There is a change in the data stored in Lu 32. Lushe Gan stored in Lu 32 ”Cuntun Lu 32. For example, if + is described, the transistor becomes an opening into the storage circuit 32. The transistor 2: Narrow: ❿ 'Because it is in the data writing state, the transistor T5 and the transistor n are combined] ... ,, The conductive state passes the first bit 堍% = a circuit loop will be formed, and there are electric steam οπ Lefan wire 26, transistor T5, and electric hybrid T1, six?丨 _ 1 tail / claw 32 is a ground terminal 38. In addition, every day T1 is hungry for the storage circuit, so there will be electricity through the electricity! Body II, factory ^ ,, the second line 28 high, within a period of time, the electric second " transformed into "〇" at the beginning ^ ^ ^ 骽 T2 will be in a conductive state, and the electrical point of the A point A bit line 26 is high, so a current flows through the second bit line 28, transistor T6, and transistor T2 to the other ground terminal 3 9 of the storage circuit 32, and a current flows through the transistor T5 to First bit line 2 6. However, because the first and second bit lines 26, 28 can withstand a limited current flow (usually about 700 m A), when the test device is tested, the static energy random access memory is tested. At 20:00, it is necessary to avoid the static random access memory 20 from being burned due to the excessive current flowing through the first and second ° bit 4 wires 26 and 28. The test device 10 can only select a part of the memory at the same time The body unit 22 is used for testing, so its testing time will be relatively long. Purpose and summary of the invention

514929 V. Description of the invention (6) Therefore, the object of the present invention is to provide a test device and a test method for burn-in testing a static random access memory. During the test, the current flowing through the bit line will be smaller. Therefore, the test device of the present invention can test more memory cells at the same time, which can shorten the test time. The test device includes a power source for applying a working voltage to the plurality of memory cells to enable the plurality of memory cells to perform a data writing operation. In addition, the test device further includes a control circuit for controlling the operation of the test device. The control circuit selects a predetermined number of memory cells for testing, and makes the voltage of the word line electrically connected to the selected memory cell higher than a first voltage value, and causes the selected memory cell to The voltage difference between the electrically connected first bit line and the second bit line is greater than a second voltage value. When the voltage of the word line electrically connected to the selected memory cell is higher than the first voltage value and between the first bit line and the second bit line electrically connected to the selected memory cell When the voltage difference is greater than the second voltage value, the control circuit will start to apply the working voltage to the selected memory unit to write data into the memory unit for storage. [Detailed description of the invention] Please refer to FIG. 3, which is a schematic diagram when the test device 100 of the present invention tests a static random access memory 1220. SRAM 1 2 0

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Contains a plurality of memory for storing data, a plurality of first bit lines 126, and a plurality of = bit digits ^ alphabetic memory cell I22 is electrically connected to a corresponding word line 12 [— = 应 的 弟 一The bit line 126 and a corresponding second bit line 128. The clothing set 100 includes a control circuit 112 for controlling the operation of the testing device 100, a power source 114 for supplying power to the various components of the testing device 100, a row of decoders 1 16 and a row Decoder 1 1 8 and test device 1 0 can use the row decoder 1 16 and the column decoder i 丨 8 to select the desired Z fe and the body unit 1 2 2 for data writing and reading. Take the test though random access memory 1 2 0. α Please refer to FIG. 4 ’FIG. 4 is a circuit diagram of the memory unit 1 2 2 of FIG. 3. As shown in FIG. 4, each memory unit 122 includes a storage circuit 132, a first switching circuit 134, and a second switching circuit 136. The storage circuit 132 is electrically connected to the power source 114 for storing one bit of data, and the first and second switch circuits 1 3 4 and 1 3 6 are electrically connected to a corresponding word line 1 2 4 and are electrically connected respectively. In the first and second bit line 1 2 6 and 1 2 8. As shown in FIG. 4, the memory cell 1 2 2 is composed of six metal-oxide-semiconductor field-effect transistors (MOSFETs) T1, T2, T3, T4, T5, and T6, where The storage circuit 132 is composed of transistors Π, T2, T3, and T4. The first switching circuit 1 3 4 and the second switching circuit 1 3 6 are respectively composed of a transistor T 5 and a transistor T 6. Among the transistors, the transistors T1, T2, T5, and T6 are N-type metal-oxide semiconductors.

514929 V. Description of the invention (8) semiconductor (NMOS), transistors T3 and T4 are P-type metal-oxide semiconductors (PM0S), so the storage circuit 1 3 2 is a complementary metal-oxide semiconductor (complementary metal-oxide semi conductor, CMOS) circuit 0 Please refer to FIG. 4 and FIG. 5. FIG. 5 is a timing diagram of each terminal voltage of the memory cell 1 2 2 in FIG. 4. When the test device 1 0 0 tests the static random access record sound 1 2 0, the control circuit 1 12 applies the record selected to the test, all of which are: \ / 元 _ 122 and the word line 124 to which it is electrically connected. Word line voltage

The voltage is higher than a first voltage value Vi, and the first and second bit lines 1 2 6 and 1 9 which are electrically connected to the selected memory card 1 2 2 are Q: 1ί ″ 8¼ Add two complementary periodic voltage signals V BL1, V BU, so that the voltage difference VG between the first and second bits-hanging 1 2 6 and 1 2 8 will be periodically greater than-giving a ^ eight, Two voltage values V 2. Among them, the period of the two voltage signals V BL1 and V blA are both 4 to 10%, but Lei is short of V BL (i.e., is applied on the first bit line 1 2 6). · U package! Δ generation on VR 丨 Tick the force port a on the second bit line 1 2 6 and the first and second bit green] and add it to the voltage difference V # in IVbli-Vbl2. , To control the U Bao Yin 1 1 2 between the thunder roads and also store the same line voltage V WL and the two voltage signals V BL1, V BL fishing power 懕 佶 a κ voltage of the operating voltage Vcc of the memory cell 122 1 to control when the voltage Vw applied to the word line 124 is higher than the first voltage value V and in winter

The voltage difference V between the bit lines 1 2 6 and 1 2 8 is larger than the voltage value V of the wide band, the first and the second, and the batch circuit 112 will cause the operating voltage Vcc from a third voltage value ν ~ Control four voltage values V4. Among them, the third voltage value V # Yu burns you and strengthens me.

514929 V. Description of the invention (9) said that when the voltage V WL of the word line 1 2 4 is not higher than the first voltage value V and the voltage difference V between the first and second bit lines 1 2 6 and 1 2 8 Before 涞 is greater than the second voltage value V 2, the sources (Source) of the transistors T 3 and T 4 are grounded. Different from the conventional test device 10, the test device 100 first applies the voltage to the word line 1 2 4 and the two-bit line 1 2 6 and 1 2 8 before applying the working voltage Vcc to the desired operation. The tested memory unit 1 2 2 and the test device 10 continuously applied a positive working voltage V cc to the tested memory unit 2 2 during the test period. In addition, the control circuit 1 1 2 changes the first and second bit lines 1 2 6, 1 by applying two complementary periodic voltage signals VBL1, VBL on the first and second bit lines 126, 128. The voltage difference between 2 and 8 changes the data type (1 or 0) stored in the memory unit 1 2 2 periodically. As shown in FIG. 5, when the voltage value of the word line 1 2 4 is raised to the voltage value V through the control circuit 1 12, the control circuit 1 12 will apply a periodic voltage signal V BU, V BL and The second bit lines 1 2 6 and 1 2 8 periodically change the voltage difference VG between the first and second bit lines 1 2 6 and 1 2 8. When the voltage value of the word line 1 2 4 is V w and the voltage values of the first and second bit lines 1 2 6 and 1 2 8 are V η and 0 respectively, the control circuit 1 1 2 changes the working voltage Vcc is raised to a fourth voltage value V 4 to write data with a logic value π 1 ″ into the storage circuit 1 3 2. In addition, when the voltage value of the word line 124 is Vw and the voltage values of the first and second bit lines 126 and 128 are 0 and V, respectively, the control circuit also increases the working voltage Vcc to a fourth voltage value V4. The data with the logic value is written into the storage circuit 132. However, when the memory unit 1 2 2 selected by the control circuit 1 1 2 is electrically connected to

Page 13 514929 V. Description of the invention (ίο) The voltage difference between the first and second bit lines 1 2 6 and 1 2 8 is less than the second voltage value V span. The control circuit 1 1 2 will cause the power supply 1 1 4 The application of the operating voltage V cc to the memory unit 122 is stopped, or the operating voltage Vcc is made smaller than the fourth voltage value V4. Therefore, when the logic value of the data stored in the storage circuit 1 3 2 is changed from π (Γ to '' Γ, the transistor T 1 will be in a non-conductive state and the voltage at point B will not be higher than the second position. Element line 1 2 8 so no current will flow through the first bit line 1 2 6 to a ground terminal 1 3 8 of the storage circuit 1 3 2 and no current will flow through the transistor T 6 to the second Bit line 1 2 8. On the other hand, when the logical value of the data stored in the storage circuit 1 3 2 is changed from π 1π to '' 0 ff, the transistor T 2 will be in a non-conductive state and point A. Voltage will not be higher than the first bit line 1 2 6, so no current will flow through the second bit line 1 2 8 to the other ground terminal 1 3 9 of the storage circuit 1 3 2, nor will there be The current flows through the transistor T 5 to the first bit line 1 2 6. In this way, when the test device 100 is testing the random access memory 1 2 0, compared with the conventional technology, if If the number of memory cells 1 2 2 tested is the same, the current value flowing through the first and second bit lines 12 6 and 1 2 8 will be much smaller. Also because the test device 1 0 0 When the machine accesses the memory 1 2 0, the current flowing through the first and second bit lines 1 2 6 and 1 2 8 is small (each memory cell is about 2 0 // A), so the test device 1 0 0 can test more memory cells 1 2 2 at the same time. As mentioned above, when the test device 1 0 0 tests the static random access memory 1 2 0, generally the following steps can be used to Means: (a) Select a predetermined number of memory cells 1 2 2 from a plurality of memory cells 1 2 2 by using a row decoder 1 16 and a column decoder 1 1 2 for testing;

514929 V. Description of the invention (11) (b) Make the voltage VWIi $ of the selected memory cell 1 2 2 and the zigzag line 1 2 4 electrically connected to the first voltage V ,; (c) make the selected The memory unit 1 2 2 has a voltage difference between the first bit line 1 2 6 and the second bit line 1 2 8 which is electrically connected to the second bit line 1 2 8 is greater than the second voltage value V 2; and (d) when the selected memory The voltage V of the word line electrically connected to the body unit 1 2 2 is higher than the first voltage value V and the selected memory cell 1 2 2 is electrically connected to the first bit line 1 2 6 and the second bit The voltage difference between the element wires 1 2 8 is greater than the second voltage value V, so that the working voltage Vcd is increased from the third voltage value V to the fourth voltage value V 4. In addition, if the control circuit 1 1 2 periodically applies the first and second bit lines 1 26 and 1 28 by applying two complementary periodic voltage signals VBU, VBL2 to the first and second bit lines If the voltage difference between the two bit lines 1 2 6 and 1 2 8 is greater than a second voltage value V, then when the test device 1 0 0 is in the burn-in test of the static random access memory 1 2 0, it additionally includes The following steps: (e) when the selected memory cell 1 2 2 is electrically connected to a voltage difference between the first bit line 1 2 6 and the second bit line 1 2 8 is smaller than the second voltage value V ί The power source 1 1 4 stops applying the operating voltage Vcc to the selected memory cell 12 2 or makes the operating voltage Vcc less than the fourth voltage value V 4; and (f) when the selected memory cell 1 2 2 is The voltage difference between the first bit line 1 2 6 and the second bit line 1 2 8 that are electrically connected is greater than the second voltage value V1, so that the operating voltage Vcc is increased to a fourth voltage value V4.

514929

V. Description of the invention (12) It should be noted that the test device 1 0 0 does not need to include the row decoder 1 6 and the column decoder 1 1 8. When the test device 1 0 0 is testing the random access memory 1 2 〇 At the time, the control circuit 1 1 2 can control the power supply 1 1 4 to directly apply voltage to the word line 1 2 4, the first bit line 1 2 6 and the second bit line 1 2 8 to store all the random access memories. The memory cell 1 2 2 in the body 12 is tested. In addition, since the test device 100 performs a test, the current flowing through the first and second bit lines 12 6 and 128 will be small, so the test device 100 can also be used to simultaneously test a wafer. A plurality of random access memories 1 2 0 formed on (wa fer) are tested. When testing the wafer-type δ-type inch 'test device 1000, all the memory cells 12 on the circle can be selected for testing, and the wafer will not be burned due to the excessive current. Compared with the conventional test device, the test device of the present invention intermittently provides a working voltage to the 5th fe unit of the test when testing the random access memory. When data is written into the self-memory unit The current through the bit line and the memory unit will be smaller than when the conventional test device is tested. Therefore, under the condition that the test device and the random access memory can withstand a limited current, the test device of the present invention can simultaneously Testing of the memory unit can effectively reduce the time required to test the random access memory. The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the application f = scope of the present invention shall fall within the scope of the patent of the present invention.

514929 Schematic description [Schematic description] Figure 1 is the intention of the conventional test device when testing a static random access memory. Figure 2 is a circuit diagram of the memory unit of Figure 1. FIG. 3 is a schematic diagram of a test device of the present invention when testing a static random access memory. FIG. 4 is a circuit diagram of the memory unit of FIG. 3. Figure 5 is the timing diagram of the terminal voltages of the memory early element of Figure 4. [Illustrated Symbols] 100 test device 112 control circuit 114 power supply 116 row decoder 118 column decoder 120 static random access memory 122 memory unit 124 word line 126 first bit line 128 second bit line 132 Storage circuit 134 First switch circuit 136 139 Second switch ground terminal circuit 138 Ground terminal

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Claims (1)

514929 VI. Application Patent Scope 1. A method for performing a burn-in test on a static random access memory (static random access memory), the static random access memory includes: a plurality of words Line (w 〇rd 1 ines); a plurality of first bit lines (bit 1 i η es); a plurality of second bit lines; and a plurality of memory cells (mem 〇ryce 1 1 s) for storing Data, each memory unit is electrically and electrically connected to a corresponding word line, a corresponding first bit line, a corresponding second bit line, and a power source, and the power source can apply a working voltage to the memory cell, In order to enable the memory cell to operate; the method includes the following steps: selecting a predetermined number of memory cells from the plurality of memory cells for testing; and making the voltage of the word line electrically connected to the selected memory cell Higher than a first voltage value; making the voltage difference between the first bit line and the second bit line electrically connected to the selected memory cell greater than a second voltage value; and The voltage of the word line electrically connected to the selected memory cell is higher than the first voltage value and the voltage difference between the first bit line and the second bit line electrically connected to the selected memory cell. When it is greater than the second voltage value, the working voltage is increased from a third voltage value to a fourth voltage value. 2. The method as described in item 1 of the patent application range, wherein the third voltage value, etc. 514929 6. The scope of patent application is zero volts. 3. If the method of claim 1 is applied, it further comprises the following steps: applying two complementary periodic voltage signals to the first bit line and the second bit line to which the selected memory cell is electrically connected, To periodically change the voltage difference between the first bit line and the second bit line. 4. If the method of claim 3 is applied, it further comprises the following steps: When the voltage difference between the first and second bit lines electrically connected to the selected memory cell is less than the second voltage value To stop the power supply from applying the operating voltage to the selected memory cell; and when the voltage difference between the first and second bit lines electrically connected to the selected memory cell is greater than the second voltage value To increase the working voltage to the fourth voltage value. 5. The method according to item 3 of the patent application, further comprising the following steps: when the voltage difference between the first and second bit lines electrically connected to the selected memory cell is less than the second voltage value To make the working voltage less than the fourth voltage value; and to make the working voltage when the voltage difference between the first and second bit lines electrically connected to the selected memory cell is greater than the second voltage value. Raise to the fourth voltage value. 6. The method of claim 1 in which each memory unit Page 19 514929 6. The scope of the patent application includes a storage circuit, a first switch circuit and a second switch circuit. The storage circuit is electrically connected to the power source and can be used to store one bit of data. The first and second The switch circuit is electrically connected to the corresponding word line and electrically connected to the corresponding first bit line and the second bit line, respectively. 7. The method of claim 6 in which the storage circuit is a complementary metal-oxide semiconductor (CMOS) circuit. 8. The method according to item 1 of the scope of patent application, wherein when a memory unit is selected from the plurality of memory units for testing, all the memory units in the static random access memory are selected for testing. 9. A test device for performing a burn-in test on a static random access memory, the static random access memory comprising: a plurality of word lines; a plurality of first bit lines; a plurality of second bit lines And a plurality of memory cells for storing data, each memory cell is electrically connected to a corresponding word line, a corresponding first bit line, and a corresponding second bit line; the test device includes There are: a power supply for applying a working voltage to the plurality of memory cells, so that the plurality of memory cells can perform data writing operation; 514929 6. The scope of the patent application and a control circuit electrically connected to the power supply for controlling the operation of the test device; wherein the control circuit will select a predetermined number of memory units for testing and make the selected memory unit The voltage of the word line electrically connected to it is higher than a first voltage value, and the voltage difference between the first bit line and the second bit line electrically connected to the selected memory cell is greater than a second Voltage value, when the voltage of the word line electrically connected to the selected memory cell is higher than the first voltage value and the first bit line and the second bit line of the selected memory cell to which it is electrically connected When the voltage difference between the lines is greater than the second voltage value, the control circuit increases the working voltage from a third voltage value to a fourth voltage value. 10. The test device according to item 9 of the scope of patent application, wherein the third voltage value is equal to zero volts. 1 1. If the test device for item 9 of the patent application scope further includes a row decoder and a column decoder, the control circuit will control the column decoder and the row decoder to select The memory unit to be tested. 1 2. The test device according to item 9 of the scope of patent application, wherein the control circuit applies two complementary periodic voltage signals to the first bit line and the second bit line to which the selected memory cell is electrically connected. To change this periodically 514929 6. Scope of patent application The voltage difference between the first bit line and the second bit line. 1 3. The test device according to item 12 of the scope of patent application, wherein when the voltage difference between the first and second bit lines electrically connected to the selected memory cell is less than the second voltage value, The control circuit causes the power supply to stop applying the operating voltage to the selected memory unit, and when the selected memory unit has a voltage difference between the first and second bit lines electrically connected to the selected memory unit, When the voltage is two, the control circuit will increase the working voltage to the fourth voltage. 1 4. The test device according to item 12 of the scope of patent application, wherein when the voltage difference between the first and second bit lines electrically connected to the selected memory cell is less than the second voltage value, The control circuit makes the working voltage smaller than the fourth voltage value, and when the voltage difference between the first and second bit lines electrically connected to the selected memory cell is greater than the second voltage value, The control circuit will increase the working voltage to the fourth voltage value. 1 5. The test device according to item 9 of the scope of patent application, wherein each memory unit includes a storage circuit, a first switch circuit and a second switch circuit. The storage circuit is electrically connected to the power source and can be used to store a For bit data, the first and second switch circuits are electrically connected to the corresponding word line and electrically connected to the corresponding first bit line and the corresponding second bit line, respectively. 16. The test device according to item 15 of the patent application scope, wherein the storage circuit 514929 Page 23