JPS6375986A - Bit map memory system - Google Patents

Abstract

PURPOSE:To contrive the speed up of processing of a whole bit map memory system, by connecting the data bus of a CPU with the address input of a pattern memory and the data output of the pattern memory with the data input of a bit map memory. CONSTITUTION:A data bus 110 is connected with the address input of a pattern memory 2 through a line 130 and the data output of the memory 2 is connected with the data input of a bit map memory 3 through a line 140. Moreover, the address bus 100 of a CPU 1 is connected with the address input of the memory 3 through a line 130. Three patterns of pattern numbers i21, j22, and k23 are previously written in the pattern memory 2. When the CPU 1 writes the pattern numbers i21-k23 only in the area 30 of the bit map memory 3, a hatched pattern is drawn in the area 30 by using the three patterns i21-k23. Since the pattern numbers can be used as writing data as they are in such way, the processing time can be reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a bitmap memory system, and more particularly to a bitmap memory configuration method suitable for rapidly filling a certain area with a two-dimensional specific pattern. .

[Conventional technology]

In conventional bitmap memory systems, when filling a certain area with a specific pattern, pattern data is created in the main memory 4 as shown in Figure 2, and then
Control means such as a microprocessor (hereinafter referred to as CP)
A method has been adopted in which data is transferred from time to time to the bitmap memory 3 using the UI (denoted as UI). Generally, the specific pattern to be filled is 8 x 8 bits or 16 bits.
A two-dimensional small area such as X16 bits is used, and this is repeatedly developed in a designated area on the bitmap memory 3, but in the conventional method, no consideration was given to pattern development.

[Problem that the invention seeks to solve]

In the above-mentioned conventional method, even though the specific pattern to be developed is fixed, it is necessary to refer to the pattern on the main memory every time the pattern is developed in the bitmap memory and transfer that pattern. For this reason, the process of expanding the pattern requires another process of referencing the pattern, which has been a problem in that the overall processing speed decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bitmap memory system that can eliminate unnecessary pattern references and improve the processing speed when performing the above processing.

[Means for solving problems]

The above object is to provide bitmap pattern data between the data bus of the CPU and the data input of the bitmap memory in a bitmap memory system equipped with a bitmap memory and a control means (hereinafter referred to as CPU) such as a microprocessor. A pattern memory is provided to hold the
This is accomplished by connecting the data bus of the CPU to the address input of a pattern memory and the data output of the pattern memory to the data input of the bitmap memory.

[Operation] A pattern to be developed is written in the pattern memory in advance. When the CPU writes to the bitmap memory, the address output by the CPU is the address of the bitmap memory, and the data output from the CPU corresponds to the pattern number of the pattern memory. As a result, the data actually written to the bitmap memory becomes the specified pattern in the pattern memory.

In this way, the CPU can develop a pattern by simply writing the pattern number indirectly into the bitmap memory, instead of reading out the pattern and writing it into the bitmap memory each time. Therefore, it is possible to eliminate the need for pattern reference, which was conventionally done, and eliminate the time required for reference, thereby improving the overall processing speed.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 3.

In FIG. 1, 1 is a CPU, 2 is a pattern memory, and 3 is a CPU.
is a bitmap memory, 100 is a CPUI address bus, and 110 is a CPU 1 data bus. A data bus 110 is connected to the address input of the pattern memory 2 via line 130, and the data output of the pattern memory is connected via line 140 to the data input of the bitmap memory 3.

In addition, for address input of bitmap memory 3, CPU
address bus 100 is connected via line 120.

FIG. 3 is an explanatory diagram when actually developing a pattern.

Now, pattern number i is stored in pattern memory 2 in advance.
It is assumed that three patterns, 21, j22, and k23, have been written by means not shown.

When using these to draw a diagonal pattern as shown in the figure in area J of bitmap memory 3, CPUI writes pattern numbers i21, j22 in area layer of bitmap memory 3.
, k23 only. Conventionally, these patterns were stored in the Ruffin memory 4 in FIG. 2, and the CPU read out the pattern based on the pattern number and then wrote it into the bitmap memory 3. According to the present invention, since the pattern number can be used as write data as it is, processing time can be shortened.

Note that, as in this embodiment, when the capacity of the pattern is particularly small, a register file 2' may be used as the pattern memory as shown in FIG.

Next, another embodiment will be explained with reference to FIG.

FIG. 5 shows a case where zero bitmap memories 3 (n is a natural number of 2 or more) are provided to store multi-tvm or multi-color bit images. In this case, the pattern memory 2 is provided corresponding to the bitmap memory 3 of each plane (hereinafter referred to as plane).

Conventionally, in such a multi-plane bitmap memory system, a register was provided at the position of the pattern memory 2 of each plane, as shown in Japanese Patent Laid-Open No. 57-181589. When the pattern is repeated, the whole play 2 is changed every time the pattern changes.
It was necessary to rewrite the corresponding registers, which placed a heavy burden on the CPU. According to this embodiment, once the pattern memory 2 is set for the first time, all that is required is to change the pattern number and repeat writing, so the load on the CPU is light and the processing speed is faster than that of the conventional method. This has the effect of being improved in proportion to the increase in the number of branes.

Although the above embodiment deals with the case where the capacity of the pattern memory 2 is small, another embodiment in which the capacity is large, that is, the number of patterns is large, will be described with reference to FIG.

Figure 6 shows CG (character generator: memory that stores character/symbol patterns) 2' as a pattern memory.
This is what was used. In this case, since it may not be possible to specify the pattern number of CG 2' using only the data bus 110 of the CPUI, the register 5 is used to expand the specification range of the pattern number.

Expanding a character pattern in a bitmap memory system required a lot of processing time because the pattern to be expanded is created each time, but with the present invention, the process of reading out the pattern can be omitted, so the expansion process can be It is possible to cut the time in half. In the case of character patterns, even in the case of a system with multiple planes as shown in Figure 5, the pattern memory can be used commonly for all planes, and when character expansion is performed in a bitmap memory system, it is generally Since the CG 2' is normally arranged in the same form as the main memory 4 in FIG. 2, the effect can be achieved with the same amount of hardware as the conventional system.

If it is necessary to shift the character pattern in the direction of the word boundary of the bitmap memory, means for shifting the pattern arrangement may be provided between the CG 2' and the bitmap memory 3. Even if a shift means is provided, this does not deviate from the essence of the present invention, which is to designate and write a pattern number.

〔Effect of the invention〕

According to the present invention, when developing a pattern in a bitmap memory, it is only necessary to write the pattern number indirectly without directly reading and writing the pattern, so the time required to refer to the bitmap pattern can be saved.
Accordingly, the processing time for pattern development can be halved. As a result, the response time of pattern development in a bitmap memory system, which has conventionally had a slow response time, is improved, and the system can be made more user-friendly.

[Brief explanation of the drawing]

1, 4, 5, and 6 are block diagrams showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional bitmap memory system, and FIG. 3 is a block diagram showing a conventional bitmap memory system. FIG. 2 is an explanatory diagram of the operation of the embodiment shown in the figure. l...CPU 2...Pattern memory 3...Bitmap memory

Claims (1)

[Claims] 1. In a bitmap memory system equipped with a bitmap memory and a control means (hereinafter referred to as CPU) such as a microprocessor, bitmap pattern data is inserted between the data bus of the CPU and the data input of the bitmap memory. A pattern memory is provided to hold the C.
A bitmap memory system characterized in that a data bus of a PU is connected to an address input of a pattern memory, and a data output of the pattern memory is connected to a data input of the bitmap memory.