JPS637516B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a wireless remote control system using wireless carrier means, which has multiple channels, and allows remote control by individually selecting any receiver from a large number of receivers. The present invention relates to a multi-channel remote control system.

First, a conventional example of a multi-channel remote control system, which is the premise of the present invention, will be explained. In addition, in this conventional example, a large number of pairs of transmitters 1 and receivers 2 are provided in a one-to-one correspondence, and an address information signal for selecting the corresponding receiver 2 is sent from any one transmitter 1. The transmitter 1 is configured to transmit the data using a wireless carrier, and the receiver 2 that receives the data determines whether or not it matches its own address setting data and controls the load 3. It is also possible to make a plurality of receivers 2 correspond to each other, create an address information signal for each receiver 2 in the transmitter 1, and call and control each receiver 2 individually using a circuit similar to the conventional example below. It was realized by. The transmitter 1 generates two types of frequency signals, for example, frequencies _f1 and _f2 , as modulation signals, and allocates one frequency to each unit time having a unit switching period of time length _TW . An address information signal is created, and a carrier wave signal of, for example, about 300 MHz is modulated using the address information signal, and the signal is sent out from the antenna 4 as a wireless signal. As shown in FIG. 1, the address information signal has a frequency f ₁ and
It is formed as a time-series frequency signal that is formed by combining the signals with f ₂ and one frequency for each unit time, and in the example shown in Fig. 1, this address information signal is 6
Indicates when the unit is composed of units. On the other hand, the receiver 2 includes a front end 5 composed of, for example, a super regenerative circuit of two transistors, and a gain of 80 dB.
a gain amplifier 6 whose center frequency is set to f ₁ and f ₂ , bandpass filters 7 ₁ and 7 ₂ whose center frequencies are set to f 1 and f 2, respectively, and an address setting section 8 formed of something like a pin board. , and a discrimination circuit 9 formed of an arithmetic processing LSI such as a microcomputer and inputting the outputs of the filters 7 ₁ and 7 ₂ and the output of the address setting section 8, and the outputs of the filters 7 ₁ and 7 ₂ (actually This filter 7 ₁ , 7 ₂
The output is digitized by a comparator),
A shift register 10 that is read and temporarily stored in synchronization with a clock signal corresponding to the unit switching period T _W on the transmitter 1 side is built into this discrimination circuit 9, and the stored contents of this shift register 10 and the address setting section 8 are A comparison circuit 12 compares the contents of the memory 11 that stores the setting contents to detect the self-call. The discrimination circuit 9 that has detected the call in this way also discriminates the added control data as necessary, and drives the speaker as the load 3 to produce a chime sound, or activates a relay to control an appropriate external load. It is designed to drive and control a relay output circuit that has a relay output circuit. Therefore, the address information signal consisting of a modulated carrier signal received by the receiving antenna 13 is amplified and demodulated by the front end 5, and is inputted in parallel to each filter 7 ₁ and 7 ₂ via a gain amplifier 6. The filters 7 ₁ , 7 ₂ correspond to the two frequency signals f ₁ , f _{2 ,} respectively, and produce an output from the filters 7 ₁ , 7 ₂ that matches the frequency of the demodulated signal received at that time, and outputs an output from the comparator. The outputs of the corresponding filters 7 ₁ and 7 ₂ are digitized by the digitizing means, and outputs corresponding to the frequencies f ₁ and f ₂ of the address information signals as shown in FIG. It will be input to circuit 9. The discrimination circuit 9 is the fourth
It is configured to perform the functional operation as shown in the figure, and inputs the outputs of the respective filters 7 ₁ and 7 ₂ corresponding to the frequencies f ₁ and f(2) from the signal input circuit 14, and Input digital signals as shown in FIG. 3 a and b are read as data shown in FIG. 3 c and d, respectively, and address information as shown in FIG. 3 e is temporarily stored in the shift register 10. Further, the address setting data set by the address setting section 8 is inputted to the discrimination circuit 9 by the address input circuit 15 and stored in the memory 11. Thus, in the discrimination circuit 9, the receiving address information temporarily stored in the shift register 10 and the address setting data stored in the memory 11 are compared in the comparison circuit 12, and when the two match, the output circuit 16 is activated. It operates and controls the external load 3.

As described above, when receiving and processing the received address information signal in the discriminating circuit 9, the filters 7 ₁ ,
The output of the transmitter ₇₂ is sampled and input to the discrimination circuit 9. Conventionally, the sampling period T _S based on this clock signal was made to match the unit switching period T _W on the transmitter 1 side. Therefore, when the sampling period T _S completely matches the unit switching period T _W , data can be read using the clock signal shown in FIG. 5 b in response to the received address information signal shown in FIG. 5 a. However, since transmitter 1 and receiver 2 operate completely independently, the unit switching cycle T changes over time. There are cases where _W and the sampling period T _S become different. Therefore, when the sampling period T _S becomes shorter than the unit switching period T _W , if a clock signal as shown in Figure 6 b is generated in response to the received address information signal as shown in Figure 6 a, the reading of the received address information signal will be delayed. There was a risk of making an error and causing a malfunction.

The present invention has been provided in view of the above points, and by setting the sampling period on the receiver side to be slightly longer than the unit switching period on the transmitter side, the sampling period can be prevented from becoming shorter due to changes over time. Even if the unit switching cycle on the transmitter side is
It is an object of the present invention to provide a multi-channel remote control system that prevents errors from occurring in reading received address information signals.

Therefore _, in the present invention, in the same circuit configuration as the conventional circuit shown in FIGS _. The period of the clock _signal to be read into the shift register ₁₀ via The sampling period T _S is set to be longer than the period T _W by about 5% of the unit switching period T _W .
Here, the above-mentioned difference in period length is realized as a difference in the frequency division ratio or the number of counts when the reference clock oscillation frequency signal of the discriminator circuit 9, etc. in the transmitter 1 and receiver 2 is divided and counted. The above 5% difference between the unit switching period T _W and the sampling period T _S is the same even when the maximum deviation of the unit switching period T _W and the maximum deviation of the sampling period T _S are added. This is set as a time difference such that the sampling period T _S does not become shorter than the unit switching period T _W .

As mentioned above, in the present invention, the sampling period on the receiver side is set to be slightly longer than the unit switching period on the transmitter side, so if the unit switching period or sampling period changes over time, In addition, the sampling period will no longer be shorter than the unit switching period, and there will be no error in reading the received address information signal to the discrimination circuit on the receiver side, and accurate data will always be read. This has the effect of making it possible.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of a conventional address information signal, Fig. 2 is a block diagram showing the overall configuration of the same as above, Figs. Figures 5a and b are explanatory diagrams of the data reading operation during normal operation of the same as above, and Figures 6a and b are
is an explanatory diagram of the data reading operation in the case of an abnormality as above,
7a and 7b are explanatory diagrams of the data reading operation of the embodiment of the present invention, in which 1 is a transmitter, 2 is a receiver, 3
is a load, 7 ₁ and 7 ₂ are filters, 9 is a discrimination circuit,
T _W is the unit switching period, and T _S is the sampling period.

Claims (1)

[Claims] 1 One or more transmitters and a plurality of receivers are provided, and an address information signal created by combining and allocating multiple types of frequency signals to each unit time of a plurality of units can be sent to an arbitrary one. In a multi-channel remote control system in which the address information signal is transmitted from a transmitter and received by an arbitrary receiver selected by the address information signal to control the load, the frequency components of each frequency signal included in the address information signal are a plurality of filters each discriminating;
storage means for reading and storing the output state of each of the filters in synchronization with a clock signal generated at a cycle slightly longer than the unit switching cycle on the transmitter side;
A multi-channel remote control system characterized by comprising a circuit that detects that the received data stored in these storage means matches the address setting data assigned to its own receiver and operates the load. .