JPS60180149U - radio receiver - Google Patents
radio receiverInfo
- Publication number
- JPS60180149U JPS60180149U JP6851184U JP6851184U JPS60180149U JP S60180149 U JPS60180149 U JP S60180149U JP 6851184 U JP6851184 U JP 6851184U JP 6851184 U JP6851184 U JP 6851184U JP S60180149 U JPS60180149 U JP S60180149U
- Authority
- JP
- Japan
- Prior art keywords
- tuner section
- signal
- intermediate frequency
- circuit
- local oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Superheterodyne Receivers (AREA)
- Noise Elimination (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案に係るラジオ受信機の要部ブロック図、
第２図は妨害の有無を説明する説明図、第３図はサンプ
リングホールド指令と局部発振器切換指令のタイムチャ
ート、第４図は本考案にか）る中間周波帯域切換の処理
の流れ図である。
１１・・・・・・第１のチューナ部、１２・・・・・・
第１の中間周波増幅器、１３ａ・・・・・・広帯域の正
フィルタ、１３ｂ・・・・・・狭帯域のＩＦフィルタ、
１４・・００．。
正フィルタ切換回路、１５・・・・・・第２のチューナ
部、１６・・・・・・レベル検出回路、１７・・・・・
・コントローラ、１８・・・・・・局部発振器切換回路
、２２・曲・サンプリングホールド回路、ＰＬＬＰ ｌ
、 ＰＬＬＰ ２・・・・・・第１、第２のフェーズ
ロックドループ。FIG. 1 is a block diagram of the main parts of a radio receiver according to the present invention,
FIG. 2 is an explanatory diagram illustrating the presence or absence of interference, FIG. 3 is a time chart of a sampling hold command and a local oscillator switching command, and FIG. 4 is a flow chart of intermediate frequency band switching processing according to the present invention. 11...First tuner section, 12...
1st intermediate frequency amplifier, 13a... wideband positive filter, 13b... narrowband IF filter,
14...00. . Positive filter switching circuit, 15... Second tuner section, 16... Level detection circuit, 17...
・Controller, 18...Local oscillator switching circuit, 22・Song・Sampling hold circuit, PLLP l
, PLLP 2...First and second phase-locked loops.
Claims (1)
間周波増幅器と、第１のチューナ部と第１の中間周波増
幅器間に配設された異なる周波数帯域を有する少なくと
も２つの中間周波フィルタと、中間周波フィルタ選択指
令に基づいて第１のチューナ部出力を所定の中間フィル
タを介して第１の中間周波増幅器に入力する第１の切換
回路と、第２のチューナ部と、第２のチューナ部の出力
レベルを検出するレベル検出回路と、１つのＰＬＬ回路
を共用すると共に、各チューナ部に対応して形成された
第１、第２のフェーズロックドループと、局部発振器切
換指令により所定のチューナ部の局部発振器出力信号を
ＰＬＬ回路に入力する第２の切換回路と、第１のフェー
ズロックドループ内に配設されると共に、サンプリング
ホールド指令によりＰＬＬ回路出力電圧をサンプリング
ホールドして該ホールド値を第１チューナ部の局部発振
器に入力するサンプリングホールド回路と、サンプリン
グホールド指令と局部発振器切換指令を出力すると共に
、第２のチューナ部をして少なくとも隣接妨害局からの
妨害信号を受信出力させ、妨害信号の受信レベルを前記
レベル検出回路から得、希望信号と妨害信号のレベルに
基づいて中間周波フィルタ選択指令を発生するコントロ
ーラを有することを特徴とするラジオ受信機。A first tuner section that receives and outputs a desired signal, a first intermediate frequency amplifier, and at least two intermediate frequency filters having different frequency bands disposed between the first tuner section and the first intermediate frequency amplifier. a first switching circuit that inputs the output of the first tuner section to the first intermediate frequency amplifier via a predetermined intermediate filter based on an intermediate frequency filter selection command; a second tuner section; A level detection circuit that detects the output level of the tuner section and one PLL circuit are shared, and the first and second phase-locked loops formed corresponding to each tuner section and the local oscillator switching command are used to generate a predetermined signal. A second switching circuit inputs the local oscillator output signal of the tuner section to the PLL circuit, and is disposed within the first phase-locked loop, and samples and holds the PLL circuit output voltage according to a sampling and hold command, and outputs the hold value. a sampling hold circuit that inputs the signal to the local oscillator of the first tuner section, outputs the sampling hold command and the local oscillator switching command, and causes the second tuner section to receive and output at least a disturbance signal from an adjacent disturbing station; A radio receiver comprising a controller that obtains the received level of the interfering signal from the level detection circuit and generates an intermediate frequency filter selection command based on the levels of the desired signal and the interfering signal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6851184U JPS60180149U (en) | 1984-05-10 | 1984-05-10 | radio receiver |
| US06/733,593 US4654884A (en) | 1984-05-10 | 1985-05-10 | Radio receiver with switching circuit for elimination of intermodulation interference |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6851184U JPS60180149U (en) | 1984-05-10 | 1984-05-10 | radio receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60180149U true JPS60180149U (en) | 1985-11-29 |
| JPH0210680Y2 JPH0210680Y2 (en) | 1990-03-16 |
Family
ID=30603327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6851184U Granted JPS60180149U (en) | 1984-05-10 | 1984-05-10 | radio receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60180149U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01159436U (en) * | 1988-04-25 | 1989-11-06 |
-
1984
- 1984-05-10 JP JP6851184U patent/JPS60180149U/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01159436U (en) * | 1988-04-25 | 1989-11-06 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0210680Y2 (en) | 1990-03-16 |
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