JPS6373410A - Power supply controller - Google Patents

Abstract

PURPOSE:To prevent destruction of a RAM due to a voltage drop which is caused when the power is supplied by starting the supply of power with a prescribed time delay. CONSTITUTION:A switch 8 is set at the earth side when no external power is supplied from a terminal T1. At the same time, an internal circuit 6 is separated from a power supply line P1 and a RAM7 receives the supply of power from a battery B1 and set under a stand-by state. An input port circuit 1 detects the supply of voltage of an external power supply carried out through the terminal T1 and changes a signal line 11 to H from L. Thus a resetting circuit 31 drives a timer 5 and the timer 5 sends a pulse signal to a signal line 52 after a prescribed time. An internal power supply control circuit 2 changes the switch to a power supply line P1 from the earth side owing to said pulse. Thus it is possible to prevent such a case where the circuit 6 is actuated before the voltage supplied from a power supply is set at a prescribed level and the voltage of the battery B1 is set under the level of stand-by voltage to destruct the contents of the RAM.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a power supply control device for controlling the on/off of the power source of an electronic device, and in particular, the present invention relates to a power supply control device for controlling the on/off of the power source of an electronic device, and in particular, the present invention relates to a power supply control device for controlling the on/off of the power source of an electronic device. This relates to power control at the time of switching between a state in which power is supplied from a relatively low-voltage battery to preserve the contents (hereinafter referred to as a standby state) and a normal operating state.

[Conventional technology]

Recently, various types of electronic devices have become more densely packed, and are required to consume as little power as possible and generate as little heat as possible. Designed to apply low battery voltage.

FIG. 3 is a block diagram showing an example of such a conventional device, and shows an example of power supply control in a 4-bit microcomputer. In the figure, T1 is an external power supply terminal,
D, p, D2, and D3 are reverse current blocking diodes, C□ is a capacitor, and B□ is a battery. Terminal T1
An external power supply (referred to as a normal power supply in this specification) capable of supplying a relatively large current is connected to the power supply. In normal operating conditions, the voltage at terminal T is higher than the voltage at battery B□, so diodes D, , D2. D3
Therefore, no current flows through battery B□. In addition, if the voltage at terminal T0 is momentarily interrupted, current is supplied from capacitor C to power line P, and the voltage at capacitor C1 changes to battery B.
When the voltage drops below the voltage □, current is supplied from the battery B1 to the power line for the first time. Also, in Figure 3 (1
) is the input port circuit, (2) is the internal power supply control circuit, (3
) is the reset circuit, (4) is the clock generation circuit, (5)
is a timer, (6) is an internal circuit, (7) is a RAM, (8
1 is a switch. The internal circuit (6) includes six registers (including an address register for ROM) and A
It includes circuits such as LU (arithmetic circuit) that consume current even when the operation is stopped. On the other hand, the internal power supply control circuit +21, IJ upper set path (3), clock generation circuit (4), and timer (5) consume almost no current when they are reset and stop operating. Also R.A.
Although M171 retains its memory contents while being supplied with voltage from battery B, writing/reading is not performed in the standby state. The clock generation circuit (4) is composed of an oscillation circuit and a frequency dividing circuit. (11).

(21), (22), (31), (32)
, (41), (42).

(51) and (61) are signal lines, respectively.

FIG. 4 is a waveform diagram showing the waveforms of signals in each part of the circuit in FIG. It's called a signal.

tel is the signal on the signal line (22), ld) is the signal on the signal line (4)
1) or (42), tel is the signal on the signal line (51), ge) is the signal on the signal line (31), (g) is the signal on the signal line (21), (h] is the signal on the signal line (21), The signal on the signal line (32) is shown.

Next, the operation of the circuit shown in FIG. 3 will be explained using FIG. 4. Assume that the power applied to terminal T□ is cut off a little before time t in order to enter the standby state. (
Alternatively, suppose that the voltage applied to the terminal T□ is restored a little before time t2 (it may be assumed that the magnetic pressure has decreased due to a source fault). Power supply sp. The input port circuit (1) that detected the voltage change above is connected to the signal line (11)
Figure 4 above! A signal having a waveform shown at at (hereinafter referred to as signal a; other signals shown in FIG. 4 are also referred to as signals bh) is output. The internal circuit (6) detects the point at which the signal a on the signal line (11) changes from logic "H" to "L" and immediately performs necessary processing (for example, saving the contents of a register), and then outputs a pulse. Send signal b (switching instruction signal). The pulse signal S changes both the signals e and g in the internal power supply control circuit (2) from logic "H" to "L". When the logic of the signal C on the signal line (22) becomes rLJ, the clock generation circuit (4) stops operating, and the signal C on the signal line (41) and (
42) The above signal d is fixed to logic rLJ. The reset circuit (3) is set by the fall of the signal C, and the signals f and h on the signal lines (31) and (32) change from logic rLJ to rHJ, respectively. The switch (8) is controlled by the signal g on the signal line (21), and the power terminal of the internal circuit (6) is disconnected from the power line P□ and grounded. Because of the signal f on the signal line (31), the internal power supply control circuit (
21 and the internal circuit (6) are reset and become inactive.

In the above state, that is, in the standby state, the voltage from battery B1 is applied to RAM +71 to save the memory contents of RAM +71, and other circuits stop operating even in the stopped state. The internal circuit (6) that consumes current is interrupted by the power line P□, so
The current flowing out from the battery B□ is about several tens of NA to 1 μA.

When signal a changes from logic rLJ to rHJ at time t2, signal ! The signal Crg on I(21) and (22) is also logic rLJ
becomes rHJ, and the clock generation circuit (4) starts generating clock pulses, and the signal on the signal line (32) falls from logic rf (J to rLJ, cancels the reset of the timer (5), and outputs the signal on the signal line (21) The switch (8) is controlled by the above signal fgl, and voltage is again applied to the internal circuit (6) from the power line P□.Also, after the time set by the timer (5), the signal line (51) Signal e is output on signal line (31), which is the output of reset circuit (3), and signal f on signal line (31) becomes logic rLJ, canceling the reset of internal circuit (6) and starting normal operation. .

[Problem that the invention seeks to solve]

The conventional device operates as described above, and in the standby state where the magnetic pressure at terminal T is zero, the RAM is transferred from battery B□ [7]
protects the memory contents of RAM [71] by supplying current to
When the voltage at terminal T□ reaches the normal voltage, the entire circuit operates normally. However, in order for the voltage at terminal T0 to rise from zero to the normal voltage near the +2 time point shown in Figure 4, it takes time to rise due to the time constant of the external power supply circuit and the time constant for charging capacitor C1. , when the voltage at terminal T□ has not yet risen sufficiently and current is still being supplied from battery B□ to power line P1, signal g on signal line (21) has already become logic rHJ and the power line P□ and the power supply terminal of the internal circuit (6) may be connected. In this case, a current of 1 mA to 2 mA flows from the battery B□ to the power line P□, so the voltage on the power line P□ decreases, and the intestine I 1
There was a problem that the memory contents of 71 were erased.

This invention was made to solve the above-mentioned problems, and provides a power supply control device that can minimize current consumption in standby mode and reliably protect the memory contents of RAM +71. The purpose is to

[Means for solving problems]

In this invention, the signal a on the signal line (11) (see FIG. 4)
The signal g on the signal line (21) was caused to rise after a predetermined time delay from the rising point of the signal g.

[Effect]

According to this invention, at the time when the internal circuit (6) is connected to the power line P□, the voltage on the power line P□ is approximately the normal voltage value, so the voltage applied to the RAM [71 is abnormal. Accidents of deterioration do not occur.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
The same reference numerals as in the figure indicate the same or equivalent parts, and (52) is the pulse signal e sent from the timer (5) to the internal power supply control circuit (2).
This is a signal line that sends out .

Further, FIG. 2 is a waveform diagram showing the waveforms of signals in each part of the circuit of FIG. 1, and signals with the same letters and symbols as those in FIG. 4 indicate the same or equivalent signals. Signal e' is the signal on signal hiro 52), signal g
' indicates a signal on the signal line (21) in FIG. In this specification, the signal e' is referred to as a first delayed pulse, and the signal e is referred to as a second delayed pulse.

In FIGS. 1 and 2, the parts with the same symbols as in FIGS. 3 and 4 operate in the same way and generate signals indicated by the same letters and symbols, so a description of the operation of those parts will be omitted and the signal e/
, g/ will be explained.

+2 When the signal becomes logic rLJ, the reset of the timer (5) is released and the signal e is generated after a predetermined time, as in the case of Fig. 3, but the signal e is generated before the signal e is generated. e' is generated and sent to the internal power supply control circuit via a signal line (52). Internal power supply control circuit (2)
The signal g' output from the signal line (21) to the signal e'
The logic changes from “L” to “H” and the switch (8)
is controlled to connect the internal circuit (6) to the power supply line P. At this point, the voltage on the power line P0 is sufficiently high, so that the RAM +7) is not affected by connecting the internal circuit (6) to the power line P□. Further, in this specification, the time from +2 to signal e' is referred to as a first delay time, and the time from signal e' to signal e is referred to as a second delay time.

After the power supply voltage is supplied to the internal circuit (6) in this manner, the signal f on the signal line (31) becomes logic "L" and the internal circuit (6) starts operating.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to prevent the phenomenon in which the screw pressure supplied to the RAM+71 decreases abnormally during the transition period of canceling the standby state.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing signal waveforms of each part of the circuit in FIG. 1, and FIG.
The figure is a block diagram showing an example of a conventional device.
FIG. 3 is a waveform diagram showing signal waveforms of each part of the circuit shown in the figure. (1) is an input port circuit, (2) is an internal power supply control circuit,
(3) is a reset circuit, (4) is a clock generation circuit, (
5) is a timer, (6) is an internal circuit, and (7) is a sea bream. Note that the same reference numerals in each figure indicate the same or similar parts.

Claims (1)

[Claims] A power supply line that is supplied with a voltage from a normal power supply having a regular voltage in a normal operating state, and is supplied with a voltage from a battery power supply having a voltage lower than the normal voltage in a standby state. In a power supply control device for an electronic device having an input port circuit that detects the voltage of the above-mentioned normal power supply and outputs a logic "L" signal when the voltage is below a predetermined value and a logic "H" signal otherwise. , an internal circuit that detects the falling point of the output signal of this input port circuit from logic "H" to "L" and outputs a switching instruction signal after completing necessary processing, with the switching instruction signal as a starting point; Means for stopping the operation of the timer, resetting the internal circuit, and disconnecting the internal circuit from the power supply line, detecting the rising point of the output signal of the input port circuit from logic "L" to "H"; means for restarting the operation of the above timer;
means for outputting a first delayed pulse at a time delayed by a delay time of , and outputting a second delayed pulse at a time delayed by a predetermined second delay time from the output time of the first delayed pulse; A power supply control characterized by comprising means for connecting the power supply line to the internal circuit at the time of outputting the first delayed pulse, and releasing the reset of the internal circuit at the time of outputting the second delayed pulse. Device.