JPS6372921U - - Google Patents
Info
- Publication number
- JPS6372921U JPS6372921U JP11237287U JP11237287U JPS6372921U JP S6372921 U JPS6372921 U JP S6372921U JP 11237287 U JP11237287 U JP 11237287U JP 11237287 U JP11237287 U JP 11237287U JP S6372921 U JPS6372921 U JP S6372921U
- Authority
- JP
- Japan
- Prior art keywords
- switch means
- resistance value
- resistance element
- variable resistance
- voltage dividing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Attenuators (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
第１図は本考案の実施例を示す回路図、第２図
は第１図の動作を説明するための図、第３図は従
来のレベル調整回路の回路図、第４図は第３図の
動作を説明するための図である。
ＶＲ……可変抵抗、Ｓ１〜Ｓ４……スイツチ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of FIG. 1, FIG. 3 is a circuit diagram of a conventional level adjustment circuit, and FIG. 4 is a circuit diagram of a conventional level adjustment circuit. FIG. VR...Variable resistance, S1-S4...Switch.
Claims (1)
て第１及び第２の信号が選択的に印加され摺動端
から該第１又は第２の信号出力を導出する可変抵
抗素子と、両端が第２の信号と基準電位点に接続
され且つ分圧点が前記可変抵抗素子の他端に接続
された分圧回路と、前記分圧回路の分圧点と基準
電位との間に接続され前記第２のスイツチ手段と
連動する第３のスイツチ手段とを備え、前記第１
のスイツチ手段を閉成し、第２、第３のスイツチ
手段を各々開放及び閉成した状態において第１の
信号出力が前記可変抵抗素子の抵抗値に応じて変
化すると共に、前記第１のスイツチ手段を開放し
、第２、第３のスイツチ手段を各々閉成及び開放
した状態において第２の信号出力が前記可変抵抗
素子の最小抵抗値から所定抵抗値まで略同一の出
力レベルで推移し、所定抵抗値以上では前記可変
抵抗素子の抵抗値に応じて変化するように構成し
たことを特徴とするレヘル調整回路。 (2) 前記分圧回路は前記可変抵抗素子の他端と
前記基準電位点との間に接続された第１の抵抗と
、一端が前記可変抵抗素子の他端に接続され他端
が前記第２の信号に接続された第２の抵抗とから
なることを特徴とする実用新案登録請求の範囲第
１項記載のレベル調整回路。[Claims for Utility Model Registration] (1) First and second signals are selectively applied to one end via first and second switch means, and the first or second signal is output from the sliding end. a voltage dividing circuit having both ends connected to a second signal and a reference potential point and a voltage dividing point connected to the other end of the variable resistance element, and a voltage dividing point of the voltage dividing circuit. and a third switch means connected between the third switch means and the reference potential and interlocked with the second switch means,
When the first switch means is closed and the second and third switch means are opened and closed, respectively, the first signal output changes according to the resistance value of the variable resistance element, and the first switch means changes depending on the resistance value of the variable resistance element. the second signal output changes at substantially the same output level from the minimum resistance value of the variable resistance element to the predetermined resistance value in a state where the means is opened and the second and third switch means are closed and opened, respectively; A level adjustment circuit characterized in that the level adjustment circuit is configured to change in accordance with the resistance value of the variable resistance element when the resistance value exceeds a predetermined resistance value. (2) The voltage dividing circuit includes a first resistor connected between the other end of the variable resistance element and the reference potential point, one end connected to the other end of the variable resistance element, and the other end connected to the first resistor. 2. The level adjustment circuit according to claim 1, further comprising a second resistor connected to a second signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11237287U JPS6348977Y2 (en) | 1987-07-22 | 1987-07-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11237287U JPS6348977Y2 (en) | 1987-07-22 | 1987-07-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6372921U true JPS6372921U (en) | 1988-05-16 |
| JPS6348977Y2 JPS6348977Y2 (en) | 1988-12-16 |
Family
ID=30993190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11237287U Expired JPS6348977Y2 (en) | 1987-07-22 | 1987-07-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6348977Y2 (en) |
-
1987
- 1987-07-22 JP JP11237287U patent/JPS6348977Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6348977Y2 (en) | 1988-12-16 |
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