JPS6370461A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6370461A JPS6370461A JP61215276A JP21527686A JPS6370461A JP S6370461 A JPS6370461 A JP S6370461A JP 61215276 A JP61215276 A JP 61215276A JP 21527686 A JP21527686 A JP 21527686A JP S6370461 A JPS6370461 A JP S6370461A
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- film
- nitride film
- positive resist
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 claims abstract description 6
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000005083 Zinc sulfide Substances 0.000 abstract description 11
- 229910052984 zinc sulfide Inorganic materials 0.000 abstract description 11
- DRDVZXDWVBGGMH-UHFFFAOYSA-N zinc;sulfide Chemical compound [S-2].[Zn+2] DRDVZXDWVBGGMH-UHFFFAOYSA-N 0.000 abstract description 11
- 230000001681 protective effect Effects 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 7
- 230000002093 peripheral effect Effects 0.000 abstract description 6
- 239000010408 film Substances 0.000 abstract 9
- 238000000926 separation method Methods 0.000 abstract 2
- 239000010409 thin film Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- LZZYPRNAOMGNLH-UHFFFAOYSA-M Cetrimonium bromide Chemical compound [Br-].CCCCCCCCCCCCCCCC[N+](C)(C)C LZZYPRNAOMGNLH-UHFFFAOYSA-M 0.000 description 1
- 101100130497 Drosophila melanogaster Mical gene Proteins 0.000 description 1
- 101100345589 Mus musculus Mical1 gene Proteins 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
本発明はＨｇＣｄＴｅ基板に形成したダイオードのｐ−
ｎ接合部周辺上に、ＥＣＲ−ＰＣＶＤ （Ｅｌｅｃｔｒ
ｏｎ Ｃｙｃｌ。[Detailed Description of the Invention] [Summary] The present invention provides a p-type diode formed on a HgCdTe substrate.
ECR-PCVD (Electr
on Cycl.
ｔｒｏｎ Ｒｅｓｏｎａｎｃｅ−Ｐｌａｓｍａ Ｃｈｅ
ｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎの略）
Ｓｉ、Ｎ４膜（以下窒化珪素膜と呼ぶ）を被着する
ことにより、界面の安定化と製造工程の再現性を向上し
たものである。tron Resonance-Plasma Che
(Abbreviation for Mical Vapor Deposition)
By depositing a Si, N4 film (hereinafter referred to as a silicon nitride film), the interface is stabilized and the reproducibility of the manufacturing process is improved.
本発明はｌＩｇｃｄＴｅ基板を用いた半導体装置の構造
改良に係り、特にダイオードの接合部の周辺部に窒化珪
素膜を形成することによってダイオードの逆方向特性の
改善と製造工程の再現性とを向上させた半導体装置に関
する。The present invention relates to improving the structure of a semiconductor device using a lIgcdTe substrate, and in particular improves the reverse characteristics of the diode and the reproducibility of the manufacturing process by forming a silicon nitride film around the junction of the diode. The present invention relates to a semiconductor device.
（従来の技術〕
第３図（ａｌ、 （′ｂ１は従来の半導体装置の構造例
を示す要部側断面図であって、（ａ）は標準構造を、（
ｂｌはゲート電極付設型構造を示している。図中におい
て、１はダイオード電極、２は基板のオーミック電極、
３は硫化亜鉛膜、１０はｐ型ＨｇＣｄＴｅより成る半導
体基板、１１は例えばイオン注入により形成したｎ型の
領域、１２は基板表面に露呈したｐ−ｎ接合部をそれぞ
れ示す。(Prior art) FIG.
bl indicates a structure with a gate electrode. In the figure, 1 is a diode electrode, 2 is an ohmic electrode on the substrate,
3 is a zinc sulfide film, 10 is a semiconductor substrate made of p-type HgCdTe, 11 is an n-type region formed, for example, by ion implantation, and 12 is a pn junction exposed on the substrate surface.
第３図ｆａ）は半導体基板１０の界面保護膜として硫化
亜鉛膜を用いた例であり、第３図（ｂ）はｐ−ｎ接合部
１２と硫化亜鉛膜３との界面における界面電位を制御す
るためのゲート電極４が形成された例である。FIG. 3 fa) is an example in which a zinc sulfide film is used as an interface protective film for the semiconductor substrate 10, and FIG. This is an example in which a gate electrode 4 is formed for this purpose.
上記第３図（ａｌのように半導体基板１０の保護膜に硫
化亜鉛膜３を用いた場合は、硫化亜鉛膜３と半導体基板
１０間の密着性は良いが、硫化亜鉛膜３と半導体基板１
０との界面特性は表面準位密度が多くて界面の固定電荷
が一定しないため、ダイオードの暗電流が増大するとい
う問題点を生じていた。When the zinc sulfide film 3 is used as the protective film for the semiconductor substrate 10 as shown in FIG. 3 (al) above, the adhesion between the zinc sulfide film 3 and the semiconductor substrate 10 is good;
Since the interface characteristics with 0 have a high surface state density and the fixed charge at the interface is not constant, this has caused a problem in that the dark current of the diode increases.
これを避けるため、ダイオード１の周辺部にゲート電極
４を形成して界面電位の最適化を図った例が第３図（ｂ
）である。しかしながら多数のダイオードを互いに接近
させて配置する必要のある赤外線検知器等では、ダイオ
ードの増加に伴ってゲート電極４の面積も増え、ゲート
電極４と半導体基板１０との短絡が起こり易く、結果的
に歩留まりが低下するといった問題点があった。In order to avoid this, an example in which a gate electrode 4 is formed around the diode 1 to optimize the interface potential is shown in Figure 3 (b).
). However, in infrared detectors and the like that require a large number of diodes to be arranged close to each other, as the number of diodes increases, the area of the gate electrode 4 also increases, making it easy for a short circuit between the gate electrode 4 and the semiconductor substrate 10 to occur. However, there was a problem in that the yield rate decreased.
なお、硫化亜鉛膜３に代え、保護膜に窒化珪素膜を用い
た場合は、表面準位密度ならびに界面固定電荷密度が共
に小さく、またこの特性の再現性も良いため、半導体基
板１ｏの界面保護膜として非常に有効であるが、窒化珪
素膜と半導体基板１ｏの密着性が低いため、プロセス上
の制限が多いという問題点がある。Note that when a silicon nitride film is used as the protective film instead of the zinc sulfide film 3, both the surface state density and the interface fixed charge density are small, and the reproducibility of these characteristics is also good. Although it is very effective as a film, it has a problem in that there are many process limitations due to the low adhesion between the silicon nitride film and the semiconductor substrate 1o.
本発明はＨｇＣｄＴｅ基板上に形成したダイオードのｐ
−ｎ接合部Ｑ２）周辺部を覆う形で窒化珪素（ＳｉｓＮ
４）の薄膜を形成し、該窒化珪素膜上に窒化珪素以外の
絶縁膜を形成した構造になっている。The present invention is a diode formed on a HgCdTe substrate.
-N junction Q2) Silicon nitride (SisN) is used to cover the periphery.
4) is formed, and an insulating film other than silicon nitride is formed on the silicon nitride film.
本発明の構造によれば、ダイオード周辺の界面特性は窒
化珪素膜で決まり、接続孔の開孔等のプロセスは硫化亜
鉛膜の形成後に行われるので、窒化珪素膜の密着性が低
いために起こる剥離の問題を防止できる。According to the structure of the present invention, the interface characteristics around the diode are determined by the silicon nitride film, and processes such as opening connection holes are performed after the formation of the zinc sulfide film, so this problem occurs due to the low adhesion of the silicon nitride film. Prevents peeling problems.
以下本発明の一実施例を図面に基づいて詳述する。 An embodiment of the present invention will be described below in detail with reference to the drawings.
第１図は本発明の一実施例を示す要部側断面図、第２図
Ｆ８１〜（ｆ）は本発明による半導体装置の製造工程の
一実施例を示す要部側断面図であるが、前記第３図と同
一部分には同一符号を付している。FIG. 1 is a side sectional view of a main part showing an embodiment of the present invention, and FIGS. The same parts as in FIG. 3 are given the same reference numerals.
第１図に示すように、本発明の半導体装置は、ダイオー
ド電極１の周辺部に界面保護用の窒化珪素膜８が形成さ
れた構造になっている。As shown in FIG. 1, the semiconductor device of the present invention has a structure in which a silicon nitride film 8 for interface protection is formed around a diode electrode 1.
従って本発明の場合は、窒化珪素膜８を付着後のリフト
オフは有機溶剤のみで済み、従来ダイオードの接続孔等
の穿孔（エツチング）に用いられる酸、アルカリが窒化
珪素膜８に触れないため剥離等の問題が生じない。Therefore, in the case of the present invention, lift-off after depositing the silicon nitride film 8 can be performed using only an organic solvent, and the acid or alkali conventionally used for drilling (etching) connecting holes of diodes does not come into contact with the silicon nitride film 8, so that the silicon nitride film 8 can be peeled off. No such problems arise.
また窒化珪素膜８と半導体基板１０との界面は固定電荷
が少ないためにほぼフラットバンド状態となり、ダイオ
ードの逆方向特性が改善される。Further, since there is little fixed charge at the interface between silicon nitride film 8 and semiconductor substrate 10, the interface is in a substantially flat band state, and the reverse characteristics of the diode are improved.
以下第２図（ａ）〜（ｆ）を用いて製造工程の一実施例
を説明する。An embodiment of the manufacturing process will be described below using FIGS. 2(a) to 2(f).
■、ポジレジスト塗布工程〔第２図（ａ）〕ｐ−ｎ接合
を形成したｌ１ｇＣｄＴｅからなる半ユ体基板１０上に
ポジレジスト５を塗布する。(2) Positive resist coating step [FIG. 2(a)] A positive resist 5 is coated on a semi-uniform substrate 10 made of l1gCdTe on which a p-n junction is formed.
■、開孔工程〔第２図（ｂ）〕
マスク（図示せず）を介して露光を行い、接合部１２２
周辺部上のポジレジストを除去し、開孔６を形成する。(2) Hole opening process [Fig. 2(b)] Exposure is performed through a mask (not shown), and the bonding portion 122 is exposed to light through a mask (not shown).
The positive resist on the periphery is removed and an opening 6 is formed.
■、窒化膜形成工程〔第２図（Ｃ）〕
ポジレジスト５および開孔６の上に窒化珪素膜８を形成
する。この窒化珪素膜８は、低温で堆積できるＥＣＲ−
ＰＣＶＤ法により形成した。(2) Nitride film forming step [FIG. 2(C)] A silicon nitride film 8 is formed on the positive resist 5 and the openings 6. This silicon nitride film 8 is made of ECR-
It was formed by the PCVD method.
■、リフトオフ工程〔第２図（ｄ）〕
リフトオフにより、ポジレジスト５および該ポジレジス
ト上の窒化珪素膜８を除去する（この工程によりｐ−ｎ
接合部１２周辺部上には窒化珪素膜８のみが残ることに
なる）。(2) Lift-off process [FIG. 2(d)] Lift-off removes the positive resist 5 and the silicon nitride film 8 on the positive resist (this process removes the p-n
Only the silicon nitride film 8 remains on the peripheral portion of the joint portion 12).
■、硫化亜鉛膜付着工程〔第２図（ｅ）〕次に硫化亜鉛
膜３を全面にわたって形成する。(2) Zinc sulfide film attachment step [FIG. 2(e)] Next, a zinc sulfide film 3 is formed over the entire surface.
この保護膜は硫化亜鉛膜に代えて、自然酸化膜を形成さ
せ、その上に酸化険阻膜を形成しても良い。This protective film may be a natural oxide film instead of the zinc sulfide film, and an oxidation barrier film may be formed thereon.
■、電極形成工程〔第２図（ｆ）〕
ダイオード接続孔および基板接続孔を穿孔し、ダイオー
ド電極ｌならび乙こオーミック電極２を形成する。(2) Electrode forming step [FIG. 2(f)] A diode connection hole and a substrate connection hole are drilled, and a diode electrode 1 and an ohmic electrode 2 are formed.
本発明によれば、ｐ−ｎ接合部周辺部を安定化でき、且
つ保護膜の剥離等の問題が解消し、またゲート電極を設
ける必要が無いため、？！！造工程の再現性１歩留まり
の向上に有効である。According to the present invention, the peripheral area of the pn junction can be stabilized, problems such as peeling of the protective film can be solved, and there is no need to provide a gate electrode. ! ! It is effective in improving the reproducibility 1 yield of the manufacturing process.
第１図は本発明の一実施例を示す要部側断面図、第２図
（ａ）〜（ｆ）は本発明の製造工程の一実施例を示す要
部側断面図、
第３図（ａｌ、 ０））は従来の半導体装置の構造例を
示す要部側断面図である。
図中、ｌはダイオード電極、
２はオーミック電極、
３は硫化亜鉛膜、
４はゲート電極、
５はポジレジスト、
６は開花、
８は窒化珪素膜、
１０は半導体基板、
１１はイオン注入領域、
１２は基板表面に露呈したｐ−ｎ接合部、８ヤビ■ｆ榎
１１ イオ〕オＬへ４匂を八゛
滲発顛Ｙ更将ダ撞
第１図
１Ｑ３ Ｌｂｌ第？図FIG. 1 is a side sectional view of the main part showing an embodiment of the present invention, FIGS. 2(a) to (f) are side sectional views of the main part showing an embodiment of the manufacturing process of the invention, and FIG. al, 0)) is a side sectional view of a main part showing a structural example of a conventional semiconductor device. In the figure, l is a diode electrode, 2 is an ohmic electrode, 3 is a zinc sulfide film, 4 is a gate electrode, 5 is a positive resist, 6 is a bloom, 8 is a silicon nitride film, 10 is a semiconductor substrate, 11 is an ion implantation region, 12 is the p-n junction exposed on the substrate surface, 8 Yavi ■ f Enoki 11 Io] O L 4 odor is exuded 8 Y 4 O L 1 Fig. 1 Q3 Lbl No. figure
Claims (1)
極（１）のｐ−ｎ接合部（１２）周辺部を覆う形で、窒
化珪素膜（８）を形成し、該窒化珪素膜（８）上に窒化
珪素以外の絶縁膜（３）を形成してなることを特徴とす
る半導体装置。A silicon nitride film (8) is formed to cover the periphery of the p-n junction (12) of the diode electrode (1) formed on the HgCdTe substrate (10), and nitride is formed on the silicon nitride film (8). A semiconductor device comprising an insulating film (3) made of a material other than silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61215276A JPH0746734B2 (en) | 1986-09-11 | 1986-09-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61215276A JPH0746734B2 (en) | 1986-09-11 | 1986-09-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6370461A true JPS6370461A (en) | 1988-03-30 |
| JPH0746734B2 JPH0746734B2 (en) | 1995-05-17 |
Family
ID=16669630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61215276A Expired - Lifetime JPH0746734B2 (en) | 1986-09-11 | 1986-09-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0746734B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0286177A (en) * | 1988-09-22 | 1990-03-27 | Fujitsu Ltd | Photoelectric converter |
| EP2213529A1 (en) * | 2009-02-03 | 2010-08-04 | Mazda Motor Corporation | Seatbelt device of a vehicle, arranging structure of seatbelt device, method of providing a seatbelt device in a vehicle, and vehicle equipped therewith |
| CN102778818A (en) * | 2012-06-25 | 2012-11-14 | 中国科学院上海技术物理研究所 | Photoetching method for preparing tellurium-cadmium-mercury deep-hole table facet chip film |
-
1986
- 1986-09-11 JP JP61215276A patent/JPH0746734B2/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0286177A (en) * | 1988-09-22 | 1990-03-27 | Fujitsu Ltd | Photoelectric converter |
| EP2213529A1 (en) * | 2009-02-03 | 2010-08-04 | Mazda Motor Corporation | Seatbelt device of a vehicle, arranging structure of seatbelt device, method of providing a seatbelt device in a vehicle, and vehicle equipped therewith |
| US8336914B2 (en) | 2009-02-03 | 2012-12-25 | Mazda Motor Corporation | Seatbelt device of vehicle |
| CN102778818A (en) * | 2012-06-25 | 2012-11-14 | 中国科学院上海技术物理研究所 | Photoetching method for preparing tellurium-cadmium-mercury deep-hole table facet chip film |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0746734B2 (en) | 1995-05-17 |
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