JPS637029A - Double integration type digital/analog conversion circuit - Google Patents

Abstract

PURPOSE:To attain a double integration operation by a single current source by disconnecting a 1st capacitor for a time corresponding to a high-order bit data after the 1st capacitor is connected in parallel with a 2nd capacitor for a time corresponding to a low-order hit data. CONSTITUTION:A DL (low-order data) counter 13 gives a count end signal to a DU (high-order) counter 12 when the count of the counter 13 is finished and the DU counter 12 starts its count after the count end signal is received. Capacitors C1, C2 have the capacitance ratio of 2<m>-1:1, and the capacitor C2 is disconnected from the parallel circuit by a switch 24. In receiving an input digital signal D and inputting split data DU, DL respectively to the counters 12, 13, the counter 13 starts counting and an integration output Vout is I(t1-T 0)/2<m>C2. Then the counter 12 starts counting and the integration output Vout is I(t2-T1)/C2. That is, the integration output Vout with respect to the input digital signal D acts like the double integration operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) This invention relates to a double-integrating digital-to-analog conversion circuit.

(Prior art) As is well known, a digital signal with a sampling frequency fs and a number of bits N is processed using an integral type digital analog (hereinafter referred to as D/analog).
In order to perform D/A conversion in the conversion circuit (abbreviated as A), the counter clock frequency f CKゲf CK≧2' f
Set to s. Here, when the number of bits N is large, the clock frequency fcK becomes very large, making it particularly difficult to integrate the D/A conversion circuit into an IC. Therefore,
A double integral type is often used in which a digital signal is divided into upper Nm bits and lower m bits for processing. Figure 3 shows its configuration.

In FIG. 3, an N-bit digital signal is first divided by a divider 11 into N-m bits of upper data DU and lower m bits of lower data DL.
2.13 is entered. These counters 12, 13 count input data based on the clock CK, and while counting, output ON control signals PI, P2 to set the switches 14, 15 in the ON state. These switches 14 and 15 are for deriving integrated currents 11B and 117 output from constant current sources 16 and 17, respectively.

116.117 is set to 2mΦIII. These integrated currents 11[1, 117 are input to an integrator 18 consisting of an integrating capacitor C1 and an operational amplifier Al.

This integrator 18 integrates the input current and generates an analog voltage V
It is led out to output terminals 19a and 19b as out.

That is, ]-input digital signal is D-2m-D
It is expressed as U+DL. Among these, the count time T1 of the counter 12 inputting the upper data DI becomes DU/fCK,
The count time T2 of the counter 13 inputting the lower data DL becomes DL/fcK. These count times are the integral current output times of the constant current sources 16 and 17, respectively.

Therefore, the two integrated currents 11B = 2 m-1, I
17-1 When the delay is delayed by 18 minutes, the integral output Vout becomes (however, Vout=0 at the start of integration), and an analog voltage proportional to the human input digital signal is obtained. If N is an even number, if m-□ is selected, the maximum data value will be 2, and the clock frequency fCK will be fCK≧2”
*fs should be satisfied. N is such a double integral type D/
The A conversion circuit can lower the clock frequency fCK compared to the integral type D/A conversion circuit, and when the number of bits N of the input digital signal is an even number, it is 1/2, and when it is an odd number, however, as described above. Conventional double integral type D/A
The conversion circuit requires two current sources with a current ratio of 1:2m. Here, there is an error in the current ratio, and (
1+ε): 2m, as shown in FIG. 4, an error of (2m-1)·ε will occur in the integral output V out when the data shifts from 2m-1 to 2m, for example. Since this error is output as noise, the accuracy of the current ratio must be increased to prevent this. However, it is extremely difficult to achieve both high accuracy and a large current ratio of 1:2 m.

(Problems to be Solved by the Invention) This invention improves the point that conventionally required multiple current sources with highly accurate current ratios, eliminates the need for highly accurate current ratios, and has a simple configuration. It is an object of the present invention to provide a double-integration type D/A conversion circuit capable of performing double-integration operation.

[Object of the Invention] (Means for Solving the Problems) A double integration type D/A conversion circuit according to the present invention converts an N-bit input digital signal into N-m bits of upper bit data and m bits of lower bit data. means for dividing into bit data, a constant current source that outputs - constant current I, C1:C2-(2m-
1): an integrator that has a parallel circuit of first and second capacitors CI and C2 having a capacity to ratio of 1, and obtains a charging voltage by supplying the - constant current I to the parallel circuit for a certain period of time; , a switch for disconnecting the first capacitor C1 from the parallel circuit; controlling this switch; and connecting the first capacitor CI in parallel to the second capacitor C2 for a time corresponding to the lower bit data; The time period corresponding to the upper bit data of the first capacitor C1
The present invention is characterized by comprising a control means for disconnecting the parallel circuit from the parallel circuit.

(Function) In the double integration type D/A conversion circuit having the above configuration, when the first capacitor CI is connected in parallel to the second capacitor C2 by switch control, the capacitance of the parallel circuit is C
Since I +C2=2mC2, the analog voltage Vout output from the integrator is Vout-1-t/2
It is C2.

Further, when the first capacitor C1 is disconnected from the parallel circuit by switch control, the capacitance of the parallel circuit is 02
Therefore, the analog voltage V o output from the integrator
ut becomes Vout = I - t/C2. Therefore,
When the input digital signal is only low-order bit data, the first capacitor C1 is connected in parallel to the second capacitor C2 to perform the integration operation, and when there is high-order bit data, after the integration operation of the low-order bit data is completed. , the first capacitor C1 is separated from the parallel circuit to perform an integration operation on the first-order bit data, and a double integration operation is performed using a single current source.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. However, in FIG. 1, the same parts as in FIG. 3 are denoted by the same reference numerals, and only the different parts will be described here.

FIG. 1 shows a configuration in which the present invention is applied to the double-integration type D/A conversion circuit shown in FIG. A count end signal is sent, and the DU counter 12 performs a counting operation after receiving the count end signal. The outputs Pl and P2 of both counters 12 and 13 are both connected to switch 2 via OR gate 20.
1 control input. This switch 21 supplies an integrated current 122 (=I) outputted from a constant current source 22 to the (-) input terminal of an operational amplifier A2 forming an integrator 23. This integrator 23 is the (10) of the operational amplifier A2.
The input terminal is grounded, and a parallel circuit of capacitors C1 and C2 is connected between the (-) input terminal and the output terminal. Capacitors C1 and C2 have a capacitance ratio of 2m-171, and capacitor C2 can be disconnected from the parallel circuit by a switch 24. The switch 24 is controlled on/off by the output P2 of the DL counter 13. It is assumed that the frequency of the input clock CK=of the counters 12 and 13 used here is fCK''.

The operation of the above configuration will be described below with reference to FIG.

First, in the integrator 23, the capacitance Cc of the parallel circuit of capacitors C1 and C2 when the switch 24 is on.
The capacitance ratio of capacitors C1 and C2 is 01:02-(
2m-1):1, so it is expressed as Cc -C10C2 = (2m-1+1)C2 2mC2. Further, when the switch 24 is set to the off state and C1 is disconnected, the capacitance Cop of the parallel circuit is Cop -C2. In other words, the capacitance ratio between Cc and Cop is 2m=1. Therefore, the total charge Qc charged in the capacitor Cc when the switch 24 is in the on state is: From this state, the charge charged in the capacitor 1tcop when the switch 24 is set to off is QO -+p
Since C1 is disconnected and only capacitor 02 is connected to the output, it becomes as follows. Therefore, the output V out of the integrator 23 is
When the switch 24 is on, the following holds true, and when the switch 24 is off, the following holds true. From the above, it can be seen that the switching operation of the switch 24 enables double integration operation with one current source 22.

In the above configuration, an input digital signal is given, and divided data DU are sent to the counters 12 and 11, respectively.

When DI is input, the square counter 13 starts a current operation. The counter 13 starts counting operation (time tO) as shown in FIG.
Until 2 hours (-DL/fCK-) have passed (time t1)
, outputs an on control signal P2. During this time, both switches 21 and 24 are set to the on state by P2, so
If to-0 is Vout-0, the integral output v out is I (tl-to)72 as shown in FIG. 2(c).
It becomes mC2.

When the DL counter 13 finishes counting operation (
At time t1), a count end signal is applied to the DO counter I2, thereby causing the counter 12 to start counting. As shown in FIG. 2(b), the counter 12 starts counting operation (time tl) for T1 time (-
The ON control signal PL is output until DO/fcK-) has elapsed (time t2). During this time, switch 2 is
I is set to the on state, but since P2 is not output, the switch 24 is in the off state. Therefore, the integral output V out is I (t
2-tl)/C2. In other words, the integral output V out for the input digitized signal is as follows, resulting in a double integral operation.

In the above configuration, in order to perform the conversion process within the same time as in the case of FIG. , in the case of an odd number, it is necessary to multiply by N/L (L is the larger value of m or N-m).

In this way, the double-integration type D/A conversion circuit with the above configuration can perform double-integration type operation with a simple configuration using only a single current source, so it can achieve a highly accurate current ratio. This eliminates the need for a current source.

[Effects of the Invention] As detailed above, according to the present invention, there is provided a double integration type D/A conversion circuit that does not require high accuracy of current ratio and can perform double integration operation with a simple configuration. can be provided.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a double integration type D/A conversion circuit according to the present invention, FIG. 2 is a diagram for explaining the operation of the same embodiment, and FIG. Heavy integral type D/A
FIG. 4 is a block circuit diagram showing the configuration of the conversion circuit, and is a diagram for explaining the drawbacks of the conventional circuit. 11... Divider, 12.13... Counter, 14.
15.21゜24...Switch, 1 [1, 17, 22
...Constant current source, 18.23...Integrator, C, C1,
C2... Integrating capacitor, Al. A2... operational amplifier, D... input digital signal, D
U... Upper data, DL... Lower data, Pl, P
2...On control signal, V out...analog voltage. Applicant's agent Patent attorney Takehiko Suzue 11 1st floor

Claims (1)

[Claims] A means for dividing an N-bit input digital signal into N-m bits of upper bit data and m bits of lower bit data, a constant current source that outputs a constant current I, and C1:C2=(
2^m-1): has a parallel circuit of first and second capacitors C1 and C2 with a capacitance ratio of 1, and an integral that obtains a charging voltage by supplying the constant current I to the parallel circuit for a certain period of time. a switch that disconnects the first capacitor C1 from the parallel circuit; and a switch that controls the switch to disconnect the first capacitor C1 from the parallel circuit for a time corresponding to the lower bit data.
1 to the second capacitor C2, and then disconnecting the first capacitor C1 from the parallel circuit for a time corresponding to the upper bit data. Digital/analog conversion circuit.