JPS6369316A - High voltage drive circuit - Google Patents

Abstract

PURPOSE:To prevent dielectric breakdown even if a voltage being an ON dielectric strength of a FET or over and being an OFF dielectric voltage or below is impressed to a circuit of the output stage by connecting a resistor symmetrically between a P-channel FET and an N-channel FET. CONSTITUTION:One end of resistors R1, R1 is connected to the source of FETs 4, 5, a voltage being a half or over of the impressed voltage (VH-VL) is impressed to the resistors R1, R2 and only a voltage being the ON-state dielectric voltage or below is impressed to the FETs 4, 5 in ON-state by selecting the resistor R1 as the interval resistance RP or over in the transient state and selecting the resistor R2 as the internal resistance RN or over and no breakdown is caused. Even in this case, when the internal resistances RP, RN are small, most of the voltage (VH-VL) is impressed to the resistors R1, R2 by selecting the resistors R1, R2 as[(VH-VL)/(R1+R2+RP+RN)]<=IM, and no breakdown voltage of the FETs 4, 5 being in on-state is not induced, where VH is a high voltage potential, VL is a low voltage potential and IM is a value of peak currents of the FET which is smaller.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to high voltage drive circuits used in true chamber discharge tubes, electroluminescence, inkjet printers, and the like.

2. Description of the Related Art With the recent development of MOS type FET technology, MOS type FETs have come to be used in high voltage drive circuits.

Some of these circuits are those in which conventional bipolar transistors are replaced with MOS FETs, but in order to reduce the power consumption of the drive circuit and improve the output waveform, as shown in Figure 3, P-channel MOS type FET104
Then, a push-pull type drive circuit using an N-channel MOS FET 105 came into use. The operation of the conventional high voltage drive circuit will be described below with reference to FIG.

This is a circuit that matches the input gate level of MOS type FETs 104 and 105 on each side of vL.

04 is a P-channel MOS type FET, and 105 is an N-channel MOS type FET.

The operation of the above configuration will be explained below with reference to the time chart of FIG. 4.

First, when the input signal becomes logic ``1'', the inverter 10
The output of 1 becomes a logic 1'0'', and therefore the outputs of level shifters 102 and 103 become a logic 0''.

On the other hand, the P-channel MOS type FET 104 is in the ON state, and since it is an N-channel MOS type FET 105, the O
The state becomes FF. Therefore, the output has a potential of vH.

Next, when the input signal becomes logic "0", the inverter 10
The output of 1 becomes logic “1”, therefore, level shifter 1
The outputs of 02 and 103 become logic 11". Therefore, the P channel MOS type FET 104 becomes OFF state, the N channel MOS type FET becomes ON state, and the output becomes vL potential. Here, the potential difference of (vH - VL) is And the withstand voltage when 105 is OFF must be lower than that.

Problems to be Solved by the Invention Some MOS FETs have a specified breakdown voltage between the drain and source when ON and a breakdown voltage when OFF. Generally, (withstand voltage when ON) < (when OFF) pressure resistance).

Therefore, when the applied voltage (VH-VL) of the drive circuit is used under the condition of (withstand voltage when ON) < (VH - VL) < (withstand voltage when OFF), the drive circuit shown in Fig. 3 has the following: The following problems arise. In other words, when the input signal changes from logic 10" to logic 1", FET 104 changes from OFF state to OFF state.
Changes to N state, FET】05 turns from ON state to OFF
make a change in state. Then, at a certain timing, the FET 104 and the FET 105 may both be in the ON state.

At this time, since the applied voltage (VH-VL) is higher than the withstand voltage when ON, FET 104 and FET 105 will be destroyed. The same thing can be said when the input signal changes from a logic level of ``0'' to ``0''.

The present invention solves the above problems of the prior art, and aims to prevent the FET from being destroyed even if a voltage higher than the withstand voltage when the FET is turned on is applied to the drive circuit. It is.

Means for Solving the Problems The present invention provides a P-channel MOS in the output stage of a high voltage drive circuit.
The above object is achieved by connecting resistors between the source of the FET and the source of the N-channel MOS FET.

Function: The present invention has the above-mentioned configuration so that both FETs are turned on instantaneously.
When the condition is reached, voltage is applied to these resistors and the FET
It is possible to prevent breakdown of withstand voltage.

Embodiment One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an output section in one embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of the output transistor and load of FIG. 1.

In FIG. 1, VH is a high voltage potential, vL is a low voltage potential, and a voltage of (VH-VL) is supplied to the circuit.

In the figure, 1 is an inverter, 2 and 3 are level shifters, 4 is a P-channel MOS FET, and 5 is an N-channel MOSFET.
It is an S-type FET, and between the breakdown voltage characteristics of FET 4 and FET 5 and the supply voltage (VH-VL), (BE resistance when ON) < (VH-VL) < (OFF
(7) withstand voltage) is satisfied. Level shifters 2 and 3 convert the signal level output from inverter 1 to the gate input level of P-channel FET 4 and the gate input level of N-channel FET 5, respectively. R1 and R7 are resistors, and one end is FET4
and the source side of FET 5, and the respective ends are connected to serve as an outlet for the output signal.

Further, 6 is a load, and the other end of the load is connected to the potential Vc.

Next, in FIG. 2, 14 is the P-channel FET of FIG.
4 is the equivalent circuit, and 15 is the N-channel FE in Fig. 1.
This is an equivalent circuit of T5. In the figure, RP and RN are the respective FEs.
It is the internal resistance when T is ON, Sp and SN are the respective switches, and (IP)M and (IN)M are the forward current values of the respective FETs. 1M is the smaller value of (IP)M and (IN)M. RL is the resistance value when the load 6 in Fig. 1 is resistive, cL is the capacitance when the load 6 is capacitive, LL is the ingetatance when the load 6 is inductive, and D,', D, are Both are diodes, and the other end is connected to vH%vL for voltage absorption.

The operation of the above configuration will be explained below.

In the steady state, as shown in the conventional example, when the input signal is logic -0, the output signal becomes L potential, and when the input signal is logic 11, the output signal becomes VH. . At this time, when one FET is in the ON state, the other FET is always in the OFF state.
Since the FET is in the FF state, the applied voltage (VH-VL) is applied to the FET in the OFF state, and the FET in the ON state does not undergo voltage breakdown.

On the other hand, at the time of a transient condition, that is, when the input signal changes from logic 0 to 11, and from logic IN to 0, P-channel FET 4 and N-channel FET 5 are instantly turned on. It is possible that this is happening.

Generally, in a MOS type FET, it is considered that (withstand voltage of ONBS)≧(withstand voltage when OFF)/2. Therefore, in a transient state, if the value of resistor R8 is set equal to or higher than the value of internal resistor RP, and the value of resistor R7 is set equal to or higher than the value of internal resistor RN, then half or more of the voltage (VHVL) applied to resistors R1 and R2 is set. In FETs 4 and 5, which are in the ON state, only 7 voltages are applied, which is less than the withstand voltage in the ON state, and this does not lead to breakdown of the withstand voltage.

Also, even in this case, when the values of internal resistances RP and RN are small, [(VH-VL)/(R1+R1+RP-I-RN)
] ≦IM・River... If we choose R1 and R, such that (V
Most of the voltage of HVL) is applied to the resistances of R1 and R7, and does not lead to breakdown of the breakdown voltage of FETs 4 and 5 which are in the ON state.

Next, consider the case where load 6 is connected. First, in the case of a resistive load RL, in a transient state there is a current flowing through the resistor R2 and a current flowing through the resistor RL, so ((VH-VL)/(R1
+R, +RP+RN)] ten ((VH-VL) /(R,
+Rp×Rt,) )≦(Ip)M ・
Song/■ Satisfies /BI It is necessary to select Rl and R2.

However, if we consider RL)R+ and Rt, it matches Equation 0.

Next, in the case of capacitive load cL, ((VH-VL) / (R1+Rp) ) < (I
p)yt, ((VH-VL)/(R, 10RN)]≦(
IN)M ・・・・・・R1 and R2 that satisfy ■ should be selected. However, when the value of C, is small, load 6 cannot be considered as resistive load RL in Fig. 2, R
Although L″>R1, Rffi, formula 0 holds true.

Next, in the case of an inductive load LL, the diode D1,
Since D2 is connected, it is considered a resistive load RL,
■R1 and R2 are selected to satisfy the formula.As is clear from the above explanation, according to this practical example, the output stage P-channel MOS type FET4 and N-channel MOS
By connecting resistors R,,R, between type FET5, (withstand voltage when ON)<[applied voltage: (VHVL)]<
Even if a voltage of (withstand voltage when OFF) is applied, breakdown of the withstand voltage can be prevented.

Effects of the Invention As described above, the present invention includes a P-channel Mos type FET,
In an output stage circuit using an N-channel MOS type FET in a push-pull type, by connecting a resistor symmetrically between the P-channel FET and the N-channel FET, the withstand voltage is higher than the withstand voltage when the FET is ON. Even if a voltage lower than the withstand voltage when OFF is applied to the output stage circuit, breakdown of the withstand voltage can be prevented, which is highly effective.

[Brief explanation of the drawing]

Fig. 1 is a high voltage drive circuit diagram in one embodiment of the present invention, Fig. 2 is an equivalent circuit diagram of the circuit diagram of Fig. 1 in the Tajiki stage, and Fig. 3 is a conventional high voltage drive circuit. 4 is a time chart of the circuit diagram of FIG. 3. 1...Inverter, 2.3...Level thick, 4.
...P channel MOS type FET, 5...N channel M
OS type FET, 6...Load, 14...P channel M
OS type FET equinodal circuit, 15...N channel MOS
Type FET equinodal circuit, R3, R2...resistance. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure j12

Claims (3)

[Claims] (1) A first voltage V_H is applied to the drain side of the P-channel MOS type FET, a second voltage V_L is applied to the drain side of the N-channel MOS type FET, and a second voltage V_L is applied to the drain side of the P-channel MOS type FET.
The ET and the N-channel MOS type FET are connected in a push-pull type, and the difference in the applied voltage (V_H - V_L)
The P-channel MOS type FET and the N-channel M
The resistor R_1 is set to be larger than the smaller value of the ON breakdown voltages of the OS type FET and smaller than the smaller value of the OFF breakdown voltages, and is equal to or higher than the internal resistance value R_P of the P-channel MOS type FET when it is turned on. P channel MOS type FE
connected to the source side of T, and the N-channel MOS type FET
The resistance R_2, which is greater than the internal resistance value R_N when turned on, is the N
A high voltage drive circuit connected to the source side of the channel MOS type FET, and the other ends of the resistors R_1 and R_2 connected to each other to serve as an output end. (2) Peak current of P-channel MOS FET (I_P)
_M and peak current of N-channel MOS FET (I_N)
When the current value of the smaller value of _M is I_M, the resistances R_1 and R_2 are [(V_H-V_L)/(R_1+R_2+R_P+R
_N)]≦I_M The high voltage drive circuit according to claim 1, which satisfies the following. (3) Resistors R_1 and R_2 are [(V_H-V_L)/(R_1+R_P)]≦(I_
P)_M, [(V_H-V_L)/(R_2+R_N)
]≦(I_N)_M The high voltage drive circuit according to claim 1, which satisfies the following.