JPS6367905A - Operational amplifier circuit - Google Patents

Abstract

PURPOSE:To expand an input voltage range up to the limit of a power supply voltage range and to prevent the generation of switching noise by combining current obtained from a pair of 1st differential amplifiers with output current obtained from a pair of 2nd differential amplifiers by a current mirror and adding the combined current to an active load when the pair of the 2nd differential amplifiers exceeds a normal operation range and circuit current is reduced. CONSTITUTION:When in-phase voltage is boosted and becomes fairly higher than a 1st reference voltage, an n-channel MOS transistor(TR) MN4 is turned off and the whole current obtain from an MN3 is allowed to flow into an MN1 and an MN2. Namely a differential amplifier circuit defining the MN1 and MN2 as input TRs and p-channel MOS transistors MP5, MP7 as loads is operated. At that time, current flowing into the MP5 and MP7 is transmitted to an the active load as current flowing into an MP6 and an MP7. Thereby, the circuit sufficiently operates up to the voltage of a terminal 4 as an input voltage. Since the sum of current transmitted to the active load always equal to the current flowing into the MN3, the generation of switching noise can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an operational amplifier circuit configured on an integrated circuit, in particular,
The present invention relates to an operational amplifier circuit that operates stably over an input voltage range up to the power supply voltage.

(Prior Art) Conventionally, the circuit shown in FIG. 2 is well known as an operational amplifier circuit configured on an MO8 integrated circuit. This circuit is
P-channel MOS transistors MPIOI and M
An N-channel MOS transistor MN is used as a differential pair with P102 as an input transistor and MP103 as a constant current source.
A P-channel MO8) transistor MP105 is added as a constant current load to a differential amplifier circuit whose load is a current mirror configured by IOI and MN102.
8) An inverting amplifier having the transistor MN103 as an input transistor is connected, and a phase compensation circuit using RC and CC is added between the input and output of this inverting amplifier. Regarding the lowest input voltage, this circuit operates up to the potential applied to terminal 5, but the upper limit of the common mode input voltage is determined by the following mechanism.

As the common-mode input voltage increases, the drain voltage of MP103 increases, and eventually MP103 stops operating as a constant current source, and the supplied current decreases. Then, the differential amplifier circuit no longer operates normally. When the common mode voltage further increases, MPIOI and MP102 are turned off and this circuit no longer works. Therefore, the upper limit of the common mode input voltage of this circuit is such that it can only operate at a voltage that is lower than the voltage applied to the terminal 4 by the threshold voltage of the input transistors MPIOI and MP102, and a voltage that is usually about 1 V lower. This voltage is approximately 2V, and since the voltage applied to recent highly integrated circuits is about 5V, the operating range is extremely limited.

The circuit shown in FIG. 3 was proposed as a circuit to expand the operating range. The input stage of this circuit is a combination of a differential amplifier whose input is a P-channel MO3) transistor and a differential amplifier whose input is an N-channel MOS transistor.
In the circuit shown in Figure 2, when one constant current circuit stops working, the other one starts working.
IEEE Journal of 5oli
It is described on page 36 of the February issue of dstate circuit. Although this circuit has a somewhat wider operating range than the circuit in Figure 2, it still has a 1.2
It is stated that it can only operate from ■ to 4.7V.

Figure 4 is from the 1985 International Solid State Circuit Conference Digest of Technical Papers (ISSCC'85 DIGEST).
This is a known circuit described on page 137 of 0FTECHNICAL PAPER 5). The input stage of this circuit also includes a differential amplifier with a pnp transistor as an input, and an n
It is a combination of differential amplifiers with pn T-transistor inputs and operates in two modes. The first mode F is when the input voltage is lower than the reference voltage at terminal 306, at which time transistor Q5 is turned off and Q6 and Q
No current flows through the current mirror created by l. Therefore, I, is a constant current source, Ql and Ql are input transistors, Q8, Q9.

It operates as an amplifier circuit that loads a so-called folded cascode stage composed of QIO, Qll, R8, R9, RIO, and R11. Therefore, the operating lower limit voltage of this amplifier circuit is up to the voltage applied to terminal 5. Next, the second mode is entered when the common mode input voltage rises and the transistor Q5 becomes conductive before the constant current III stops operating. Then, engineering is Ql and Q
The signal does not flow through I, but flows through Q5, and the differential amplifier circuit with Ql and Ql as inputs stops operating. This current is Q6 and Q
A current mirror formed by L causes current to flow through Q3 and Q4. In this case, it becomes a so-called folded cascode differential amplifier using Q3 and Q4 as input transistors.

Therefore, the upper limit voltage for operation at this time is the voltage applied to terminal 4. That is, this amplifier has an input range that extends to the entire power supply voltage range.

However, this circuit presents a problem when switching between the two modes mentioned above. That is, in the first mode, all current flowing through R10 and R11 flows through QIO and Qll, respectively, and all current flowing through Q1 and Ql flows through R8 and R9, respectively. Therefore, the current flowing through R8 is the sum of the current flowing through R10 and the current flowing through 01. Next, in the second mode, the current flowing through RIO is the current flowing through R8 and the current flowing through 03. Since the current flowing through R8 and RIO changes in these two modes, it is inevitable that switching noise will be generated at the output when the input voltage crosses this voltage. Therefore, it has the disadvantage of causing waveform distortion when operated as an amplifier.

(Problems to be Solved by the Invention) In circuits according to the prior art, such limitations in the input operating range or generation of switching noise cannot be avoided. SUMMARY OF THE INVENTION It is an object of the present invention to provide an operational amplifier circuit which solves the problems of the prior art, expands the input operating range to the maximum power supply voltage, and does not generate waveform distortion.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the operational amplifier circuit provided by the present invention has a pair of input terminals; control electrodes are respectively connected to these input terminals, and source electrodes are commonly connected. a first differential pair consisting of a transistor pair having a first polarity; a control electrode is respectively connected to the pair of input terminals;
a second differential pair consisting of a pair of transistors having a second polarity whose source electrodes are commonly connected; one end connected to the commonly connected source electrode of the first differential pair and the other end connected to a first voltage source; a constant current source connected to; the respective drain electrodes of the first differential pair as inputs, the second voltage source as a reference electrode, and the outputs respectively input to the drain electrodes of the second differential pair; first and second current mirror circuits connected in a cross-coupled relationship to the terminals; a control electrode connected to a reference voltage source and a source electrode connected to a common connected source electrode of said first differential pair; a transistor having a first polarity; a drain electrode of the transistor is used as an input, and the second voltage source is used as a reference electrode.

a third current mirror circuit having an output connected to a commonly connected source electrode of the second differential pair; one drain electrode of the second differential pair serving as an input and the other drain electrode serving as an output; , a fourth current mirror circuit whose reference potential is the first power supply; an inverting amplifier whose input is the output of the fourth current mirror circuit; and an inverting amplifier interposed between the input and output of the inverting amplifier. It is characterized by having a phase compensation circuit.

(Function) In this circuit, when the second differential amplifier pair exceeds the normal operating range and the circuit current decreases, the first differential amplifier pair takes over the amplification equivalent to the decrease, and the first differential amplifier pair The current of the amplifier pair is combined with the output current of the second differential amplifier pair using a current mirror to obtain the differential amplifier output voltage in addition to the active load, so the input voltage range can be expanded to the power supply voltage range at once. . Furthermore, since the current flowing through the active load is always constant regardless of the common-mode input voltage value, the output voltage of the current mirror circuit does not suffer from switching noise unlike conventional circuits.

(Example) Hereinafter, the present invention will be described in more detail with reference to an example realized on an MO8 type integrated circuit. FIG. 1 is a circuit diagram of this embodiment.

The embodiment shown in FIG.
O3) A first differential pair consisting of transistors MNI and MN2, and a P-channel MO whose gate electrodes are connected to input terminals 1 and 2, respectively, and whose source electrodes are commonly connected.3) A second differential pair consisting of transistors MPI and MP2. vs.
a drain electrode is connected to a common source of the first differential pair;
A second reference voltage of the first and second reference voltages is generated by a reference voltage generation circuit whose source electrode is connected to the first voltage source 5 and whose gate electrode is made up of a series connection of constant current sources ICI, MNIO, and MNll. A constant current source MN3 connected to a voltage and a drain electrode of each of the first differential pair are used as inputs, and a second voltage source 4 is used as a reference electrode.
The drain electrode of 6 is connected to the drain electrode of MP2, the drain electrode of MP8 is connected to the drain electrode of MPI by cross-coupling, and the P-type MO8) transistors MP5, MP6 and M
P7. first and second current mirror circuits each consisting of an MP8; and an N-type MOS transistor having a gate electrode connected to the first reference voltage and a source electrode connected to the common connection source electrode of the first differential pair. MN4 and MN4
The P-type MO8) transistors MP3 and M
a third current mirror circuit consisting of P4; and a fourth current mirror circuit consisting of transistors MN5 and MN6; N-channel MO8) having one drain electrode of the second differential pair as input and the other drain electrode as output; and constant current −
N-channel MO3) with fllXI C2 as the load and the drain electrode of MN6 as the input; an inverting amplifier with the transistor MN7 as the driving transistor; a resistor RC and a capacitor C connected in series between the input and output of this inverting amplifier;
It is realized by a phase compensation circuit consisting of C.

The operation of this circuit will be described first when the common mode input voltage is close to the voltage applied to the power supply 5. At this time, MHI and MN2 are turned off, so the current of constant current source MN3 is M
It flows through N4 to MP4. Then, due to the current mirror effect, a current equal to the current flowing through MP4 also flows through MP3. When the input voltages are equal at terminals 1 and 2, half of the current flowing through MP3 flows through MPI and MP2, which functions as a differential amplifier with MPI and MP2 as input transistors and MN5 and MN6 as active loads. The inverting amplifier in the next stage is for further increasing the gain as an operational amplifier, and does not necessarily have to be this circuit. Further, the phase compensation circuit is intended to operate stably as an operational amplifier with two gain stages. When the common mode voltage increases,
Current begins to flow through MNI and MN2. Since the current flowing through MN3 is constant, the current flowing through MP4 decreases by the value of this current flowing. The currents flowing through MNl and MN2 are connected to MP2 and MPI by current mirror circuits composed of MP5 and MP6 and MP7 and MP8, respectively.
is combined with the drain current of Therefore, the combined current value remains unchanged at half of the current value flowing through MN3.

When the common mode voltage increases further and becomes significantly higher than the first reference voltage, MN4 is turned off and all of the current in MN3 flows through MNI and MN2. That is, it operates as a differential amplifier circuit with MNI and MN2 as input transistors and MP5 and MP7 as loads. At this time, the current flowing through MP5 and MP7 is transmitted to the active load as current flowing through MP6 and MP8. Therefore, this circuit operates satisfactorily up to the voltage at terminal 4 as the input voltage. Furthermore, the sum of the currents transmitted to this active load is always guaranteed to be equal to the current flowing through MN3, and switching noise unlike the prior art does not occur.

In the present invention, a circuit may be used in which the N-channel MOS transistor and the P-channel MOS transistor in the embodiment of FIG. 1 are exchanged. Furthermore, although a MOS transistor is used in this embodiment, the present invention can be realized even if this is replaced with a bipolar transistor. When using bipolar transistors, it is preferable to connect a resistor of several tens of ohms to several hundred ohms in series between the emitter electrodes directly connected to the voltage sources 4 and 5 and between the emitter electrodes and the voltage sources. good.

(Effects of the Invention) According to the circuit of the present invention, operation up to the full electrode voltage, which was impossible with the conventional MO8 technology, is possible. moreover,
Conventional bipolar technology inevitably generates switching noise when switching between operating modes.
According to the present invention, this does not occur.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a CMO8 operational amplifier circuit commonly used in the past, and Fig. 3 is a conventional circuit diagram showing an input range wider than that in Fig. 2. FIG. 4 is a circuit diagram of a known bipolar operational amplifier circuit whose input range can be extended to the full power supply voltage.

Claims (1)

[Claims] a pair of input terminals; a first differential pair consisting of a pair of transistors having a first polarity, each of which has a control electrode connected to these input terminals and whose source electrode is commonly connected; a first differential pair having a control electrode connected to the pair of input terminals; a second differential pair consisting of a pair of transistors having a second polarity, which are connected to each other, and whose source electrodes are commonly connected; one end is connected to the commonly connected source electrode of the first differential pair and the other end is a constant current source connected to one voltage source; the respective drain electrodes of the first differential pair are used as inputs, the second voltage source is used as a reference electrode, and the outputs are respectively connected to the second differential pair; first and second current mirror circuits connected to the drain electrode in a cross-coupled relationship to the input terminal; a control electrode connected to the reference voltage source;
a transistor having a first polarity, the source electrode of which is connected to the commonly connected source electrode of the first differential pair; the drain electrode of this transistor is the input, the second voltage source is the reference electrode, and the output is a third current mirror circuit connected to the commonly connected source electrodes of the second differential pair; having one drain electrode of the second differential pair as an input and the other drain electrode as an output; a fourth current mirror circuit whose reference potential is the first power supply; an inverting amplifier whose input is the output of the fourth current mirror circuit; and a phase compensation interposed between the input and output of the inverting amplifier. An operational amplifier circuit comprising: