JPS6367368B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal detection circuit that samples and detects analog signals and converts them into digital signals.

An electronic meter for water meter reading generates an almost sinusoidal analog signal with a period corresponding to the number of rotations of the meter via a built-in Hall element (see Figure 1 A).
occurs. This analog signal is judged whether it is above or below the reference level V, and is converted into a signal as shown in FIG. 1B. Furthermore, based on this signal, a signal like C is created, and this signal is used to detect the rotation speed of the meter. On the other hand, the signal in Figure 1 (B) is in a pulse form, but this is done in order to save power by intermittently turning on the power to a pulse converting circuit (not shown) that converts A to B to sample the analog signal. This is because this is used to determine whether or not the reference level V is above or below.

In the above conventional example, when the analog signal is at a delicate position near the threshold level V, the output of the pulsing circuit, which is turned on intermittently, becomes unstable, resulting in the output as shown by the dotted line in Figure 1 (b). "1""0"
The output will be unknown at which level it will appear,
Conventionally, this signal was considered to be a valid signal if it was repeated several times in a row at the same level, and fluctuations were ignored. However, if the period of the analog signal mentioned above is sufficiently longer than the sampling period, there is no problem.
When the flow rate of water is large and the rotation of the meter is fast, there is a risk that the effective signal period may be considered to fluctuate, and even if the analog signal changes, it is difficult to know whether the change is from above to below level V or from below to above. The problem was that it was difficult to judge.

Therefore, the number of peaks in the sinusoidal analog signal,
That is, there was a problem in that the signal corresponding to one rotation of the meter could not be accurately determined.

Another related publication is Japanese Patent Application Laid-Open No. 51-86954, which states that when the output of an analog signal source is intermittently sampled to save power, multiple pulses are generated per rotation, and the number of pulses increases with the period. Therefore, there is a problem that the signal corresponding to one revolution of the meter cannot be accurately determined, and power saving cannot be achieved.

The present invention provides a signal conversion device that can reliably follow even when the period of a sinusoidal analog signal fluctuates, and in which the output signal is not affected even if the analog signal is sampled to save power. It is something to do.

The present invention is connected to an analog signal source that generates a sinusoidal analog signal and has a first output and a second output.
a pulsing circuit that generates an output; a logic circuit connected to the pulsing circuit and configured to perform a logical operation on the first output and the second output; an oscillation circuit that generates a sampling pulse signal by using a power supply circuit; a power supply circuit that supplies power to the pulse generation circuit and the analog signal source; a switching circuit connected to the circuit and supplying power intermittently to the pulsing circuit and the analog signal source, the switching circuit being connected to the pulsing circuit and the analog signal source in synchronization with the sampling pulse; The logic circuit is configured to supply power, and the logic circuit is configured by a microcomputer to determine the output level of the pulsing circuit and to determine the output waveform of the analog signal source, the first reference value, and the second reference value. The output pulse is generated by detecting the end of passing through the intersection points with the value in a predetermined order, and the output pulse is held by a loop of the program until the end of passing through each of the intersection points. .

An embodiment will be explained using FIGS. 2, 3, and 4.

FIG. 2 shows a block diagram of the present invention. 1
2 is an analog signal source consisting of a Hall element of an electronic meter, etc. 2 is a pulse generation circuit that receives an analog signal at its positive terminal and generates _two types of pulse signals _. two comparators 3 set at threshold level;
3'. 4 is 2 from pulsing circuit 2
This is a logic circuit equipped with a microcomputer that receives different signals and determines their mutual levels at the timing of generation of signal d to generate one pulse signal.
7 is a power supply circuit, 6 is an oscillator that generates the sampling pulse signal d, and 5 is a relay that is driven to open and close by the signal d, which intermittently transmits the power to the analog signal source 1 and the pulse generator 7 in synchronization with the signal d. .

More specifically, the input analog signal a of the pulsing circuit 2 enters the inputs of two comparators 3 and 3', where it is pulsed with different threshold voltages V ₁ and V ₂ , respectively. Pulse groups having different phases and widths are outputted as b and c. This situation is shown in the timing chart of FIG. Near the intersection of the input analog signal a and the threshold voltage _V1 or _V2 , fluctuations may occur in the output waveform b or c synchronized with the sampling pulse d due to instability of the output due to intermittent power supply, but in other areas Then, when the level of analog signal a is above and below the threshold level, pulse signal groups of "1" and "0" are generated, respectively. The intermediate level between pulse “1” and “0” is
This is an unstable level when the power is not turned on to the pulse generator 2, but at this time there is no sampling pulse d, and the logic circuit 4
Since the output of the pulsing circuit 2 is not judged, there is no problem even if the output is unstable.

These output pulses b and c are further applied to a logic circuit, and the respective levels of pulses b and c are read in synchronization with the sampling pulse. The operational flow of this logic circuit is shown in FIG. In other words, is the level of pulse c = 1? Check → Pulse b level = 1? Check → Pulse b
level = 0? Check → Pulse c level =
0? The output pulse _e1 is generated at a period that satisfies the check flow. This is because the logic circuit 4 detects the peak of the sinusoidal output waveform generated from the analog signal source 1, that is, the elapse of a positive half cycle, and generates the output e ₁ corresponding to one rotation of the meter. be. Figure 5 shows the flow for detecting the trough of the sinusoidal output waveform generated from the analog signal source 1, that is, the passage of a negative half cycle, and generating the output _e2 corresponding to one revolution of the meter. show.
Furthermore, the output _e3 is an example in which the pulse width is changed by changing the threshold voltage. Further e ₄ if necessary
It is also possible to generate a pulse as shown in FIG. In this embodiment, it is determined that a positive or negative half cycle has passed by detecting that the analog signal source's sinusoidal output waveform has passed sequentially through the points that characterize the peaks or valleys, that is, the intersections with the threshold level. As a result, the meter is considered to have made one revolution and output is generated, so it is not affected by fluctuations in the period of the sinusoidal output waveform.Furthermore, the program loops when passing each intersection until the end of the passage. Since the output of the circuit is held, one output signal is reliably generated for each rotation of the meter even if it is intermittently supplied to the output pulse generator of the analog signal source to save power. be able to.

As is clear from the above description, according to the present invention, even if the period of a sinusoidal analog signal fluctuates, it can be reliably tracked, and even if the analog signal is sampled to save power, the output signal will not change. It is possible to obtain a signal conversion device that is not affected.

[Brief explanation of drawings]

Figure 1 is a timing chart of a conventional example, Figure 2 is a timing chart of a conventional example.
3 is a timing chart of signals at each point in FIG. 2, FIG. 4 is a first flow diagram showing the operation of the logic circuit, and FIG. FIG. 2 is a flow diagram of step 2. 1; Analog signal source, 2; Pulsing circuit, 3,
3': Comparator, 4: Logic circuit.

Claims (1)

[Claims] 1 a first comparator connected to an analog signal source that generates a sinusoidal analog signal and generates a first output when the output of the analog signal source exceeds a first reference value; The second smaller than the reference value
a second comparator that generates a second output when the reference value of a logic circuit configured to perform logical operations on the analog signal source; an oscillation circuit connected to the logic circuit to generate a sampling pulse signal; a power supply circuit for supplying power to the pulsing circuit and the analog signal source; a switching circuit provided between the circuit and the pulsing circuit and the analog signal source and connected to the oscillation circuit to intermittently supply power to the pulsing circuit and the analog signal source; The circuit is configured to supply power to the pulsing circuit and the analog signal source in synchronization with a logic operation on the pulsing circuit output of the logic circuit, and the logic circuit includes a microcomputer to perform the pulsing circuit output. Determining the output level of the circuit, detecting that the output waveform of the analog signal source passes through the intersection points of the first reference value and the second reference value in a predetermined order, and generates an output pulse. The signal converting device is further configured to hold the output pulse by a program loop when passing through each of the intersection points until the end of passing.