SU1749899A2 - Differentiating device - Google Patents

Abstract

The invention relates to analog computing and can be used, 2 used in control and automatic control systems. The purpose of the invention is to improve the accuracy of differentiation. The differentiating device comprises an adder 1, an integrator 2, a scaling element 3, a memory unit 4, a comparator 5 and 6, a clock pulse generator 7, a one-shot 8, a compensating voltage source 9, a bias voltage source 10, electronic keys 11–13, And elements 14 - 16, the element is NOT 17, the element is OR 18, the input 19 and the output 20 tires. 1 il.

Description

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The invention relates to analog computing, can be used in control and automatic control systems and is an improvement of the known device according to Aut. No. 1539799.

The known device comprises an adder, an integrator, a memory unit, a clock pulse generator, two electronic components I. two electronic keys, two comparators, a single vibrator, a two-pole compensating voltage source, a two-pole bias voltage source, an input and an output bus. In it, the first (non-inverting) input of the adder is connected to the input bus, the second (inverting) input to the integrator's output, and the output to the information input of the memory unit and the first inputs of the comparators, the second inputs of the first and second comparators are connected respectively to the first and second the outputs of the bias voltage sources, and the outputs with the first inputs 5 of the first and second elements I, whose second inputs are connected to the single output of the one-vibrator, and the outputs from the control inputs of the first and second elec- The tron keys, the information inputs of the first and second electronic keys, respectively, are connected to the first and second outputs of the compensating voltage source, and the outputs to the integrator input, the control input of the memory unit is connected to the output of the clock generator and the single vibrator input; and the output is with the output bus.

The disadvantage of this device is relatively low accuracy, due to the insensitivity of the device to the signals at the output of the adder, not exceeding the amplitude of the bias voltage

The aim of the invention is to improve the accuracy of differentiation

The third element AND, the third electronic key, the mass element, the OR element and the NOT element, the first input of the third AND element are connected to the output of the NOT element, the second one is connected to the device with the one-shot output. and the output with the control input of the third electronic key, whose information input through the scale element is connected to the output of the adder, and the output directly to the integrator input of the first and second inputs of the OR element are connected to the outputs of the first and second comparators, respectively, and the output of the element NOT.

The drawing shows a block diagram of the proposed device

The device contains an adder 1, an integrator 2, a scaling element 3, a memory unit 4, comparators 5 and 6, a clock generator 7, a one-shot 8,

source 9 of compensating voltage, source 10 of bias voltage, keys (electronic) 11-13. elements AND 14 - 16, the element is NOT 17, the element is OR 18, the input 19 and the output 20 tires.

The first (non-inverting) input of the adder 1 is connected to bus 19, the second (inverting) input to the output of integrator 2, and the output directly to the information input of unit 4 and to the first

the inputs of comparators 5 and b, and through the 3rd element information input of the key 13. The second inputs of the comparators 5 and 6 are connected respectively to the first and second outputs of the source 10, and the outputs to the inputs of the element 18 and the first inputs of the elements 15 and 14, respectively, the second the inputs of which are connected to the output of the one-shot 8 and the second input of the element 16, and the outputs to the control inputs of the keys 11

and 12 respectively

The output of the generator 7 is connected to the input of the one-shot 8 and the control input of the unit 4 whose output is connected to the bus

20, the first input of the element 16 is connected to the output of the element 17. connected by its input to the output of the element 18, and the output to the control input of the key 13, the output of which is connected to the input of the integrator 2 and

the outputs of the keys 11 and 12, connected by their information inputs, respectively, with the first and second outputs of the source 9.

Differentiating device operates as follows.

The adder 1 generates the difference between the current value of the input signal and the signal value preceding the current one for a fixed interval

time T The current value of the signal is fed to the first (non-inverting) input of the adder 1 from the bus 19, and the previous one to the second (inverting) input from the output of the integrator 2. The specified difference,

is proportional to the derivative of the input signal, goes directly to the information input of block 4 and the first inputs of comparator 5 and 6, and through element 3 to the information input of key 13.

The generator 7 generates clock pulses with a period of following T, which are fed to the input of the one-vibrator 8 and the control input of block 4. Under the action of the pulses of the generator 7, block 4 memorizes the signal value at its information input and the result of the memory comes from the output of b / ck 4 to bus 20 .

The second input of the comparator 5 receives the bias voltage Vc of positive polarity from the first output of the source 10, and the second input of the comparator 6 is bias voltage - V negative polarity from the second output of the source 10. The output of the comparator 5 forms a signal whose level corresponds to logical 1, if the signal level from the output of the adder 1 exceeds V. If the signal level from the output of the adder 1 does not exceed Vc, then the signal level at the output of the comparator 5 corresponds to logical O. The signal from the output of the comparator 5 is fed to the first inputs of elements 15 and 18.

At the output of comparator 6, a signal is generated that corresponds to logical 1 if the signal level from the output of adder 1 is less than Vc. If the signal level from the output of the adder 1 is not less than Vc, then the signal level at the output of the comparator 6 corresponds to the logical O. The signal from the output of the comparator 6 is fed to the first input of the element 14 and the second input of the element 18.

At the clock points of time under the action of the pulses of the generator 7, the one-oscillator 8 generates pulses with a level corresponding to logic 1, which arrive at the second inputs of the elements 14-16.

If the signal from the output of the adder 1 modulo VK level exceeds, then the signal, the level of which corresponds to logical 1, from the output of comparator 5 (or 6) through element 15 (or 14), during the action of the pulses of one-oscillator 8 through element 15 (or 14) , enters the control input of the key 11 (or 12), as a result of which the compensating voltage level E of positive (or negative) polarity from the first (or second) output of source 9 through the key 11 (or 12) enters the input of the integrator 2. During the time of the action of the one-shot pulse 8, the output voltage gratora increases (or decreases), reducing the mismatch signals at the input of the adder 1 to a level Vc.

The level E of the compensating voltage of the source 9 is chosen so large that during the time of action of the pulse of the one-shot 8 the integrator 2 has managed to work out any error accumulated during the time interval T. The bias voltage level Vc is chosen so small that the error matching process is stable. Element 3 together with key 13 and elements 16-18

provide additional testing of the mismatch between the signals on the first and second inputs of the adder 2 to the zero level.

The signal controlling the closure of the key 13, and hence the connection of the element 3 to the input of the integrator 2, is formed at the output of the element 16. The inclusion of the element 17 between the output of the element 18 and the first

input element 16 provides prevention of the output element 16 signal, the level of which corresponds to the logical 1st in the presence of such signals at the outputs of Comparators 5 or 6, and the connection of the second input element 16 to the output of the one-vibrator 8 ensures the closure of the key 13 only for the duration of the pulse one-shot 8 and open the loop mismatch contour for the remainder

period T,

The transmission coefficient Kz of element 3 is selected from the condition

25

3

This provides, on the one hand, a stable, and on the other hand, a fairly quick processing of the mismatch.

In the known device, the element 3, the key 13 and the elements 16-18 are absent, therefore, the mismatch is tested there only to the level Vc, in the proposed, it is provided more accurate, practically

to the zero level, working out the mismatch. Consequently, the accuracy of storing the signal level at the previous cycle in the proposed device is higher, and hence, the differentiation accuracy is higher.

Claims (1)

Claims of the invention Differentiating device according to the author. St. No. 1539799, characterized in that, in order to improve the accuracy of differentiation, the third AND element, the third key, the scaling element, the OR element and the NOT element, the first input of the third AND element are connected to the output the element is NOT, the second is with the one-shot output, and the output is with the control input of the third key, whose information input is connected through the scale element to the output of the adder, and the output is the integrator input, the first and second inputs of the OR element are connected to the outputs of the first and second comparators, respectively, and the output is connected to the input of the element NOT.