JPS6367367B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a voltage synthesizer tuner comprising:
This invention relates to an automatic tuning tuner that enables accurate tuning.

Conventionally, a voltage synthesizer tuner has an antenna 1, a high frequency amplification stage 2, a mixing circuit 3, an intermediate frequency amplification stage and detection circuit 4, a voltage controlled oscillator 5, and a tuning clock, as shown in FIG. and a voltage synthesizer controller 6 that converts and sets the output frequency of the voltage controlled oscillator 5. In addition, the detection circuit detects the tuning point using S
Input the curve output to window comparator 7,
The output of the window comparator 7 was used as a stop signal when searching for a broadcast station. In this case, for example, the first
As shown in Figure b, when searching in the increasing direction of the broadcast frequency, the tuning point is set at a position a predetermined number of pulses of the tuning clock from the falling edge of the output _S1 of the window comparator 7, and when searching in the decreasing direction of the frequency The tuning point was set at a position a predetermined number of pulses of the tuning clock from the falling edge of the output _S2 of the window comparator 7.

Therefore, the width of the stop signal (width between the outputs S ₁ and S ₂ of the window comparator) and the number of tuning clocks within this width differ for each band of the tuner, and even within one band, it varies depending on the frequency. It's different.

This is because the tuning clock is fixed at 10 to 12 bits and the relationship between the frequency of the voltage controlled oscillator 5 and the tuning clock is not linear.

Therefore, the voltage synthesizer tuner has a drawback that when searching for a broadcast station, even if a broadcast station is detected and the tuning operation is stopped, the position is often not the optimal tuning point of the tuner.

The present invention has been made in view of the above, and an object of the present invention is to provide an automatic tuning tuner which eliminates the above-mentioned drawbacks.

According to the invention, this object can be achieved by counting the tuning clocks present within the stop signal band from the comparator and setting the 1/2 position as the tuning point.

The present invention will be explained below with reference to Examples.

FIG. 3 is a block diagram of the main part of an embodiment of the present invention, and FIG. 3 shows a tuning point detection means.

The tuning point detection means according to an embodiment of the present invention includes flip-flops F ₁ to _{F 3} , F ₇ , a 1/2 frequency divider F ₄ , a 1/8 frequency divider F ₅ , an up/down counter F ₆ , and an AND gate. It consists of _G1 , _G2 , _G4 , _G5 , _G8 to G10, _G13 , _G15 , OR gates _G3 , _{G11 ,} and inverters _G6 , _G7 , _G12 , _G14 .

The flip-flop _F1 stores the up direction search and is set by key input or the like. When flip-flop _F1 is set, AND gate _G1 opens, and the output from external oscillator CK is output as a tuning clock through OR gate _G3 , and at the same time, AND gate _G4 also opens and outputs up and down outputs. also becomes a high potential and is output to the voltage synthesizer 16 to start searching in the upward direction.

Then, when the output _S1 of the window comparator 7 is outputted by the S curve output, the slowdown flip-flop _F2 is set. By setting the flip-flop _F2 , the AND gate _G1 is closed and the AND gate _G2 is opened, and the pulse output obtained by dividing the output pulse from the external oscillator CK by 1/8 by the 1/8 frequency divider _F5 is ANDed. Gate G ₂ and Or Gate
Output as tuning clock through _G3 . Therefore, the search speed for broadcast stations becomes slow. This is the D/A in the voltage synthesizer controller 6.
This is to compensate for the time delay caused by the conversion filter.

Next, the output _S1 of the window comparator 7 changes from a high level output to a low level output. So the AND gate G ₈ opens and the 1/2 divider F ₄ divides the 1/8 divider F ₅
The output pulse of the oscillator CK is further divided by 1/2, and the output pulse of the oscillator CK, whose frequency has been divided by 1/16, is input to the up/down counter _F6 through an AND gate _G10 and an OR gate _G11 . Up/down counter _F6 U/
Since the D terminal is on the high potential side, the up/down counter _F6 performs up counting. During this time as well, the tuning clock is an output obtained by dividing the output pulse of the oscillator CK by 1/8, so the output _S2 of the window comparator 7 eventually changes from a low level output to a high level output. Since the output _S2 of comparator 7 becomes a high level output, the flip-flop
_F3 is set and up/down counter _F6 is set.
As for the CK input, the input from the 1/2 frequency divider _F4 is prohibited, and instead, the output pulse of the oscillator CK whose frequency has been divided by 1/8 by the AND gate _G9 is input.

Furthermore, when the flip-flop _F3 is set, the AND gate _G4 is closed, and the up/down output to the voltage synthesizer 6 and the up/down counter U/terminal become low level inputs.
Both switch in the down direction. Therefore, the direction returns from the point in time when the output _S2 of the window comparator 7 in FIG. 1b is entered.

If the output continues in the down direction, the count contents of up/down counter _F6 will all become 0,
Carry-out output (borrow) occurs. This output passes through AND gate G ₁₅ to set flip-flop F ₇ and output Q of flip-flop F ₇ .
changes from a low level output to a high level output, and at the same time clears flip-flop F ₇ itself by AND gate G ₁₃ , the output Q of flip-flop F ₇
are flip-flops F ₁ , F ₂ , F ₃ and 1/2 divider
The signal is input to the clear terminal of _F4 , and at this point, flip-flops _F1 , _F2 , _F3 and 1/2 frequency divider _F4 are cleared and the search is completed.

The above action can be illustrated in a diagram as shown in FIG. In Figure 3, a is the S curve output, b is the output _S1 , c is the output _S2 , d is the tuning clock, e is the up/down output, f is the carry out output (borrow), g indicates the output Q of flip-flop _F7 .

As a result, the output S ₁ of the window comparator 7 and
During the period when both _S2 outputs are at low level, the tuning clock is divided by 1/2 by the 1/2 frequency divider _F4 and counted by the up/down counter _F6 , and the frequency is counted by the up/down counter F6. In order to return the output _S2 of the window comparator 7 to the output _S1 side of the window comparator 7 by the number of pulses counted from the time when the output S2 changed from a low level output to a high level output, the position where the tuning clock stops is the output of the window comparator 7. It will be located approximately at the center of the low level output period of S ₁ and S ₂ .

Therefore, even if the slope of the straight line part of the S curve is small and the low level output period of the outputs S ₁ and S ₂ of the window comparator 7 is long, the S curve output will not reach the tuning point P.
The optimum tuning point can be obtained as long as the straight line portion is symmetrical with respect to , and the reference level of the window comparator 7 is set to a symmetrical voltage around the zero potential point.

Furthermore, although the above description has been made regarding the case where the frequency goes up, the same configuration can be applied to the case where the frequency goes down.

As described above, according to the present invention, the voltage synthesizer can perform tuning at the optimal tuning point when searching for a broadcast station.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a conventional automatic tuning tuner, FIG. 2 is a block diagram of essential parts of an embodiment of the present invention, and FIG. 3 is a diagram for explaining the operation of the block diagram of FIG. 2. It is. 4...Intermediate frequency amplification stage and detection circuit, 5...Voltage controlled oscillator, 6...Voltage synthesizer controller, 7...Window comparator, _F1 , _F2 , _F3 and _F7 ...Flip-flop, _F4 ...1/2 frequency divider , _F5
…1/8 frequency divider, F ₆ …up/down counter.

Claims (1)

[Claims] 1. In a voltage synthesizer type automatic tuning tuner that searches for a broadcasting station by changing the output of a voltage controlled oscillator using a tuning clock,
A comparator that receives the S-curve output of the FM detection circuit as an input and detects when the signal enters the reception band across the positive tuning point, and when the comparator detects that the signal falls within the reception band, the period of the tuning clock is determined. and a means for counting the tuning clock within the reception band detected by the comparator, and counting a count value of 1/2 of the count value counted within the reception band;
1. An automatic tuning tuner comprising means for setting an optimum tuning point at a location.