JPS59823Y2 - Receiving machine - Google Patents

Description

[Detailed explanation of the idea] This invention relates to a so-called scanning receiver.

For example, some multi-channel transceivers sequentially scan each channel during reception, and stop scanning at the channel where transmission is being performed.

Figure 1 shows an example of a receiving system, where 1 is an antenna, 2 is a high frequency amplifier, 3 is a mixer circuit, 4 is a local oscillation circuit, 5 is an intermediate frequency amplifier, 6 is a detection circuit, and 7 is a low frequency amplifier. , 8 indicates a speaker.

In this case, the local oscillation circuit 4 is configured to be able to switch the local oscillation frequency in, for example, 10 steps by switching the crystal oscillator or by changing the frequency division ratio of the PLL.

Further, 11 is a decimal counter for scanning, and the count contents of this counter 11 are supplied to the local oscillator circuit 4 as a control signal for the local oscillator frequency, and when the count value of the counter 11 is N (0≦N≦9), , (N11) channels are formed.

Furthermore, 12 is a clock pulse generation circuit, from which a clock pulse having a period of about 0.3 to 1 second is taken out, and this pulse is supplied to the counter 11 as a count input.

Reference numeral 13 denotes a scan lock control circuit, which detects the presence or absence of a received signal using, for example, an AGC voltage, and supplies the detection signal as an enable input to the counter 11 to control the counting operation.

Therefore, the counter 11 counts clock pulses, and the count value increases by 1 (after 9, it overflows and becomes 0), so the local frequency changes sequentially in accordance with this count value, As a result, the reception channels change one channel at a time at the clock pulse cycle.

Then, when a certain channel is selected, if there is a reception input, a change in the AGC voltage due to this is detected by the control circuit 13, and the counter 13 stops counting based on the detection signal.

Therefore, the reception status of that channel is locked.

However, if the reset switch S1 is turned on at any time, or if radio waves cannot be received, the locked state is released, and reception channel scanning continues thereafter.

However, in this case, in the receiver of FIG. 1, the first channel period after turning on the reset switch S□ becomes irregular.

That is, the counter 11 counts the rising edge of the clock pulse Pc, and the detection signal Se of the control circuit 13 (enable input of the counter 11) is 5e.
When 5e=0, the counter 11 counts, but when 5e=1, it does not count.

Then, as shown in FIG. 2A or B, for example, the first channel is selected at time t1, but if there is no reception input on this first channel, it is SeO, and at time t1.
2, the count value of the counter 11 is incremented by 1 by the next clock pulse Pc, and the second channel is selected.

Then, if there is a reception input on the second channel, the 5
Since e=1, the counter 11 stops counting,
Thereafter, the reception state of the second channel continues regardless of the clock pulse Pc.

Then, when the reset switch Sl is turned on at an arbitrary time t3, 5e=0, but when 5e=0,
Since the count value of the counter 11 increases by 1, time t3
The third channel will be selected.

Then, at time t4, the fourth channel is selected by the next clock pulse Pc.

Therefore, in this receiver, the reception period of the first channel after the time t3 when the reset switch S1 is turned on, that is, the reception period of the third channel, varies depending on the time t3 when the switch S1 is turned on.

This idea attempts to eliminate such variations.

An example of this will be explained below.

In FIG. 3, a resistor R1 and a capacitor C1 are connected in series between a power supply terminal T1 and the ground, and the anode and cathode of, for example, PUT (Ql) are connected in parallel to the capacitor C1, and the terminal Resistors R2 and R3 are connected in series between T1 and ground, and P is connected at the midpoint of the connection.
A clock pulse generation circuit 12 is configured by connecting the gate of UT (Ql).

Then, the gate of PUT(Qt) is connected to the input terminal of the counter 11.

Furthermore, the AGC voltage is taken out from the intermediate frequency amplifier 5 as a signal indicating the level of the received signal, and this AGC voltage is further supplied to the buffer and shaping inverter Q2, Q3 through the variable resistor R4 for adjusting sensitivity. Been 4th
As shown in the figure, a detection signal Se is formed, and this signal Se
is supplied to the base of the transistor Q4, and its collector and emitter are connected in parallel to the capacitor C1 to form the lock control circuit 13.

In this case, a transistor Q5 is connected to the base of the transistor Q4, and a reset switch S1 is connected to the transistor Q5.

In such a configuration, as shown before time t1 in FIG. 4, when there is no received signal, it is 5e-0, and therefore transistor Q4 is off.

Then, when transistor Q4 is off, capacitor C1 is charged through resistor R1, and its terminal voltage VC
Luka rises, vC-■DD Ninaruto, PUT (Ql)
is turned on, the capacitor C1 is discharged, and when the discharge is finished, it is charged again.

Therefore, the voltage Vc changes in a sawtooth pattern as shown in FIG.

Then, the voltage at the midpoint of the connection between resistors R2 and R3 becomes a divided voltage by these resistors R2 and R3, but PUT(
When Ql) is on, it becomes 0, so this is taken out as a clock pulse Pc as shown in FIG. 4, and is supplied to the counter 11 and counted.

Therefore, each time PUT (Ql) is turned off (each time capacitor C1 is charged), the count value of the counter 11 increases by l, and one channel is scanned.

Then, at time t1, for example, channel 4 is selected, and at this time, if there is a reception input, 5e = 1 immediately, so transistor Q4 is turned on.

If the transistor Q4 is on, the capacitor C1 is not charged and the clock pulse Pc is not generated, so the reception state of the fourth channel continues.

Then, if switch S1 is turned on at an arbitrary time t2, transistor Q5 is turned on, transistor Q4 is turned off, and charging of capacitor C1 starts again from this time t2, and at time t3, the fifth capacitor C1 is charged. Channel is selected.

Furthermore, even if there is no reception input instead of turning on the reset switch S1 at time t2, 5e=0, and the fifth channel is similarly selected at time t3.

Thus, according to this invention, scanning reception and scan lock are performed, but in this case, especially according to this invention, the start of charging at time t3 is always performed from the initial state (Vc = 0). Therefore, the period t3 to t4
is constant regardless of the time t2, and therefore, there is no variation in the reception period t3 to t4 of the fifth channel, which is the first channel after the time t1 when the reset switch S1 is turned on.

Moreover, the configuration for this is simple, and compared to the conventional example,
It does not become particularly complicated.

[Brief explanation of drawings]

FIG. 1 is a system diagram of a conventional example, FIG. 2 is a waveform diagram thereof, FIG. 3 is a connection diagram of an example of this invention, and FIG. 4 is a waveform diagram thereof. 4 is a local oscillation circuit, and 11 is a counter.

Claims (1)

[Scope of utility model registration request] A counter that counts the rise (or fall) of a clock pulse, a local oscillation circuit that forms a local oscillation signal with a frequency corresponding to the count value of this counter, and a local oscillation circuit that forms the above clock pulse starting from a certain initial state. A clock pulse generation circuit, a scan lock circuit that controls the formation of the clock pulse in the clock pulse generation circuit in response to a received input, and a reset switch that releases the scan lock state, forming the clock pulse generation circuit. The clock pulse to be
In the scan lock state, the receiver is fixed to a rising state (or falling state), and when the reset switch is operated, the clock pulse generation circuit starts from the fixed initial state.