JPS6367260U - - Google Patents
Info
- Publication number
- JPS6367260U JPS6367260U JP16017286U JP16017286U JPS6367260U JP S6367260 U JPS6367260 U JP S6367260U JP 16017286 U JP16017286 U JP 16017286U JP 16017286 U JP16017286 U JP 16017286U JP S6367260 U JPS6367260 U JP S6367260U
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- die pad
- semiconductor chip
- pad portion
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986160172U JPH06834Y2 (ja) | 1986-10-21 | 1986-10-21 | 半導体装置用リ−ドフレ−ム |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986160172U JPH06834Y2 (ja) | 1986-10-21 | 1986-10-21 | 半導体装置用リ−ドフレ−ム |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6367260U true JPS6367260U (enrdf_load_stackoverflow) | 1988-05-06 |
JPH06834Y2 JPH06834Y2 (ja) | 1994-01-05 |
Family
ID=31085305
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986160172U Expired - Lifetime JPH06834Y2 (ja) | 1986-10-21 | 1986-10-21 | 半導体装置用リ−ドフレ−ム |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06834Y2 (enrdf_load_stackoverflow) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016134592A (ja) * | 2015-01-22 | 2016-07-25 | Shマテリアル株式会社 | リードフレーム |
JP2019079935A (ja) * | 2017-10-25 | 2019-05-23 | 三菱電機株式会社 | 電力用半導体装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5684360U (enrdf_load_stackoverflow) * | 1979-11-29 | 1981-07-07 | ||
JPS5818948A (ja) * | 1981-07-27 | 1983-02-03 | Toshiba Corp | リ−ドフレ−ム |
-
1986
- 1986-10-21 JP JP1986160172U patent/JPH06834Y2/ja not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5684360U (enrdf_load_stackoverflow) * | 1979-11-29 | 1981-07-07 | ||
JPS5818948A (ja) * | 1981-07-27 | 1983-02-03 | Toshiba Corp | リ−ドフレ−ム |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016134592A (ja) * | 2015-01-22 | 2016-07-25 | Shマテリアル株式会社 | リードフレーム |
JP2019079935A (ja) * | 2017-10-25 | 2019-05-23 | 三菱電機株式会社 | 電力用半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
JPH06834Y2 (ja) | 1994-01-05 |