JPS6367011A - Set/reset flip-flop circuit - Google Patents

Abstract

PURPOSE:To simultaneously prevent two transmission gates from becoming ON, and also, to execute a circuit operation by a one-phase clock, by controlling a second transmission gate by a pulse whose width is narrower than that of a clock, and a reset input signal, in a D-type flip-flop having a first transmission gate of a D input and the second transmission gate for inputting its inverted output to a latch. CONSTITUTION:The first transmission gate TG1 reads a D input by an inversion of a clock CK or a reset signal, and provides it to the second transmission gate TG2 through an inverter IV1. The second transmission gate TG2 reads a signal by an H level of a pulse of a narrow width outputted at the time of rise of the leading edge of the clock CK and an H level of the reset signal, and latches it, when it has become an L level. Also, when the reset signal is in an H level, a set signal is allowed to pass through, therefore, a state shown in the table is taken. By generating an inverted signal of the clock signal in the inside, a one-phase input will suffice, and also, by reading the signal to a latch by the pulse of a narrow width, an edge trigger type is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a set-reset flip-flop circuit.

[Prior Art] FIG. 3 is a circuit diagram of a first conventional set-reset delay type flip-flop circuit, and FIG. 4 is a timing chart showing waveforms of various parts of the circuit of FIG. 3.

In Figure 3, Q, and 02 are respectively p channel M
It is an O9 type field effect transistor (hereinafter referred to as MOSFET) and an n-channel MOSFET, and the sources and drains of each MO3FETQ and Q2 are connected together, respectively, and a transmission gate 1-'T''G.

is formed. Also, Q3 and Q4. Q5 and Q6. Q7
and Q, are transmission gates T G 2 and TG ! having the same configuration and function as the above transmission gate TG formed by MO8FETQ and Q2, respectively. l and T G ,
It is.

The input terminal is connected to MO8FETQ via inverter IV.
MO9FETQ, and Q are connected to each source of I and Q.
, each drain of MOS FET Q , and Q4
and the first input terminal of the AND gate of the ANDNOR gate. This ANDNORI gate ANDNORI is a composite gate of an AND gate and a NOR gate, and the output terminal of this AND gate is connected to the first input terminal of the NOR gate, and the output terminal of this NOR gate is connected to the first input terminal of the NOR gate.
It serves as an output terminal for ANDNOR+.

Clock terminal CK is MOSFET Q2,
Q3. Q.

and G8, while the inverted lock terminals are connected to the gates of MO8FETQ, , Q, , Qe and G7. Also, the set input terminal S is connected to the inverter T.
V5 to the second input terminal of the AND gate of the ANDNORI gate, as well as the ANDNOOR gate AN
It is connected to the second input terminal of the AND gate ANDNOR2, which has the same configuration and function as DNOR+. Furthermore, the reset input terminal R is connected to the second input terminal of the NOR gate of the ANDNOR gate ANDNOR+, and is also connected to the second input terminal of the NOR gate of the ANDNOR gate ANDNOR2. The output terminal of the ANDNOR gate ANDNOR+ is connected to each source of MO8FEi'Q3 and G4 via the inverter IVa, and is connected to the sources of MO8FEi'Q3 and G4 via the inverter IV3.
ETQ5 and Q. connected to each drain of the This M.O.
Each source of 9FETQ5 and G6 is MOSFET
TQ? and G8, and is also connected to the first input terminal of the AND gate of the ANDNOR gate ANDNOR2. This Antono Game-1-AN
The output terminal of D N OR2 is connected to the output terminal Qn+1, and is also connected to MO9FE via inverter rv4.
Connected to each drain of TQ7 and G8.

The truth table of the set-reset delay type flip-flop circuit of FIG. 3 configured as above is shown in Table 1.
The operation of this circuit will be explained with reference to the timing diagram of FIG.

In Fig. 3, both the set input terminal S and the reset input terminal R are at a low level (hereinafter referred to as 7), and the clock signal is OK, while the inverted clock signal C is at a high level (hereinafter referred to as 7). , H.), when
Transmission gates 1'G and TG4 are turned on, while transmission gates TG and TG3 are turned off. Therefore, the signal input to the input terminal is inverted by the inverter IV, and then input to the first input terminal of the AND gate of the ANDNOR gate ANDNOR1 via the transmission gate LTG. The second input terminal of the AND gate of the gate ANDNOR+ is I (and the ANDNOR gate AN
Since the second input terminal of the NOR gate of ANDNOR+ is at L, the signal input to the first input terminal of the AND gate of ANDNOR+ is inverted and output.

Next, when the clock signal CK becomes 11 and the inverted clock signal CK becomes L, the transmission gate TG.

and T G 3 are turned on, while transmission gate 1 - T G
, TG4 turns off. As a result, the output of Antono Game) ANDNOr(1 is the inverter r V 2
, transmission game) TG2 and Andnor Gate ANDNOr
The output of the ANDNOR gate ANDNOR1 is inverted by the inverter 3, and then passed through the transmission gate TG3 to the ANDNOR gate ANDNOR2. It is output to the first input terminal of the gate. Here, Antono Gate)
The second input terminal of the AND gate of ANDNOR2 is ■-
Since the second input terminal of the NOR gate is 1, the ant game 1 of the ANDNOR gate ANDNOR2 is
The J signal inputted to the first input terminal of . is inverted and outputted to the output terminal Qn+1.

Furthermore, when the clock signal CK becomes L again, the transmission gates TO and TG 4 are turned on, while the transmission gates TG and TG 3 are turned off. As a result, the output of the ANDNOR gate ANDNOR2 is transferred to the inverter IV4. The clock signal is held statically by a loop circuit constituted by the transmission gate 1'TG4 and the ANDNOR gate ANDNOR2 until the clock signal rises to H level next time.

Therefore, when the set input terminal S and the reset input terminal R are both connected, the signal input to the input terminal is delayed and outputted at the same level to the output terminal Q n -1-1, and the circuit shown in FIG. It can be seen that the circuit operates as a delay type flip-flop circuit.

Furthermore, when the set input terminal S becomes i-I, the second input terminal of the AND gate of ANDOR gate A and NDNOR2 becomes L, so ANDOR gate A
, N D N OR2 becomes H, and therefore the output terminal Qn-1-1 becomes H. Furthermore, when the reset input terminal R becomes [■] in this state, the second input terminal of the NOR gate of the ANDNOR gate 8NDNOR2 becomes H, so the output terminal Qn+] becomes L and is reset. Therefore, it can be seen that the circuit of FIG. 3 operates as a set-reset delay type flip-flop circuit.

In addition, a CMOS flip-flop circuit (hereinafter referred to as the second conventional example) using a MOSFET transmission gate has been proposed in Japanese Patent Application Laid-Open No. 17719/1982, and in this circuit, two inverter input and output A latch circuit configured by cross-connecting the two terminals, a pulse generation circuit that generates a timing pulse with a minute pulse width for the required time in synchronization with the clock pulse, and a pulse generation circuit that is controlled by this timing pulse and sends a write signal to the latch circuit. A delay type flip-flop circuit is constructed with the transmission gate that transmits data.

[Problems to be Solved by the Invention] However, in the first conventional example described above, a two-phase clock of the clock signal CK and the inverted clock signal α is required to operate the circuit, and the clock speed is The clock signal CK and the inverted clock signal U become very high.
[If a phase difference occurs between the transmission game) TG and TG3 are both turned on, and the signal input to the input terminal is outputted as is to the output terminal Qn+1, which may cause a so-called shogi defeat phenomenon. There is a problem that this causes the flip-flop circuit to become inoperable. Furthermore, the second embodiment has the disadvantage that it is not an edge trigger type.

The object of the present invention is to solve the above-mentioned problems and provide a set-reset flip-flop circuit which is an edge-trigger type that can operate with only a one-phase clock, and which can prevent the above-mentioned chess falling phenomenon. There is a particular thing.

[Means for Solving the Problems] The present invention provides a first transmission gate that transmits an input signal of a flip-flop circuit in response to a clock signal and a reset signal, and a first transmission gate that transmits an input signal of a flip-flop circuit in response to a clock signal and a pulse width of the clock signal in response to a clock signal. a pulse generating circuit that generates a timing pulse with a predetermined pulse width narrower than the timing pulse; and a second transmission circuit that transmits a signal corresponding to the output of the first transmission gate in response to the timing pulse and the reset signal. a gate, and a set signal inputted in response to the reset signal to the second gate.
The present invention is characterized in that it includes a third transmission gate for transmitting data to the transmission gate.

[Embodiment] FIG. 1 is a circuit diagram of a set-reset delay type flip-flop circuit according to an embodiment of the present invention. Components in FIG. 1 that are the same as those in FIG. 3 are given the same reference numerals.

In FIG. 1, Q and Q are a p-channel MO8FET and an n-channel MOSPET, respectively, and the sources and drains of the MO8FETs Q and Q2 are connected together to form a transmission gate TG.

Also, Q3 and Q4. Q5 and Q. .

Q7 and Q8 are the above MO8FETQ and Q, respectively.

The transmission gate TG3. has the same configuration and function as the transmission gate TG formed in the transmission gate TG3. TG, and 'T' G.

The input terminal is connected to the sources of MO8FETQ and Q, and the drains of MO3FETQ and Q are connected to M
It is connected to each source of OS FET Q 5 and Q8, and is connected to the MOS F
Connected to each source of E T Q3 and Q4.

The clock input terminal GK is connected to the first input terminal of NOR gate N0RI, and the set input terminal S is connected to MO9FE.
Connected to each source of TQ5 and Q8. Furthermore, the reset terminal R is MO3FETQ.

MO8FETQ is connected to the second input terminal of the NOR gate N0RI and the first input terminal of the NOR gate N0R2 through the inverter IV4.
Connected to gate 5. The output terminal of the NOR gate N0RI is connected to the gate of the MOS FET Q2, the second input terminal of the NOR gate N0R2, and the first input terminal of the NOR gate NOR3, and also connected to the inverter rv.
5 through MO9);'ETQ.

connected to the gate. The output terminal of the NOR gate N0R2 is connected to the second input terminal of the NOR gate NOR3, and the output terminal of the NOR gate NOR3 is connected to each gate of the MO9FETs Q4 and Q.
It is connected to each gate of MO9FETQ3 and Q8 via Ve. Each drain of MOSFET Qs and Q4 is connected to MOSFET Q? and Q8, and is connected to the output terminal Qy++1 via the inverter IV2, and this output terminal Qn+1
is the MOS FET Q via inverter IV3.
? and connected to the source of Q8.

The truth table of the set-reset delay type flip-flop circuit of FIG. 1 configured as above is shown in Table 2.
The operation of this circuit will be explained with reference to the timing diagram of FIG.

In FIG. 1, there are three Noah gates NORI.

The circuits N0R2 and NOR3 constitute a timing pulse generation circuit, and when the reset input terminal R is on and the clock signal CK is L, both L and I signals are input to the NOR gate NOR3. The output of is L, but when the clock signal CK rises from L to H, the levels of both signals input to both input terminals of NOR gate NOR3 differ by the delay time of the operation of NOR gate N0R2. NOR gate NOR3 outputs an H minute pulse having a pulse width equal to the operation delay time of NOR gate N0R2.Furthermore, in this timing pulse generation circuit, when the reset input terminal R becomes H,
Regardless of the level of clock signal GK, NOR gate N
The output of OR3 becomes T-1.

In the circuit of FIG. 1, the set input terminal S and the reset input terminal R are both connected to the clock signal CK.
When the transmission gate TG is set.

and TG4 are turned on, while transmission gates TG and T
G3 is turned off. Therefore, the signal input to the input terminal is transmitted to the transmission gate TG and the inverter IV +
to the sources of MO8FETs Q3 and Q4 of the transmission gate TGL.

Since this inverter IVI does not have a latch circuit on the input side, the output of the inverter T V + changes from H to L or from L to H as shown in 11 to 15 in FIG. The absolute value of decreases.

Next, when the clock signal GK becomes H, the transmission gate T G
+ is turned off, and the clock signal GK goes low.
At the rise from H to H, the Noah gate N0R is activated as described above.
The H minute pulse having the pulse width of the operation delay time of 2 is the NOR gate NOR3 and the transmission gates TGt and TG.
, and while the H minute pulse is being output, the transmission gate TG is turned on and the transmission gate TG4 is turned off. “With this, M.O.S.F.
The signals input to the sources of E T Q3 and Q4 are
The signal is output to the output terminal Qn+1 via the inverter ■■. Furthermore, when the output of the NOR gate N'OR3 falls to L, the transmission gate TGt is turned off and the transmission gate TG4 is turned on, and the signal output from the inverter IV to the output terminal Qn+1 is transferred to the inverter rv.

The level is statically held by a latch circuit composed of a transmission gate TG and an inverter IVz.

Although inverter IV does not have a level self-holding circuit, it can be seen that it operates statically if it is held only for the time when the timing changes from H to L after clock signal GK becomes I].

Therefore, when both the set input terminal S and the reset input terminal R are present, the signal inputted to the input terminal is delayed and outputted to the output terminal Qn+1, thereby operating the delay type flip-flop circuit.

Furthermore, when the reset input terminal R is H, the transmission gate T G 3 is turned on, and at this time, the NOR gate N0R1
Since the outputs of NOR gate NOR3 and NOR2 are both the same, the output of NOR gate NOR3 becomes H. Therefore, transmission gate T G
2 is turned on, while transmission gate 1-TG is turned off. Here, regardless of the level of the clock signal, the output of the NOR gate N0RI is 17, so the transmission gate TG
, is turned off.

Therefore, the signal input to the set input terminal S is transmitted to the transmission gate '1'G3. The signal is output to the output terminal Qn-1-1 via the inverter TV, transmission gate TG2, and inverter IV. Next, when the reset input terminal R becomes 17,
Transmission gate TG2 is turned off, transmission gate TG is turned on, and the level of its output terminal Qn-1-1 (
J1 is held at least until the time after the next clock signal CK rises from 17 to H until the time after the delay time of the operation of NOR gate N0R2. Therefore, the circuit of FIG. 1 operates as a set-reset delay type flip-flop circuit.

In the embodiment shown in FIG. 1, the input load, so-called fan-in, on the clock input terminal CK is 1. compared to the conventional circuit shown in FIG. In addition to having the advantage of being small, this circuit operates with a single phase clock signal CK. Moreover, the shogi falling phenomenon described in ``-'' does not occur as long as the pulse width of the timing pulse output from the NOR gate NOR3 exists. Therefore, a high-speed set-reset delay type flip-flop circuit can be realized.

In the second embodiment, a latch circuit consisting of an inverter IV, a transmission gate TG4, and an inverter IV2 is provided on the output side of the transmission gate TG2. If the level does not need to be held for more than a given time compared to the clock speed,
Inverter I3 and transmission gate TG may be removed. Note that even with a circuit from which these are removed, a set-reset delay type flip-flop circuit having the above-mentioned effects can be realized.

-15= Table 1 Table 2 (Note) * indicates an arbitrary level.

-1 also- [Effects of the Invention] As detailed above, according to the present invention, the first transmission gate transmits the input signal of the flip-flop circuit in response to the clock signal and the reset signal; and a second transmission gate that transmits a signal corresponding to the output of the first transmission gate in response to the reset signal and the reset signal.
The second transmission gate and the second transmission gate are not turned on at the same time, so that the so-called forward +tt overturning phenomenon can be prevented, and the circuit can be operated using only one phase clock. With this, a high-speed flip-flop circuit can be realized.

Furthermore, a third transmission gate is provided for transmitting a set signal inputted to the second transmission gate in response to the reset signal, thereby realizing a set-reset flip-flop circuit having a dual effect. be able to.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a set-reset delay type flip-flop circuit according to the first embodiment of the present invention, Fig. 2 is a timing chart showing waveforms of various parts of the circuit of Fig. 1, and Fig. 3 shows a conventional example. A circuit diagram of a set-reset delay type flip-flop circuit. FIG. 4 is a timing chart showing waveforms of various parts of the circuit of FIG. 'rG8. TGt+TG3. TGt...transmission gate,
Ql, Qt, Qs, Q4. Q5. Qe, Q7. Qa-M
OS type field effect transistor (M, OS FET)
, IV+, IV2. I V3. I V-, I
V5'''inverter, N0RI, N0R2, NOR
3...Noah Gate.

Claims (1)

[Claims] (1) A first transmission gate that transmits an input signal of the flip-flop circuit in response to a clock signal and a reset signal, and a timing pulse having a predetermined pulse width narrower than the pulse width of the clock signal in response to the clock signal. a second transmission gate that transmits a signal corresponding to the output of the first transmission gate in response to the timing pulse and the reset signal; A set-reset flip-flop circuit comprising a third transmission gate that transmits a set signal to the second transmission gate.