JPS6366068B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MIS (metal-insulator-semiconductor) memory device, and in particular, a gate electrode is used as one electrode, and a channel layer on the semiconductor surface via an insulating film under the gate electrode is used as the other electrode. The target is MIS memory devices that use capacitors as electrodes as storage means.

In order to obtain the capacity as the storage means, it is necessary to apply a power supply voltage to the gate electrode and form a channel layer (inversion layer) on the surface of the substrate.

Conventionally, voltage was supplied to the gate electrode by commonly connecting it to the power supply line of the memory device. Therefore, when selecting semiconductor memory chips to determine insulation defects in the gate insulating film, since the drain of the MIS transistor that constitutes the logic circuit is connected to the power supply line, it is necessary to This made it impossible to perform a pressure test.

For this reason, conventional MIS memory devices have had major reliability problems.

This invention can improve reliability.
Made to provide MIS memory devices.

This invention provides an MIS memory device completed on a chip, by newly providing a bonding pad for supplying a power supply voltage to the gate electrode of a storage capacitor, or by using this pad as a pad for placing a probe needle, as well as for supplying power. This is intended to provide resistance between the pad and the pad.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Reference numeral 1 denotes a MIS memory chip completed on a semiconductor wafer, and is composed of a memory matrix 2 and a peripheral circuit 4 comprising an address buffer circuit, a decoder circuit, a data input/output circuit, and the like.

As shown in the structural cross-sectional view of FIG. 2, the memory matrix section 2 has a gate electrode 10 as one electrode, and a channel layer 11 on the surface of the semiconductor substrate 6 via an insulating film under the gate electrode as the other electrode. The MIS capacitor used as an electrode is used as a memory means, and the drain 7
The memory cells are arranged in a matrix, using MIS transistors as switching means, which are connected to the data line D, the gate 9 to the word line W, and the source 8 to the channel layer 11 of the MIS capacitor. This is what I did.

A bonding pad 3 for supplying a power supply voltage to be applied to the gate electrode of the MIS capacitor is newly provided in addition to the bonding pad 5 for supplying power to the peripheral circuit 4.

As mentioned above, completed on the wafer tip
Configure memory cells as MIS memory device
Since the bonding pad 3 is provided to supply the power supply voltage to the gate electrode 10 of the MIS capacitor,
In other words, only for this bonding pad 3,
Since voltage can be selectively supplied to the gate electrode 10 of the MIS capacitor separately from the peripheral circuit 4, screening can be performed using any high voltage (for example, about 60 V) necessary to determine defects in the insulating film. becomes. Therefore, since it is possible to determine whether a product is defective at the time it is completed on a wafer chip, it is possible to reduce costs and improve reliability.

In other words, the majority (60-70%) of reliability failures in conventional MIS memory devices as described above are due to defects in the gate insulating film, and the gate area of the MIS capacitor occupies more than half of the total area. Therefore, the reliability of the MIS memory device can be further improved.

In addition, the newly installed bonding pad 3 mentioned above
In addition, in the wire bonding process, an increase in the number of external terminals can be prevented by connecting to a common lead terminal with the bonding pad 5 that supplies power to the peripheral circuit 4.

The present invention is not limited to the above-mentioned embodiment, but for example, as shown in FIG.
The gate electrode 10 of the MIS capacitor may be provided with a pad 3' for applying a probe needle, and a resistor R may be provided between it and the bonding pad 5 for power supply.

By setting the value of this resistance R to a value larger than the screening voltage source impedance, a large voltage can be applied to the gate electrode of the MIS capacitor. In the wire bonding process, only the bonding pad 5 may be connected to the power supply lead terminal.

Note that during normal operation, the
Voltage is supplied to the gate electrode of the MIS capacitor, but since this impedance is extremely large, the presence of the resistor R does not affect the voltage supply operation in any way.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the invention, FIG. 2 is a sectional view of the structure of a memory cell, and FIG. 3 is a block diagram showing another embodiment of the invention. 1...MIS memory chip, 2...memory matrix section, 3...bonding pad, 4...peripheral circuit,
5... Bonding pad, 6... Substrate, 7... Drain, 8... Source, 9... Gate, 10... Gate electrode, 11... Channel layer.

Claims (1)

[Scope of Claims] 1. An MIS transistor as a switching means, one electrode constituted by a first electrode, the other electrode facing the one electrode with an insulating film as a dielectric interposed therebetween, and the MIS transistor as a switching means. a memory matrix comprising a plurality of memory cells each including a capacitor as a storage means coupled to a transistor, and in which the first electrode is fixed at a fixed potential determined by a power supply voltage when the memory is in use, and a peripheral circuit;
In the MIS memory device, the MIS memory device includes a power supply voltage supply bonding pad coupled to the peripheral circuit and to be coupled to the power supply voltage supply external terminal, at least the bonding pad being coupled to the external terminal. A pad for applying a test voltage is coupled to the first electrode so that a test voltage independent of the voltage applied to the bonding pad can be applied to the first electrode before bonding. MIS memory device. 2. The MIS memory device according to claim 1, wherein the pad for applying the test voltage comprises a bonding pad to be coupled to the external terminal together with the bonding pad. 3. A test voltage can be applied to the test voltage application pad between the bonding pad and the first electrode substantially independently of the bonding pad, and a memory can be used. 2. The MIS memory device according to claim 1, further comprising resistance means for supplying the power supply voltage of the bonding pad to the first electrode in the above-mentioned state.