JPS6365957B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a flat panel display device, and more particularly to a new improvement of a display device having a configuration in which selective driving active elements corresponding to pixels are integrated and integrally combined with a display medium. It is.

Recently, a display unit has been proposed in which an integrated drive circuit is integrally combined with a flat matrix display device using electroluminescence (EL) or liquid crystal. The drive circuit has active elements corresponding to pixels and is integrated on a single silicon wafer, and partially selectively controls the optical function of the display medium stacked above the silicon wafer. There is. In addition, from the perspective of configuring a display unit with as large an area as possible, attempts have been made to integrate active elements corresponding to the above pixels using SOS (Silicon On Saphire) technology or thin film transistor (TFT) technology instead of silicon wafers. .

However, it is extremely difficult to increase the size of a flat matrix display device that combines the above-mentioned active elements using conventional techniques. In other words, in a configuration in which active elements corresponding to pixels are integrated using a silicon wafer, the size of the display screen is limited by the size of the wafer. From the viewpoint of yield, it is extremely difficult to form a large number of active elements and light emitting points without defects. Also SOS configuration and TFT
Even if a new configuration is adopted, it is difficult to form driving active elements and light emitting points in a number corresponding to the required number of pixels with a high yield, and in the end, the most important goal for this type of display device is to economically obtain a large display screen. This has become a difficult point.

In response to such problems, the present inventors previously filed Japanese Patent Application No. 55-25844 (Japanese Unexamined Patent Publication No. 56-122089).
We proposed a concept for configuring a large-scale display device by combining small-scale display modules. According to the future proposal, by using an IC chip that integrates not only driving active elements corresponding to pixels but also shift registers for addresses as a substrate and stacking a display medium on top of it, it is possible to create a dot matrix for each character, for example. A method is adopted in which display modules are constructed and a required number of display modules are arranged in a matrix to construct a character display device of any size. Therefore, in this case, the display area can be expanded without being limited by the size of the semiconductor wafer, and even if a partial display defect or functional decline occurs, the entire display module can be replaced by replacing only the relevant display module. It is possible to maintain the quality functions of this type of display device, and it is possible to solve the problem of economic efficiency that accompanies the increase in the size of this type of display device.

Here, the present invention further develops the display device having the above-mentioned modular structure, so that even when the display screen is enlarged, selection and control of each display module can be easily performed without complicating the connection wiring between the modules. The object of the present invention is to provide a modular display device that provides a modular display system. Briefly stated, the present invention includes a memory element connected to an input terminal of a module selection signal attached to each display block, which is composed of a plurality of display modules constituting a large display screen, and a memory element connected to an input terminal of a module selection signal. The input/output terminals of the address shift registers are connected in series, and the input/output terminals of each of the block selection storage elements are connected in series, so that module selection signals are sequentially transferred between the block selection storage elements. The present invention is characterized in that the driving of each display module in a sequentially selected display block is selectively enabled. In this case, especially if the memory elements for multiple display blocks are connected in series so that the module selection signals can be transferred sequentially, access to the display module can be achieved simply by controlling the transfer form of the module selection signal between the memory elements. It becomes possible to control operations as appropriate, such as sequential access or high-speed skip access, depending on the displayed content.

Preferred embodiments of the present invention will be described in more detail below with reference to the drawings.

FIG. 1a is a sectional view schematically showing the general structure of a display module used as a basic structural unit of a display device according to the present invention. A semiconductor IC chip 6 is provided with a transparent substrate 4, pixel electrodes 5 arranged in a matrix as described below and corresponding required driving circuit elements integrated therein, a display medium 7 such as a liquid crystal, and a transparent electrode 8 on the lower surface. It is constructed as a laminate of covers 9. Although such a laminated structure itself is not particularly different from conventional display devices incorporating active elements of this kind, in the present invention, the laminated structure is configured as a small-scale display module of one character or several characters. It also differs from conventional ones in that it has an internal address function.

FIG. 1b shows the semiconductor of the display module 1.
6 is a schematic diagram showing an equivalent circuit configuration of circuit elements integrated into an IC chip 6, in this case, 5×7
It has a matrix pixel array of dots. 1st
In FIG. b, P ₁₁ , P _{12 .} . . P ₇₅ are pixel electrodes 5 formed insulated from each other on a silicon substrate 10 of a required size to correspond to this pixel arrangement, and each has an electric field as an active element for selective driving. Effect transistors (FETs) Q ₁₁ , Q ₁₂ ... are connected to each drain electrode of Q ₇₅ . The source electrodes of these driving FETs are connected to the character data shift register 11 via a common X conductor for each column in the vertical direction. This character data shift register 11 has an input terminal 12 for a character data signal CS and a capture timing signal (CTS) for the character data signal.
It has an input terminal 13 and an output terminal 14. Further, each gate electrode of the drive FET is connected to the output of the AND gate circuit 15 via a common Y conductor for each row in the horizontal direction. This AND gate circuit 15
One input of the scanning signal SS input terminal 16
is connected to a scanning shift register 18 having an input terminal 17 for a scanning signal acquisition timing signal STS, and the other input is a module selection signal MAS.
is led out to the input terminal 19 of.

A display module as shown in FIG. 1a is completed by forming a space in which a display medium such as a liquid crystal and a transparent counter electrode are enclosed on a silicon substrate 10 on which the circuit elements as described above are integrated. do. In the illustrated example, this display module has a display function for one character using 5×7 dots.

FIG. 2 is a schematic diagram showing an example of the configuration of a modular display device of the present invention in which a plurality of single character display modules as described above are arranged vertically and horizontally, and in this case, 32
256 display modules DM ₁ to DM ₂₅₆ are arranged in a matrix of 32 horizontal columns and 8 vertical rows to form a display screen of 8 lines of characters. Display module with 32 items per row DM ₁ - DM ₃₂ ... DM ₂₂₅ - DM ₂₅₆
are mounted on a common sub-unit board and constitute display blocks DB1 to DB8 in row units, and terminals 13, 16, 17 and 19 of display modules included in each block are common in row units on the sub-unit board. It is connected to the.
Further, the character data shift register in each display module has its output terminal 14 connected in series to the input terminal 12 of an adjacent register.

Each of the row unit display blocks includes memory elements MAM1 to MAM1 for module selection, which is a feature of the present invention.
MAM8 is attached. In the illustrated example, this memory element has a configuration of a so-called JK flip-flop (FF) circuit, and has a selection signal input terminal J.
and an input terminal CL for a timing signal that instructs to take in the selection signal, and an input terminal K for an inverted signal.
It also has an output terminal Q for a selection signal.
A module selection instruction signal is supplied to the J terminal of the memory element MAM1 attached to the display block DB1 in the first row.
A terminal 20 for inputting MSS is connected, and the MSS terminal 20 is also connected to the K terminal via an inverter IN. Further, the output Q terminal of each memory element is commonly connected to the module selection signal input terminal 19 of the display module included in the corresponding row block, and is cascade-connected to the J input terminal of the memory element MAM2 in the next row. There is. Therefore, the eight memory elements MAM1 to MAM8 have an eight-stage shift register configuration as a whole, and the first memory element
It becomes possible to sequentially transfer the module selection instruction signal input from the MSS terminal 20 to the J terminal of MAM 1 to the CL terminal of each element by the timing signal TTS for signal acquisition commonly applied from the terminal 21.

In the device shown in FIG. 2, the input terminal 12 for character data for the display module in the first column of each row is connected in parallel to the input terminal 22 for the character data signal CS. Terminals 13, 16 and 17 of the display module are also commonly connected as a whole to terminal 2 of the character data capture timing signal CTS.
3. It is led out to a terminal 24 for the scanning signal SS and a terminal 25 for the timing signal STS for capturing the scanning signal. Thus, the display device shown in FIG.
In total, it has six signal input terminals.

Next, the operation of the above modular display device will be explained. FIG. 3 is a timing chart for explaining an example of operation using the line sequential access method, and each signal waveform is shown with a code corresponding to the signal code written on each signal input terminal section of the device in FIG. .

Now, when the module selection instruction signal MSS is input from the external interface circuit side, this signal is applied from the terminal 20 to the J terminal of the memory element MAM1 of the FF circuit configuration attached to the display block DB1 in the first row, and the timing signal TTS is input. At the falling edge, it is taken into the memory state and becomes logic “1” from the Q terminal.
The module selection signal MAS1 is output. This selection signal MAS1 is commonly applied to the module selection signal input terminals 19 of the 32 display modules included in the first row display block, opens the AND gate 15 for passing the scanning signal, and selects the output signal for each drive element. Enables the supply of scanning signals.

At this time, the character data signal CS is inputted to the terminal 22 from the external interface circuit, applied to the input terminal 12 of the character data shift register 11 included in the display module of the first column, and is separately input from the terminal 23 to the input terminal 13 for data acquisition. timing signal
The CTS sequentially loads the data into shift registers that are cascaded row by row. The character data signal string first stored in this way corresponds to information to be displayed on the first display line of the first row of display blocks.

On the other hand, the scanning signal SS is applied from the terminal 24 to the input terminal 16 of the scanning shift register 18, and this signal is fetched from the terminal 24 at the falling edge of the fetch timing signal STS. Thereafter, this scanning signal is sequentially transferred by a scanning timing signal STC (signal line not shown), and seven lines of Y conductors are sequentially scanned and addressed in synchronization with the addressing operation by the above-mentioned character data signal. In other words, the first pulse of the scan timing signal STC,
A scanning address signal SAS1 that controls the gate electrodes of the first line driving FETs of the first line display modules _DM1 to _DM32 to be in the ON state is applied through the AND gate circuit 15, and at the same time, the character data shift register 11 The FET selected according to the data address signal applied from the top line selectively drives the pixel electrode of the first line. Then, a new character data signal is sent to select and drive the second display line of the first display block DB1.
CS is controlled by the capture timing signal CTS and is input in series to the character data shift register 11, while the scanning signal in the scanning shift register is shifted by one bit by the scanning timing signal STC and outputs SAS2. The pixel electrodes of the second line are selectively driven by both address signals. Thereafter, the pixel electrodes of the seven lines in the first row are sequentially driven in the same manner, and the character information in the first row is displayed.

As above, the display block DB for the first line is created.
1 is enabled by the module selection signal MAS1, the character data signal CS, scanning signal SS, and signal capture timing signals CTS and STS are also commonly applied to the display blocks on the second and subsequent rows. However, in the display blocks below the second row, the output of the corresponding module selection memory element is in the logic "0" state, and this is the result of the AND gate circuit inserted at the output side of the scanning shift register of each display module. 15 is closed, passage of the scanning address signal to the gate electrode of the driving FET is prohibited, and driving of the solid line becomes impossible.

At the stage when the driving of the first row is completed, a timing signal TTS for fetching the module selection signal is generated, whereby the module selection signal MAS1 of the first row is transferred to the memory corresponding to the display block of the second row. The signal is taken into element MAM2, and a second row module selection signal MAS2 is generated from its Q terminal. The module selection signal MAS2 enables driving of the display blocks in the second row, and they are sequentially addressed starting from the first line, as in the case of the first row. In this way, module selection signals are sequentially transferred between memory elements corresponding to rows, and display blocks for each row are selectively driven in time series, thereby completing the display of one screen.

On the other hand, in the line sequential access method as described above, if there is a space line on the display screen, the speed of display can be increased by skipping the address operation at the space line. FIG. 4 is a timing chart for explaining such a skip access operation, and shows signal waveforms when scanning addresses in the third and fourth rows are skipped.

That is, in FIG. 4, the module selection signal
After the display blocks in the first and second rows are sequentially driven by MAS1 and MAS2, a signal capture timing signal TTS (the third (pulse) to suppress the subsequent scanning signal capture timing signal STS. Next, the module selection signal MAS3 is sent to the memory element of the next row.
After adding a timing signal TTS (fourth pulse) for transfer to the MAM 4, control is performed so that the timing signal for capturing the next scanning signal is also suppressed using this signal. In this way, by shortening the time interval of the module selection signal acquisition timing signal to the storage element and suppressing the scanning signal acquisition timing signal STS during that time, module selection signals MAS3 and MAS4 are generated, but the scanning shift is Since the output of the register is not valid, a skip operation will eventually be achieved.

In the above, sequential access and scanning in units of rows is achieved by arranging storage elements for module selection signals corresponding to rows and performing logical operations on the module selection signals from the storage elements and the output signals of the scanning shift registers. Although skip access is possible, various access methods can be adopted by appropriately setting the correspondence between display modules and display blocks and adding a memory element for each required block.

FIG. 5 shows an example of the configuration of a display device that achieves a character sequential access method, and for simplicity, nine display modules DM11 to DM33 are arranged in a matrix of 3 rows and 3 columns. Each display module has a configuration in which module selection memory elements MAM11 to MAM33 each having an FF circuit configuration are integrally integrated on a driving IC chip, and these are connected in series row by row on a subunit board (not shown). ing. Also, for each row, there is an FF for row block selection, similar to the embodiment shown in FIG.
Memory elements MAM1 to MAM3 are attached, and the Q terminal outputs of these memory elements are connected to the first J input terminal of the modular memory elements connected in series for each row, while the row selection memory associated with the next row It is also connected to the J input terminal of the element to enable signal transfer. Also, the row selection memory element MAM
The acquisition and transfer of signals to the module selection storage elements MAM1 to MAM3 are controlled by the timing signal TTS from the terminal 21.
The acquisition and transfer of signals to the MAM 33 are controlled by a timing signal MTS from a terminal 26. Although the signal lines on the data side and the scanning side are not shown to avoid complication, they are not particularly different from the embodiment shown in FIG. Therefore, the display device shown in FIG.
There is only one additional input terminal 26 for the timing signal MTS.

According to the configuration shown in FIG. 5, sequential access for each character (module) and high-speed skip access operation are possible, and the optimum operation mode can be set depending on the display content. Figure 6 is a timing chart for explaining such an operation, and the display module DM indicated by diagonal lines in Figure 5.
11, 12, 23, 31, and 32 are selectively driven, and the rest are skipped.

That is, after the module DM12 is selectively driven by the module selection signal MAS12, the timing signal MTS that sends the selection signal to the next module DM13 is thinned out, and the row selection signal MAS1 is sent to the next row using another timing signal TTS. Proceed,
Furthermore, the selection signal MAS2 on the second line is connected to the module DM2 using the high-speed controlled timing signal MTS.
The data is transferred to the memory element MAM23 of No. 3, and the module is selectively driven. In this case, although the input of character data is not particularly shown, the data for each character is input in common to all modules in accordance with the scanning order, and the logic on the scanning address side or data address side is selected by the module selection signal mentioned above. Only modules whose gate circuits are open will be effectively driven.

Although the main embodiments of this invention have been described above, those skilled in the art will be able to make various other modifications and extensions. For example, the configuration of the display module is
It is not limited to one character unit, but may include pixels for multiple characters. Furthermore, the selection of display modules can be performed in any other arbitrary block format other than row by row blocks, and of course a selection method for each module is also possible. Furthermore, the circuit configuration integrated on the semiconductor substrate of each module should be of a memory drive type in which a capacitor for signal storage is attached to each drive active element, in addition to the refresh type as illustrated. and various other changes are possible.

In short, the present invention provides a method for storing module selection signals using a plurality of display modules as a unit block in order to facilitate drive control when a large-scale display device is constructed by combining a plurality of small-scale display modules. A memory element is provided, and the output of the memory element selectively enables the driving of the module included in the corresponding block. Therefore, according to the present invention, although it is possible to easily adopt a large screen configuration, the connection wiring and control interface for the entire device are extremely simple, and moreover, it is possible to perform sequential access, high-speed skip access, etc. Since it has a function, it becomes possible to set the optimum operation mode according to the display contents.
Therefore, the present invention is extremely useful when applying a display device with an integrated drive circuit structure to a character display device for a computer terminal, etc.

[Brief explanation of drawings]

FIGS. 1a and 1b are cross-sectional views schematically showing the schematic structure of a display module used as a basic structural unit of a display device according to the present invention, and FIG. 2 is a schematic view showing an example of an equivalent circuit structure of an IC chip. is a schematic diagram showing one embodiment of the modular display device of the present invention. FIGS. 3 and 4 are timing charts for explaining the operation, respectively. FIG. 5 is a schematic diagram showing another example of the configuration of the modular display device of the present invention. The schematic diagram in FIG. 6 is a timing chart for explaining an example of the operation of the device shown in FIG. 6: IC chip, 7: Liquid crystal, 8: Transparent electrode,
9: Cover, 10: Silicon substrate, P11-P7
5: Pixel electrode, Q11-Q75: Drive FET,
11: Character data shift register, 12: Character data input terminal (CS), 13: Character data capture timing signal (CTS) input terminal, 14: Output terminal, 15: AND gate circuit, 16: Scanning signal,
17: Scanning signal capture timing signal (STS) input terminal, 18: Scanning shift register,
19: Module selection signal input terminal, MAM: Memory element for module selection, DM: Display block,
20: Module selection instruction signal (MSS) input terminal, IN: Inverter, 21: Timing signal (TTS) input terminal for signal acquisition.

Claims (1)

[Claims] 1. Comprising a display medium 7, a plurality of pixel electrodes 5, P _ij arranged regularly facing the display medium, and a selection driving active element Q _ij corresponding to each pixel electrode. A display screen is constructed by combining a plurality of display modules 1, DM ₁ to DM ₂₅₆ , and each display module has an input terminal for a module selection signal, an input terminal for an address signal, and an address for distributing the address signal to each active element. shift register 11,1
8, and memory elements MAM ₁ to MAM ₈ connected to the input terminal of the module selection signal for each display block DB ₁ to DB ₈ , each of which has a plurality of display modules as a unit.
The input/output terminals of the address shift registers of each display module in each display block are connected in series, and the input/output terminals of the memory elements for selecting each block are connected in series. A display device configured to enable sequential transfer of module selection signals between memory elements, and selectively enable driving of each display module in a sequentially selected display block. . 2. The display module is mainly composed of a semiconductor substrate 10 on which selective driving active elements are integrated;
2. The display device according to claim 1, wherein the storage element for the module selection signal is integrally formed on each semiconductor substrate. 3. Logic gate circuits SAS ₁ to SAS ₇ that open and close in response to a module selection signal from the storage element are provided between the output of the address shift register included in each of the display modules and the selection drive active element, 2. The display device according to claim 1, wherein driving of the display module is selectively enabled by the logic gate circuit. 4 A plurality of the display modules are arranged horizontally (vertically) to form a display block in units of rows, and
A multi-line display screen is constructed by arranging a plurality of display blocks vertically (horizontally) in parallel, and a memory element for module selection is provided corresponding to each display block in units of rows, so that the display modules of each row can be shared. The display device according to claim 1, characterized in that the display device is configured to select. 5 A plurality of display modules are arranged horizontally (vertically) to form a display block in units of rows, and
A multi-line display screen is constructed by arranging a plurality of display blocks vertically (horizontally) in parallel, and a memory element MAM _ij for module selection is provided corresponding to each display module, and each line is connected in series. , and a memory element MAM _i for row selection corresponding to each row unit display block.
are attached and connected in series so that module selection signals can be transferred sequentially between the memory elements for selecting each row and between the memory elements for selecting modules in each row. The display device according to item 1. 6. The storage element that stores the module selection signal has an input terminal for the selection signal, an input terminal for a timing signal that instructs the storage element to take in the selection signal, an input terminal for an inverted signal, and a signal output terminal. A display device according to any one of claims 1 to 5, characterized in that it has a configuration of a flip-flop circuit.