JPS6365642A - Formation of connection hole - Google Patents

Formation of connection hole

Info

Publication number
JPS6365642A
JPS6365642A JP20793986A JP20793986A JPS6365642A JP S6365642 A JPS6365642 A JP S6365642A JP 20793986 A JP20793986 A JP 20793986A JP 20793986 A JP20793986 A JP 20793986A JP S6365642 A JPS6365642 A JP S6365642A
Authority
JP
Japan
Prior art keywords
film
connection hole
etching
insulating film
connection holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20793986A
Other languages
Japanese (ja)
Inventor
Takashi Nishida
西田 高
Yoshio Honma
喜夫 本間
Eiji Sasaki
英二 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi ULSI Engineering Corp
Hitachi Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP20793986A priority Critical patent/JPS6365642A/en
Publication of JPS6365642A publication Critical patent/JPS6365642A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To open connection holes in a constant dimension with good accuracy without depending on the film thickness of an insulating film and also, to contrive to be able to form the connection holes comparatively favorably even to the covering property of the upper conductor by forming the connection holes with their lower parts having a vertical sidewall and their upper parts with a constant slant. CONSTITUTION:A polyimide high-molecular resin film 104 is spin coated as an interlayer insulating film on a substrate with first layer Al wirings 103 formed through an insulating film 102 on an Si wafer 101 having a step on its surface. A plasma CVD SiO film 105 is formed on the polymide high- molecular resin film 104 and the opening parts 106 and 106' of the plasma CVD SiO film 105 are formed at places where interlayer connection holes are provided by a reactive ion etching method wherein CF4 gas is used using a photoresist as a mask. Then, connection holes 107 and 107' having a vertical sidewall are formed in the polymide high-molecular resin film 104 by a reactive ion etching method using the SiO film 105 as a mask. After the SiO film 105 which is an etching mask is removed by CF4 plasma etching, the whole surface of a sample is etched.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電子回路装置等に用いる多層配線の層間接続
孔、あるいは半導体基板等へのコンタクト孔の形成方法
に係り、特に微細でも信頼性の高い接続孔を形成するに
好適な接続孔の形成方法に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for forming interlayer connection holes in multilayer wiring used in electronic circuit devices, etc., or contact holes in semiconductor substrates, etc. The present invention relates to a method for forming a connection hole suitable for forming a connection hole with a high .

〔従来の茂術〕[Traditional martial arts]

半導体装置等の高集積化が進展するにつれ、多層配線の
層間接続孔、コンタクト孔が微細になりつつある。微細
な孔を開孔するため罠は反応性イオンエツチングが多用
されている。しかし反応性イオンエッチにより側壁が垂
直な接続孔が形成されるとこの部分での上層の導体の被
覆性が問題となる。特に上層の導体が、スパッタあるい
は蒸着で形成される金属膜の場合には深刻な問題となり
得る。これに対する解決策については列えばプロン−デ
ィング オブ ファースト ブイ−エル・ニス−アイ 
マルチレベル インタコネクションコンファレンス 1
06頁(1984年) (Proc。
2. Description of the Related Art As semiconductor devices and the like become more highly integrated, interlayer connection holes and contact holes in multilayer interconnections are becoming finer. Reactive ion etching is often used in traps to create minute holes. However, when a contact hole with vertical sidewalls is formed by reactive ion etching, the coverage of the upper layer conductor at this portion becomes a problem. This can be a serious problem, especially when the upper layer conductor is a metal film formed by sputtering or vapor deposition. For a solution to this, see the Proclaiming of First V.L.N.I.
Multi-level interconnection conference 1
Page 06 (1984) (Proc.

1 st VLSI tVultilevel Int
erconnectionConference pp
106−14(1984)  )に記載されているよう
に、接続孔に傾斜付けをすることが検討されている。し
かし接続孔に傾斜付けをすると、@2図に示すように場
所によって接続孔を形成すべき絶縁膜の膜厚がり、、h
2と違っている場合には同一のマスクを用いても、該絶
縁膜の厚さによって接続孔の開孔寸法が各々dI+Gと
異なってしまうという不都合があり、実用的ではない。
1 st VLSI tVultilevel Int
erconnectionConference pp
106-14 (1984), it has been considered to make the connecting holes sloped. However, if the connection hole is sloped, the thickness of the insulating film where the connection hole should be formed increases depending on the location, as shown in Figure @2.
If they are different from 2, even if the same mask is used, the dimensions of the contact holes will differ from dI+G depending on the thickness of the insulating film, which is not practical.

またこの接続孔に傾斜付けをする方法は。Also, how do you make this connection hole slanted?

プロセスのバラツキに起因する膜厚変動の影響を受は易
く、この点からも余り望ましい方法ではない。
This method is easily affected by film thickness variations due to process variations, and from this point of view, it is not a very desirable method.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記の傾斜付けの方法では、実際の集積回路等の段差構
造、あるいは絶縁膜の平坦化に伴う絶縁膜の膜厚が場所
によシ異なることについて配慮がなされておらず、接続
孔の寸法を一定に制御することが1%に微細な接続孔に
おいて難しいという問題があった。
The above slanting method does not take into account the step structure of the actual integrated circuit, or the fact that the thickness of the insulating film varies depending on the location due to the flattening of the insulating film, and the dimensions of the contact hole are not considered. There is a problem in that it is difficult to maintain constant control for connection holes as small as 1%.

本発明の目的は、絶縁膜の膜厚に依存せずに。An object of the present invention is to achieve a method independent of the thickness of an insulating film.

精度良く一定の寸法に接続孔を開孔し、かつ、上層の導
体の被覆性も比較的良好に接続孔を形成することにある
The object of the present invention is to form a connection hole with high precision and a constant size, and to form the connection hole with relatively good coverage of the upper layer conductor.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、接続孔下部は垂直な側壁を有し。 For the above purpose, the lower part of the connecting hole has a vertical side wall.

上部では一定の傾斜付けのなされた接続孔を形成するこ
とにより達成される。
This is achieved by forming a connecting hole with a constant slope in the upper part.

上記形状は、接続孔の形成に際しまず等方的エツチング
を途中まで行ない、その後に異方性エツチングに切シ替
えて開孔を完了するという方法でも原理的には可能であ
る。しかし1等方性のドライエツチングではウェーハ内
の均一性の確保が難かしく、また1寸法依存性が出易い
という問題もある。等応性のウェットエツチングでは、
接続孔の加工寸法が小さくなったときにエツチングをし
た後の洗浄時に、洗浄ひらにより寸法の均一性が劣化し
てしまうという問題がある。このように等方的+異方的
エツチングで上記形状を達成することは実用上の現点か
らは、微細加工向きではなかった。
In principle, the above shape can also be achieved by a method in which when forming the connecting hole, first performs isotropic etching halfway, and then switches to anisotropic etching to complete the opening. However, with uniisotropic dry etching, it is difficult to ensure uniformity within the wafer, and there is also the problem that dependence on one dimension is likely to occur. In conformal wet etching,
When the processing dimensions of the connection hole are reduced, there is a problem in that the uniformity of the dimensions deteriorates due to the cleaning blade during cleaning after etching. From a practical point of view, achieving the above shape by isotropic and anisotropic etching is not suitable for microfabrication.

微細な接続孔においても上記形状を安定に達成するには
まず所定の寸法にi+ia壁が垂直な接続孔を形成した
後に1反応性でかつ異方性の強いエツチング(例えば反
応性イオンエツチング、反応性イオンビームエツチング
、バイアスを印加した反応性マイクロ彼プラズマエツチ
ング等)ヲ用いて。
In order to stably achieve the above-mentioned shape even in a fine connection hole, first, a connection hole with perpendicular i+ia walls is formed to a predetermined size, and then a highly anisotropic etching process (e.g. reactive ion etching, reactive etching) is performed. using reactive ion beam etching, biased reactive micro-plasma etching, etc.).

絶縁膜表面を全面エツチングすることにより、前記形状
の接続孔が開孔される。この形状の接続孔は、Arガス
を用いた。いわゆる逆スパツタによっても形成すること
がtq能である。しかしこの場合には実用的に効果のあ
る傾斜付けを行なうと。
By etching the entire surface of the insulating film, a contact hole having the shape described above is formed. Ar gas was used for the connection hole having this shape. It is also possible to form it by so-called reverse sputtering. However, in this case, slanting is a practical method.

接読孔の下の下部導体表面に接続孔上部で削られた絶縁
性物質が被着し、接続抵抗の上昇や、はなはだしい場合
には、不導通を引き起こすため、反応性イオンエツチン
グ等を用いることがより有効である。
The insulating material scraped at the top of the connection hole will adhere to the surface of the lower conductor below the reading hole, increasing connection resistance or, in extreme cases, causing non-conductivity, so use reactive ion etching, etc. is more effective.

〔実施例〕〔Example〕

以下本発明の実施例を図を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.

実施例1 表面に段差を有する3iウエーハ101上に絶縁膜10
2を介して第1層のAt配線103が形成された基板上
に1層間絶縁膜として約3.5μmのポリイミド系高分
子樹脂膜104を回転塗布した(41図a)。この後同
図すに示すようにポリイミド系高分子樹脂膜104上に
0.2μmのプラズマCVD5iO膜105を形成し、
ホトレジスト(図示せず)をマスクにCFA系ガスを用
いた反応性イオンエツチングによシ1層間接続孔を設置
する場所にプラズマCVD5iO膜105の開孔部10
6.106’を形成した。次いで同図Cに示すように該
SiO膜105をマスクに、酸素ガス圧力1mtorr
、高周波(1&56KHz )i[力密度0.2N/−
の条件で反応性イオンエツチングによりポリイミド系高
分子樹脂膜104Kfll壁が垂直な接続孔107,1
07’を形成した。更にCF”4 プラズマエツチング
を用いてエツチングマスクであるSiO膜105を除去
した後に酸素圧力1 mtorr  、高周波電力密度
0.5 ’N / crdの条件で試料表面を全面エツ
チングしポリイミド系高分子圏脂膜の厚さを約2μmと
した(同図d)。この処理によシ、接続孔底部での径は
変化することなく接続孔上部では約0.5μmの深さで
基板法線から計って約30’の傾斜をもつ九テーバ部分
が形成され、深い接続孔107’ではその下に約1μm
の垂直部分が残されており、浅い接続孔107”では垂
直部分の深さは0.2μmであった。この上にArのス
パッタクリーニング処理を行なった後に、約1μmの厚
さのAt薄膜をスパッタ形成し。
Example 1 An insulating film 10 is formed on a 3i wafer 101 having a step on its surface.
A polyimide polymer resin film 104 having a thickness of about 3.5 μm was spin-coated as an interlayer insulating film on the substrate on which the first layer of At wiring 103 was formed via 2 (FIG. 41a). After that, as shown in the figure, a 0.2 μm plasma CVD5iO film 105 is formed on the polyimide polymer resin film 104.
The openings 10 of the plasma CVD 5iO film 105 are etched by reactive ion etching using a CFA-based gas using a photoresist (not shown) as a mask.
6.106' was formed. Next, as shown in Figure C, using the SiO film 105 as a mask, an oxygen gas pressure of 1 mtorr was applied
, high frequency (1 & 56KHz) i [force density 0.2N/-
By reactive ion etching under the conditions of
07' was formed. Furthermore, after removing the SiO film 105 as an etching mask using CF''4 plasma etching, the entire surface of the sample was etched under the conditions of an oxygen pressure of 1 mtorr and a high frequency power density of 0.5'N/crd to form a polyimide polymer sphere. The thickness of the film was approximately 2 μm (Fig. d). Through this treatment, the diameter at the bottom of the connection hole did not change, and the diameter at the top of the connection hole was approximately 0.5 μm, measured from the normal to the substrate. Nine tapered portions with an inclination of about 30' are formed, and in the deep connection hole 107', a depth of about 1 μm is formed below.
The vertical portion of the shallow contact hole 107'' was 0.2 μm in depth. After performing Ar sputter cleaning treatment on this, an At thin film with a thickness of approximately 1 μm was deposited. Formed by sputtering.

通常のホトエツチング技術を用いて第2層のAt配l1
lljl(図示せず)を形成する。こうして作成した試
料の直径1゜0μm、栗さ1.5μm接続孔部での接触
抵抗は、200mΩ/ケと、当初から1−間膜4が2μ
mで傾斜付けを行なわなかった試料での値400mΩ/
ケと比較して約半分に減少しでいた。これは接続孔断面
部のSF、M観察から、この接続孔での第2層Atの被
覆係数(平坦部の第2層At配線の膜厚に対する接続孔
部で最も薄い部分のAt膜厚の比で定義)が、0.05
〜0.1から0.2に改善されていたことによることが
判った。
The second layer of At metal 11 is etched using conventional photoetching techniques.
lljl (not shown). The contact resistance at the connecting hole of the thus prepared sample with a diameter of 1°0 μm and a thickness of 1.5 μm was 200 mΩ/ke, and from the beginning the interlayer film 4 was 2 μm.
Value of 400 mΩ/
It was reduced by about half compared to the previous year. This can be determined from the SF and M observations of the cross-section of the connection hole.The coverage factor of the second layer At in this connection hole (the thickness of the At film at the thinnest part of the connection hole relative to the thickness of the second layer At wiring in the flat area) ratio) is 0.05
It was found that this was due to the improvement from ~0.1 to 0.2.

実施例2 実施例1と同様に垂直な接続孔を形成した後。Example 2 After forming vertical connection holes in the same manner as in Example 1.

試料人では、酸素ガスを用いたマイクロ波プラズマエツ
チング(μ波電力100W、バイアス電圧4sOV、&
素ガス圧力5 X 10−’ Torr )で。
The sample was subjected to microwave plasma etching using oxygen gas (μ wave power 100 W, bias voltage 4 sOV, &
At an elementary gas pressure of 5 x 10-' Torr).

試料Bでは酸素プラズマ灰化(酸素ガス圧力1゛for
r、高周波′電力200W>で、膜厚が3.5μmから
約2μmになる迄眉間のポリイミド系高分子を全面エツ
チングした。また試料CではArスパッタエツチング(
Arガス圧5 mtorr、 高周波電力500W)に
よシ膜厚が28μmから約2μmKなるまでエツチング
し、やはり実施例1と同様に第2層のAt配線を形成し
接続孔の接触抵抗を測定した。設計上1μmφ1.5μ
m深さの接続孔で、試料人では430mΩ/ケ、試料B
では80mΩ/ケ、試料Cでは一部で1Ω〜10Ω/ケ
の接触抵抗が得られたものの大部分は不導通(〉10Ω
/ケ)であった。また、試料A、 Cでは接続孔底部の
径は当初の値と変化しておらず。
For sample B, oxygen plasma ashing (oxygen gas pressure 1゛for
The polyimide polymer between the eyebrows was etched on the entire surface using a high frequency power of 200 W to a film thickness of 3.5 μm to approximately 2 μm. In addition, in sample C, Ar sputter etching (
Etching was performed using Ar gas pressure of 5 mtorr and high frequency power of 500 W) until the film thickness was from 28 μm to approximately 2 μmK, and a second layer of At wiring was formed in the same manner as in Example 1, and the contact resistance of the contact hole was measured. 1μmφ1.5μ due to design
m depth connection hole, 430 mΩ/piece for sample B, sample B
In sample C, a contact resistance of 80 mΩ/ke was obtained, and in sample C, a contact resistance of 1 Ω to 10 Ω/ke was obtained in some parts, but most of the contact resistance was non-conducting (>10 Ω/ke).
/ke). In addition, in samples A and C, the diameter of the bottom of the connecting hole did not change from the original value.

接触孔上部には約0.5μmの深さの傾斜部(傾斜角2
5°程度)が形成されているのに対して試料Bでは径が
約3.5μmKまで拡がっておシ、これが底接触抵抗の
原因であることが判った。試料Bの不導通の接続孔部分
では、第1層の配線表面にAtではない炭素を主成分と
する薄い被膜が形成されておシ、これが高抵抗の原因で
あると推定された。またこの被膜の主成分が炭素である
ことから、接触孔上部に傾斜がつく間に削られた高分子
+Ij脂の一部が接続孔底部に堆積し被膜となったもの
と考えられる。
At the top of the contact hole, there is an inclined part (angle of inclination 2) with a depth of approximately 0.5 μm.
5°), whereas in sample B, the diameter expanded to about 3.5 μmK, and it was found that this was the cause of the bottom contact resistance. In the non-conducting connection hole portion of sample B, a thin film mainly composed of carbon other than At was formed on the surface of the first layer wiring, and this was presumed to be the cause of the high resistance. Furthermore, since the main component of this coating is carbon, it is considered that a portion of the polymer + Ij resin that was scraped while the upper part of the contact hole was sloped was deposited at the bottom of the contact hole and formed a coating.

実施例3 実施例1と同様に段差を有する基板上にポリイミド系高
分子樹脂膜304を約3.5μmの1草さに形成した後
に、プラズマCVD窒化珪素膜305をマスクとして、
酸素反応性イオンエツチング(0,: 1mtorr、
 O,a w/i)でZ5.c+mの深さに側壁が垂直
な孔306を形成した(箒3図a)2続いて同図すに示
すように窒化珪素膜305を除去した後に、酸素反応性
イオンエツチング【02ガス圧!mtorr、高周波成
力密度0.5 W/ca )でポリイミド系高分子樹脂
膜を約1.5μmの厚さだけ、表面から全面エツチング
した。この方法でも底部での孔匝は約0.1μm初期の
値より拡がっているだけでろ如実飛例1と同様の形状の
接続孔を形成することが可能であった。また第2JΔ配
線を形成して測定した接続孔の接触抵抗は、180mΩ
/ケと良好な値であった。
Example 3 After forming a polyimide polymer resin film 304 in a thickness of approximately 3.5 μm on a substrate having steps as in Example 1, using a plasma CVD silicon nitride film 305 as a mask,
Oxygen reactive ion etching (0,: 1 mtorr,
O, a w/i) and Z5. A hole 306 with a vertical side wall was formed at a depth of c+m (Fig. 3a) 2. After removing the silicon nitride film 305 as shown in the figure, oxygen reactive ion etching (02 gas pressure! The entire surface of the polyimide polymer resin film was etched to a thickness of about 1.5 μm at a high frequency energy density of 0.5 W/ca). Even with this method, it was possible to form a connecting hole having the same shape as in Example 1, except that the hole size at the bottom was expanded by about 0.1 μm from the initial value. In addition, the contact resistance of the connection hole measured after forming the second JΔ wiring was 180 mΩ.
It was a good value of /.

以上実施例ではポリイミド系樹脂の全面エツチングには
酸素を用いた反応性かつ異方性エツチングを用いた例の
みを示したが、必ずしも反応ガスとしては純酸素に限ら
れる必然性はなく1例えばArに2%以上の酸素を混入
したガスを用いれば物理的衝撃効果が増すため、平坦部
のエツチング速度を大きく変化させることなく、接続孔
上部での傾斜づけが容易になる。このように酸素を成分
として含むガスであればこれを用いても本発明の目的が
充分に達成される。
In the above examples, only examples were shown in which reactive and anisotropic etching using oxygen was used for etching the entire surface of polyimide resin, but the reactive gas is not necessarily limited to pure oxygen; for example, Ar may be used. If a gas mixed with 2% or more oxygen is used, the physical impact effect will be increased, so that the upper part of the connection hole can be easily sloped without greatly changing the etching rate of the flat part. As described above, the object of the present invention can be sufficiently achieved even if a gas containing oxygen as a component is used.

また実施例ではkt系2層配線の層間て用いた場合につ
いてのみ記述したが、池の配線材料系あるいは2層を越
える多層配線の層間の場合、あるいは拡散4.ポリ8 
i配線への接触孔部への適用を妨げるものではない。
In addition, in the embodiment, only the case where it is used between two layers of KT-based wiring is described, but it is also applicable to the case where it is used between the layers of KT-based two-layer wiring, or between the layers of multi-layer wiring of more than two layers, or diffusion 4. poly8
This does not preclude application to the contact hole portion for i-wiring.

また層間絶縁膜としては高分子樹脂(ポリイミド)の場
曾テついてのみ述べたが、下地との選択性の充分に大き
な反応性、異方性エツチング手段を用いれば、他の5i
02系等の無機絶縁膜への適用かり能であることは明ら
かである。
In addition, although we have only mentioned the use of polymer resin (polyimide) as an interlayer insulating film, if we use an anisotropic etching method with sufficiently high reactivity with the underlying layer, other 5i materials can be used.
It is clear that the present invention can be applied to inorganic insulating films such as 02 series.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、場所により膜厚の異なる絶縁膜に接続
孔底部での径を一定に保ったまま接続孔を形成でき、し
かも上層4本の接続孔部での被覆性を向上し、安定な導
通を確保できるという効果がある。
According to the present invention, connection holes can be formed in an insulating film whose thickness varies depending on the location while keeping the diameter at the bottom of the connection hole constant, and the coverage of the four connection holes in the upper layer is improved and stable. This has the effect of ensuring good continuity.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を表わす工程概略図。 第2図は従来の傾斜付き接続孔の間雇点を示す図、第3
図は本発明の別の実施例全表わす概略図である。 101.301・・・Si基板、102,302・・・
絶縁膜、103,303・・・81層At配線、104
゜304・・・ポリイミド系樹脂膜、105・・・プラ
ズマcvDs io、a os−・・プラズマCVD5
 iN。 106.106’・・・エツチングマスク開孔部。 107.107’・・・垂直な接続孔、107“。 107”、307“、307”・・・上部に傾斜のつい
た接続孔、307,307’・・・途中まで形成した垂
直な接続孔、d・・・接続孔上部径* hl * hl
・・・ノー間膜厚* dl !  d2・・・接続孔底
部径。 ・−゛ 、 代理人 弁理士 小川時角  ゛ 第 / 図 第2図 グ2 第 3図
FIG. 1 is a process schematic diagram representing an embodiment of the present invention. Figure 2 is a diagram showing the connection point of a conventional inclined connection hole, Figure 3
The figure is a schematic representation of another embodiment of the invention. 101.301...Si substrate, 102,302...
Insulating film, 103, 303...81 layer At wiring, 104
゜304...Polyimide resin film, 105...Plasma CVDs io, a os-...Plasma CVD5
iN. 106.106'...Etching mask opening. 107.107'... Vertical connection hole, 107". 107", 307", 307"... Connection hole with a slope at the top, 307, 307'... Vertical connection hole formed halfway , d... Connection hole upper diameter * hl * hl
...No intermembrane thickness* dl! d2... Connection hole bottom diameter.・-゛、Representative Patent Attorney Tokaku Ogawa ゛Part / Figure 2 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】 1、絶縁膜に、その上層と下層との電気的接続を確保す
るための接続孔を形成するに際して、まず所定の寸法の
側壁がほぼ垂直な接続孔を形成した後に、反応性の異方
性エッチングを用いて該絶縁膜の全面エッチングを行な
うことにより、接続孔上部にテーパ付けをすることを特
徴とする接続孔の形成方法。 2、該絶縁膜が高分子樹脂で、かつ反応性の異方性エッ
チングが、酸素を成分として含むガスを用いた反応性エ
ッチングであることを特徴とする特許請求の範囲第1項
記載の接続孔の形成方法。 3、該高分子樹脂が芳香族ポリイミド系の高分子樹脂で
あることを特徴とする特許請求の範囲第2項記載の接続
孔の形成方法。
[Claims] 1. When forming a connection hole in an insulating film to ensure electrical connection between an upper layer and a lower layer thereof, first, after forming a connection hole with a predetermined dimension and a substantially vertical side wall, 1. A method for forming a connection hole, which comprises etching the entire surface of the insulating film using reactive anisotropic etching, thereby tapering an upper portion of the connection hole. 2. The connection according to claim 1, wherein the insulating film is made of a polymer resin, and the reactive anisotropic etching is reactive etching using a gas containing oxygen as a component. How to form pores. 3. The method for forming a connecting hole according to claim 2, wherein the polymer resin is an aromatic polyimide-based polymer resin.
JP20793986A 1986-09-05 1986-09-05 Formation of connection hole Pending JPS6365642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20793986A JPS6365642A (en) 1986-09-05 1986-09-05 Formation of connection hole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20793986A JPS6365642A (en) 1986-09-05 1986-09-05 Formation of connection hole

Publications (1)

Publication Number Publication Date
JPS6365642A true JPS6365642A (en) 1988-03-24

Family

ID=16548038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20793986A Pending JPS6365642A (en) 1986-09-05 1986-09-05 Formation of connection hole

Country Status (1)

Country Link
JP (1) JPS6365642A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02198691A (en) * 1989-01-30 1990-08-07 Yoshiharu Iino High-degree filter medium for potable water
JP2014078762A (en) * 1995-11-27 2014-05-01 Semiconductor Energy Lab Co Ltd Manufacturing method of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02198691A (en) * 1989-01-30 1990-08-07 Yoshiharu Iino High-degree filter medium for potable water
JP2014078762A (en) * 1995-11-27 2014-05-01 Semiconductor Energy Lab Co Ltd Manufacturing method of semiconductor device

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