JPS6363231A - Start pattern detector - Google Patents

Abstract

PURPOSE:To correctly detect a start pattern and to minimize a circuit size by passing through the output of a coincidence detection means when a judgement means judges that the output of a pattern reproduction means and reception data have the same pattern. CONSTITUTION:The output PN of the pattern reproduction means 11 and the reception data R DATA are inputted to an exclusive OR circuit 17. When in the judgement means 2 the output PN of the pattern reproduction means 11 coincides with the reception data R DATA to let the output of the exclusive OR circuit 17 to zero, the output of a filter 24 comes to a voltage at a low level. A hysteresis comparator 25 compares the output, and outputs CONT=0 as a switching control signal. An AND gate 13 is used as the coincidence detection circuit 13, and decides coincidence when all contents in a shift register stand at zero. A gate means 14 is constituted of an inverter 26 and an AND circuit 27, and passes through the output of the coincidence detection means 13 with CONT=0 given.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a start pattern detection device, particularly a start pattern detection device for detecting a start pattern when receiving a digital signal having a signal configuration in which an information signal follows. Regarding equipment.

[Conventional technology]

In order to process the received information signal, it is necessary to detect the starting point, or start cuturn, of the information signal. In this sense, the start pattern must be detected accurately without any errors. especially.

The more important the meaning of the information signal, the longer the start pattern is used to ensure accurate detection. However, the hardware configuration for this has become extremely large.

FIG. 3 shows a configuration diagram of an example of a conventional start pattern detection device, which is a circuit for detecting start/lean from received data (RDATA). To simplify the explanation, use this as a starting pattern.

'11001' with n = 5 bits is selected. In this example, a detection output can be obtained even if there is an error of r = l bits as the detection tolerance value, and the detection result is MAT
It is output from the CH terminal.

Next, the circuit of FIG. 3 will be explained in detail. 1 is n = 5
Receive data (RDATA) in the shift register of the stage
Store only 5 bits of . AND darts 2 to 6 each output MATCH=1 if one of them outputs 1 at the start/-e turn in the received data. circuit 8
, 9 are inverters when the start pattern is stored in register 1.

The inputs of AND darts 2 to 6 are all set to 1.

The circuit shown in Figure 3 starts with n =
This is true in the case of 5 bits, and it is easy to realize this level. However, in this circuit, even when RDATA is not a start pattern, the erroneous detection rate of determining it as a start pattern is extremely high. For example, when noise is input as RDATA even though no signal is being received (when receiving with an FM receiver, it becomes a noise state when not receiving),
What is the rate of detection of a 5-bit start pattern from completely random noise with a 1-bit tolerance?

P, = 1/25 + 5X1/25 = 3/16, 16
It happened 3 times in the bit. Therefore, even when no signal is being received, there is a very high probability that a start pattern included in noise will be detected and erroneous processing will be performed.

2. For example, if the start pattern is composed of n = 100 pits and the error tolerance is allowed up to r = 3 bits, then what is the probability of finding the start pattern in a noisy state?

The remaining days P = 1/2100 + 1ooC 1/2100 + 1ooC
2/2100+1ooC5/2100. . CZ21
00U 1.6
The 97-person AND gate is the equivalent of ND dates 2 to 6. There is no need for 161,700 oC3, resulting in an extremely large circuit scale.

[Problem that the invention seeks to solve]

That is, in the conventional device, if the length n of the start pattern is increased so as not to erroneously detect the start pattern from noise, the scale of one circuit becomes extremely large, which is difficult to realize.

[Means for solving problems]

The start pattern detection device of the present invention includes: a pattern reproducing means for reproducing a start pattern; an electronic switch for selecting one of the received data and the output of the pattern reproducing means and inputting the result to the pattern reproducing means;
determining means for determining whether the output of the pattern reproducing means and the received data are the same pattern, and when it is determined that they do not match, generating a control signal to select the received data at the electronic switch; and.

a coincidence detection means for performing a pattern match on the reproduction pattern of the pattern reproduction means; and gate means for passing the output of the coincidence detection means.

〔Example〕

Next, two aspects of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In this figure, a five-stage shift register 15 and an exclusive OR circuit 16 are used as the pattern reproduction means 11. The electronic switch 10 selects either the received data (RDATA) or the output (PN) of the pattern reproduction means 11. In this example, when the electronic switch 10 selects the output (PN) of the turn regeneration means, the turn regeneration means outputs a five-stage PN (Pseudo No1se) signal (period=271=31 bits).

The switching control signal (C0NT) of the electronic switch 10 is outputted from the determining means 12. If the output (PN) of the pattern reproducing means 11 and the received signal (RDATA) match, the determining means 12 outputs 0 as a switching control signal (CONT), and the electronic switch 10 switches the no-j turn reproducing means 11.
control to select the output (PN).

Next, the 9 determining means 12 will be explained. The output (PN) of the A' turn reproducing means 11 and the received data (RDATA) are input to the exclusive OR circuit 17. Exclusive OR circuit 17
outputs O if (PN) and (RDATA) match. The output of this circuit 17 is filtered through a low-pass filter 2 consisting of a resistor (R,) 18 and a capacitor (C1) 19.
4 to suppress the change. Here, one time constant R1C is selected to be sufficiently large compared to the time width of one bit.

The output of the low-pass filter 24 is further sent to the hysteresis comparator 25! Then, it is compared with the base voltage v0. The hysteresis comparator 25 has hysteresis characteristics by positively feeding back the result of comparison by the comparator 23 through a resistor (R5) 21. The resistor (R2) 20 is chosen to be slightly high so that the output of the comparator 23 does not adversely affect the filter 24. In other words, 2 determination means 12
If the output (PN) of the Noreen regeneration means 11 and the received data (RDATA) match and the output of the exclusive OR circuit 17 becomes 0, the output of the filter 24 also becomes a low voltage, which is connected to the hysteresis comparator. 25 and outputs C0NT=O as a switching control signal.

The operation of the electronic switch 10 t'' turn reproduction means 112 judgment means 12 can be explained as follows using the time chart of FIG. In this section, the received data (RDATA) is completely random and therefore does not necessarily match the output (PN) of the pattern reproduction means 11, and therefore the output x17 of the exclusive OR circuit 17 changes irregularly. A voltage higher than the comparison reference voltage is generated at the output ``24'' of the low-pass filter 24, which is compared by the hysteresis converter 25 and outputs C0NT=1 as a switching control signal. At this time, the electronic switch 10 selects the received data side according to the control from the determining means 12 and inputs it to the pattern reproducing means 11.

Next, the 5-stage PN pattern “00” is used as the start pattern.
0110111010100001001011001
1111" is received as an example, and its operation will be explained. When receiving this pattern, at least 5
When more than one bit is input to the Restorer 15.

Since there is a property that the output of the reproducing means and the received data match, x17=0. In that case, as shown in Fig. 2, the voltage at the output ``24'' of the low-pass filter 24 is low, and when it falls below a certain voltage v0 - ΔV (ΔV is the hysteresis width), the hysteresis comparator 25 responds. The switching control signal C0NT=O is output.The electronic switch 10 selects the output (PN) of the pattern reproduction means 11 and generates a signal independently of the received data (RDATA).Here, furthermore, (RDATA) If and (PN) have the same pattern, x17 remains 0, and therefore
Since the output of remains C0NT = 0, switch 1
There is no switching of 0.

If the received data happens to have an error at the moment when the electronic switch 10 is switched while receiving the start turn, the following will occur. At this time, since an incorrect pattern is input to the shift register 15, (RDAT
A) and (PN) cannot make the same Z turn, x, 7
becomes an irregular signal. So, a low pass filter! 2
The output of 4 becomes a high voltage again, and this is compared by the hysteresis controller 25 and output as a switching control signal to C0.
Outputs NT = 1.

Therefore, the received data (RD
ATA) is input. Therefore, the received data (R
DATA) and the output of the turn reproducing means 11 (PN)
The judgment means 12 checks whether the two match, and finally, even if the electronic switch 10 selects the output (PN) of the pattern reproduction means 11, this operation is automatically performed until the state in which (RDATA) and (PN) stably match continues. repeated.

Conversely, the electronic switch 10 outputs the output (P
Even if you select N), if (RDATA) and (PN) continue to match, the received data (RDATA)
is a star consisting of 5 stages of PN signals) 1? It is considered to be a turn. At this time, the received data (RDATA)
Even if an error occurs, the output of the pattern reproducing means 11 (PN
), no errors will occur, so the coincidence detection means 13 should perform coincidence detection on the contents of the pattern reproduction means (outputs Q, -Q5 of the register 15).

Detection without error is performed. In the example in Figure 1.

AND&”-) 13 is used as the coincidence detection means 13.

A match is determined when the contents of the shift register are all 1s. The number of inputs to the AND dart 13 may be equal to the number of stages of the shift register 15. The result of the match detection is outputted through the dart means 14. The dart means 14 is composed of an inverter 26 and an AND circuit 27.
When 0NT=O, the output of the coincidence detection means 13 is passed.

In the embodiment shown in FIG. 1, the starting pattern is a five-stage PN.
/? The case where the turn is 31 bits and 7 bits has been explained. Even if the start pattern is very long, for example, about 1000 bits, it can be implemented as a two-circuit scale by increasing the number of stages of the register 15 to 10 without changing the two circuits significantly.

Regarding the operation, the pattern reproducing means 11 reproduces the start pattern in synchronization with the received data, and this pattern reproducing means 11 performs coincidence detection, so it is not directly related to bit errors contained in the received data. Detection is performed at Therefore, detection errors are extremely rare.

In the explanation of FIG. 1, in order to make it easier to understand, the second judgment means 12 is explained using analog filter 24 and hysteresis controller 25.

A UPat) OWN counter is used in place of the filter 24.

It is also possible to use a digital comparator in place of the hysteresis comparator 25 for processing.

At this time, for example, the OWN counter (UPat) is ``17'' and the count is 7' r X1y '' 0
Make it count down when .

〔Effect of the invention〕

As explained above, the start pattern detection device of the present invention can detect a very long start pattern without error, and
The circuit scale for this can be made smaller compared to conventional devices.

In the following, Fig. 1 is a diagram showing a circuit configuration I of an embodiment according to the present invention, Fig. 2 is a time chart for explaining the operation of Fig. 1,
FIG. 3 is a diagram showing a circuit configuration of an example of a conventional start pattern detection device.

In the figure, 10...electronic switch, 11...pattern reproducing means, 15...shift register, 16...
Exclusive OR circuit, 12... Judgment means, 17... Exclusive OR circuit, 24... Low pass filter, 18...
resistance.

19... Capacitor, 25... Hysteresis controller or regulator, 20.21... Resistor, 22... Volume, 23... Comparator, 13... Coincidence detection means, 14.
...Cate means, 26... Inverter, 27...
It is an AND circuit.

゛ri! Figure 3 L.K.

Claims (1)

[Claims] 1. Pattern reproducing means for reproducing a start pattern;
an electronic switch that selects either the received data or the output of the pattern reproducing means and inputs the result to the pattern reproducing means; and whether or not the output of the pattern reproducing means and the received data are the same pattern. determining means for generating a control signal to select the received data in the electronic switch when it is determined that there is a mismatch, and a coincidence detecting means for pattern matching the reproduction pattern of the pattern reproduction means. and a gate means for passing the output of the coincidence detecting means when the determining means determines that the output of the pattern reproducing means and the received data are the same pattern. Device. 2. The start pattern detection device according to claim 1, wherein the start pattern is composed of a PN signal.