JPS6362431A - Packet switching network - Google Patents

Abstract

PURPOSE:To obtain a high throughput in a less hardware quantity by arranging plural number of multi-stage unit packets applying the write/read to/from a buffer memory. CONSTITUTION:A packet switch network consists of unit packet switches 101-106, incoming lines 11-19. outgoing lines 21-29, links 31-30 and control 1ines 41-49 applying data transfer by the hand-shake technology. Through the constitution above, the data reached to the incoming lines 11-13 is expanded in parallel in the word length of a buffer memory 111 and written in the buffer memory 111 at each word. Furthermore. stored information is stacked in the links 31-33 corresponding to the outgoing line to be sent as a queue. when the objective links 31-33 are idle, the packet data is transferred to the 2nd- stage unit packet switches 104-106.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a packet switch that switches packet information, and in particular, the present invention relates to a packet switch that switches packet information, and in particular, a large-capacity packet switch that can accommodate a large number of high-speed lines within the packet switch. Regarding switch networks.

[Prior Art] The basic operation of a packet switch is to first store packet information arriving from multiple input lines in a buffer memory, and then transfer the stored packet information to the output line corresponding to the destination route. It is to send out.

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It is generally expressed as the maximum amount of information that can be passed per unit time. This throughput is equal to the sum of the speeds of the main lines, the sum of the speeds of the outgoing lines, or, if these sums are different, the smaller of the two.

The throughput of this packet switch is mainly limited by the operating speed of the buffer memory.

As a method for realizing a packet switch having a throughput exceeding the capacity of a buffer memory, a method is known in which a plurality of unit packet switches are arranged in multiple stages as shown in Fig. 6.

In FIG. 6, 1 to 6 are unit packet switches each having three main lines and three outgoing lines,
It is arranged in two tiers.

The main lines 11 to 19 are connected to the input terminals of the unit packet switches l to 3 on the input side, while the output lines 2I to 2 are connected to the output terminals of the unit packet switches 4 to 6 on the output side.
9 is connected. In addition, unit packet switch 1~
The output terminals of the unit packet switches 3 and the input terminals of the unit packet switches 4 to 6 are connected by interstage links 31 to 39.

The unit packet switches 1 to 6 have buffer memories inside, and for example, the unit packet switch I has
Packet information arriving at large lines 11 to 13 of the packet switch network is temporarily stored in the buffer memory, and the packet is sent to links 31 to 33 according to the target outgoing lines 21 to 29 of the packet switch network.

Therefore, the buffer memory of the unit packet switch 1 is required to have an operating speed sufficient to write packet information at the sum of the speeds of the large lines 11 to 13 and to read the packet information at the sum of the speeds of the links 31 to 33.

[Problems to be Solved by the Invention] By the way, in the conventional packet switch network described above, since the speeds of the links 31 to 39 are constant, when traffic is concentrated on a specific link 31 to 39, packet information is There was a problem that the data could not be transmitted completely and the packet information was lost.

I will explain further. For example, main lines 11 to 19, outgoing line 2
It is assumed that the speeds of links 1 to 29 and links 31 to 39 are all the same value ■. In this case, the main line 11-1
If the destinations of the packet information No. 3 are concentrated on the outgoing lines 21 to 23 of the outgoing lines 2I to 29 for a while, all of these packet information will pass through the link 31. However, since the speed of the link 31 is ■, it is impossible to carry all the packet information from the large lines 11 to 13, and the packet information that cannot be stored in the internal buffer memory of the unit packet switch 1 is lost. I'll get lost.

To avoid such loss of packets within the communication path, the speeds of links 31-39 can be increased. Shi, rudder,
In this case, there is a disadvantage that the operating speed required of the buffer memory increases.

On the other hand, in order to reduce packet loss without increasing the speed of the links 3I to 39, it is possible to reduce the number of outgoing lines of the unit packet switches 4 to 6 on the outgoing side to one or two, or to A method of increasing the storage capacity of the buffer memory in 6 to 6 can be considered. however,
The method of reducing the number of outgoing lines reduces the throughput of the packet switch network, and the method of increasing the number of buffer memories has the drawbacks of increasing the number of hardware rings and increasing delay time.

Although the above description has been made assuming that the speeds of the large line and the outgoing line are the same, the same drawbacks occur even when lines of different speeds are accommodated.

This invention was made against this background.
Take full advantage of the buffer memory's storage capacity and operating speed,
The aim is to provide a packet switch network that can achieve high throughput with a small amount of hardware.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides that, in a communication path that performs packet switching such as a packet switch, a packet output terminal, and a buffer memory that can be commonly accessed from the input terminal and the output terminal and has a capacity capable of storing a plurality of packets, and a write request from the input terminal to the buffer memory and a buffer memory that can store a plurality of packets. A configuration in which a plurality of unit packet switches for writing to the buffer memory and reading from the buffer memory in response to a read request from the output terminal to the output terminal are arranged in multiple stages; connecting the stages of the unit packet switches; As long as the sum of the speeds of a link that performs asynchronous packet data transfer using handshaking and the link accommodated in a single unit packet switch is less than or equal to the operating speed of the buffer memory in that unit packet switch, The present invention is characterized by comprising a control circuit that controls data transfer by handshake while dynamically changing the capacity of the link.

[Function] According to the above configuration, each unit packet switch can transfer data within the range where the sum of the speeds of packet data transfer links accommodated in a single unit packet switch is less than or equal to the operating speed of the buffer memory in that unit packet switch. The speed of the link can be changed dynamically. As a result, among the links of a single unit packet switch, the speed of the link on which traffic is concentrated can be increased, while the speed of the other links can be decreased, allowing efficient data transfer.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

[First Embodiment] FIGS. 1 and 2 are block diagrams showing the configuration of a first embodiment of the present invention. In these figures, 101-106
is a unit packet switch, ■1 to 19 are lines to the packet switch network, 21 to 29 are output lines of the packet switch network, 31 to 39 are links, and 41 to 49 are links 31 to 3
This is a control line for performing the data transfer of No. 9 using the handshake technique.

FIG. 2 shows the internal configuration of the first stage unit packet switch 1O1 and the second stage unit packet switch 104 among the unit packet switches 101 to +06, and the other unit packet switches also have the same structure. It is the composition.

The first stage unit packet switch 101 includes a buffer memory 111 for storing input packet information;
It has output circuits 131 to 133 for sending data to a plurality of links 31 to 33, and a selection control circuit 121. Here, each of the output circuits 131 to 133 outputs packet data to be read to the output circuit from the buffer memory 1.
11, and when the output circuit has finished sending the packet data read from the buffer memory III to the links 31 to 33, the selection control circuit 121 is instructed to read the packet data. Send a request. Selection control circuit! 21 is each output circuit 131 to 133
It performs an operation of arbitrating (ordering and distributing) read requests from , sequentially selects requests, and sequentially reads data corresponding to the selected requests to each of the output circuits 131 to 133.

The second-stage unit packet switch 104 includes a buffer memory 112, a selection control circuit +22, and input circuits 141 to 22.
143. Input circuits 141-+43 send stale requests to selection control circuit 122 when packet data arrives from links 3.1 and 34.37. The selection control circuit 122 arbitrates the write requests from each input circuit 14+-143, sequentially selects the input circuits 141 to 143, and selects the received data? The data is written to the buffer memory 112 in a time-division manner.

In such a configuration, the packet data arriving at the entrances III to 13 are expanded in parallel to the word length of the buffer memory 111, and written into the buffer memory +ti every l words. For example, if the length of one packet is 2048 bits and the word length is 32 bits, the data for one packet is divided into 64 times and stored in the buffer memory 111.
It will become outdated.

When packet data is written into the buffer memory 111, the accumulated information is loaded as a queue on the links 31 to 33 corresponding to the outgoing line to be sent, according to the routing information inside the header. Then, when the target links 31 to 33 become vacant, the packet data is read out again in word length sections in the buffer memory 21 and transferred to the second-stage unit packet switches 104 to 106. Note that the control of the queue is performed by a control section (not shown) within the unit packet switch 101.

Writing to the buffer memory 111 and reading from the buffer memory 111 described above are performed by each large line 11.
19 and links 31 to 39 in a time-sharing manner. In this case, since the large lines 11-19 have a constant speed, writing from the large lines 11-19 is performed periodically. However, it is possible to provide some degree of freedom in writing from the large lines 11-19 to the buffer memory 111 by providing a FIFO for small-capacity packet data in correspondence with the large lines 11-19. .

On the other hand, since data transfer on the links 31 to 39 is performed by an asynchronous handshake method, reading from the buffer memory 111 to the links 31 to 39 is asynchronous.

In this way, the first stage unit packet switch +01
−103 to second stage unit packet switch 104~;
06, the packet information is temporarily stored in the buffer memory 112 of the second-stage unit packet switches 104 to 106, and then sent to the outgoing lines 21 to 29 at a constant speed.

The speed of data transfer by handshake is determined by the read cycle time of the transmitted data from the buffer memory 111,
It is determined by the write cycle time of the received data to the buffer memory 111 and the operating time of the circuit that transfers the packet data and control information. The transfer circuit is generally composed of simple circuits such as flip-flops and gates, and operates at a speed sufficiently faster than the operating speed of the buffer memory 111. Therefore, the data transfer speed is mainly determined by the operating speed of the buffer memory 111.

For example, if the packet data sent from the unit packet switch 101 to the unit packet switch 104 is not stored in the buffer memory 111 of the unit packet switch 101, or if the buffer memory 112 of the unit packet switch 104 is full and new packet data is If the data cannot be written, the operating speed of the buffer memory 111 or 112 is zero, so the data transfer speed of the link 31 is zero.

On the other hand, when there is no data to be sent from the unit packet switch 101 to the unit packet switches 105 and 106, and furthermore, there is no data to be sent from the unit packet switch 102, 103 to the unit packet switch 104, the unit packet switch 101 sends the link 32. There is no read request from the output circuits 132 and 133 corresponding to link 3, and in the unit packet switch 104, link 3
Since there are no write requests from the input circuits 142 and 143 corresponding to 4.37, compared to the case where reading to multiple links or writing from multiple links is performed, it is easier to write from the unit packet switch 101 to the unit packet switch 104. Packet data transfer can be performed at high speed. This is because, in this case, the output circuit 131 is
1 and because the input circuit 141 can occupy the buffer memory 112, the cycle time for reading packet data and the cycle time for writing packet data can be shortened.

In this way, the output circuits 131-133, the input circuit 141
-143, the one with the transfer request has buffer memory 1.
By granting access rights to 11 and 112, data can be transferred asynchronously and the transfer speed can be increased.

Next, inside the unit packet switches 101 to 106, in order to increase the equivalent operating speed of the buffer memories 111 and 112, a method is used in which packet data is expanded, written, and read in parallel. For example, the buffer memory 11 of the unit packet switch +01
The packet data read out in parallel from 1 is converted into serial data by output circuits 131 to 133 and supplied to links 31 to 33. Also, packet data that arrives in series at the input circuit 141 of the unit packet switch 104 is converted into parallel data by the input circuit 141 and written into the buffer memory 112.

FIGS. 3 and 4 show circuit configurations for performing this conversion.

FIG. 3 shows a parallel-to-serial conversion circuit that converts 3-bit parallel data read from the buffer memory 111 into serial data, and this constitutes a part of the output circuit 131.

The operation of this parallel-to-serial conversion circuit is as follows.

(2) When parallel data is supplied, this parallel data is latched into data buffers 205-207 under the control of handshake control circuits 215-217.

(2) When the parallel data is latched, the handshake control circuits 215 and 216 switch the switching circuits 223 to 226 to the solid line side in the figure. As a result, the data buffer 205
and data buffer 208, and handshake control circuit 215 and handshake control circuit 218 are connected, respectively.

■The handshake control circuit 218 uses the control information from the handshake control circuit 215 to
data is transferred to the data buffer 208.

(2) Send the data in the data buffer 208 to the link 31.

■The handshake control circuit 215 is connected to the switching circuit 223.
225 to the dashed line side. Thereby, data buffer 206 and data buffer 208, and handshake control circuit 216 and handshake control circuit 218 are connected.

■The handshake control circuit 218 uses the control information from the handshake control circuit 216 to
data is transferred to the data buffer 208.

(2) Send the data in the data buffer 208 to the link 31.

■The handshake control circuit 216 is connected to the switching circuit 224.
226 to the dashed line side. As a result, the data buffer 207 is connected to the data buffer 208, and the handshake control circuit 217 is connected to the handshake control circuit 21.
Connected to 8.

■The handshake control circuit 218 uses the control information from the handshake control circuit 217 to control the data buffer 207.
data is transferred to the data buffer 208. Furthermore, the handshake control circuit 2+7 notifies the selection control circuit 121 that it is ready to accept the next parallel data.

[Stocks] Sends the data in the data buffer 208 to the link 31.

By repeating each of the above operations, parallel data is converted to serial data.

FIG. 4 shows a serial deconversion circuit sent from link 31, which forms part of input circuit 141 of FIG.

The operation of this serial-to-parallel conversion circuit is as follows.

■When the first bit of data arrives, this data becomes
It is latched into data buffer 201 under the control of handshake control circuit 211 .

■The handshake control circuit 211 informs the switching circuit 221 that the data has been latched in the data buffer 201.
The information is transmitted to the handshake control circuit 212 via the .

(2) The handshake control circuit 212 transfers the data in the data buffer 201 to the data buffer 202 by exchanging control information with the handshake control circuit 211.

(2) The handshake control circuit 212 switches the switching circuit 221 to the broken line side. As a result, the handshake control circuit 211 and the handshake control circuit 213 are connected.

The first data is transferred to the data buffer 203 by the control information transmitted to the handshake control circuit 213 via the path of handshake control circuit 211 - switching circuit 221 - switching circuit 222 → second handshake control circuit 213. be done.

(2) The handshake control circuit 213 switches the switching circuit 222 to the broken line side. As a result, handshake control circuit 211 and handshake control circuit 2+4 are connected.

(2) The third bit of data latched in the data buffer 201 is transferred to the data buffer 204 by the handshake control circuit 214.

(2) Thereafter, the handshake control circuit 214 notifies the selection control circuit 122 that it is ready to send parallel data.

(2) When the parallel data is transferred, the handshake control circuits 212 to 214 are reset, and the same operation is repeated to execute serial/parallel conversion.

In this first embodiment, the speed of the large line 11-13 is V
The sum of the information writing and reading speeds of 1 buffer memory I11 and 112 is 3■, respectively, and large lines 11 to 1
Suppose that the destinations of the packet information No. 3 are concentrated on the outgoing lines 21 to 23 for a while.

At this time, if the data stored in the buffer memory Ill of the unit packet switch IO1 is only packet information to be sent to the unit packet switch +04 via the link 31, it is necessary to send the data to the links 32 and 33. Therefore, the output circuit 131 is connected to the buffer memory 2.
1, and only the information to be sent to the link 31 needs to be read. Therefore, information can be transferred to the unit packet switch network 4 at a maximum speed of 3V. As a result, the problems of the prior art, such as loss of packet information within the channel due to the link speed V, are solved.

On the other hand, from the unit packet switch 101, the link 31,
32. Via 33, unit packet information -chi 104
, 105, 106 is stored in the buffer memory itt, each link 3
1, 32, and 33 can be transferred at an equal rate, that is, equivalently at a rate V. In other words,
Transfer is possible in exactly the same way as when connected with a constant speed V link.

The same applies to writing to buffer memory +12. That is, when data arrives only from a single link, it is written to the buffer memory 112 at high speed, and when data arrives from a plurality of links, it is written at low speed.

In this way, when data is transferred between stages of a unit packet switch using the handshake technique, the sum of the speeds of packet data transfer links accommodated in a single unit packet switch is the buffer memory of that unit packet switch network. The capacity of the links between the stages changes dynamically within the range below the operating speed of , increasing the throughput of the packet switch network and making it possible to flexibly respond to fluctuations in packet information traffic.

Note that the above explanation was about the configuration of a two-stage unit packet switch that accommodates three lines and links, but even if the number of lines and links accommodated in a unit packet switch changes, the number of stages also changes. - similar effects can be expected. In addition, the conversion circuits shown in FIGS. 3 and 4 convert serial data and three times the serial data.

Although this is a conversion circuit between parallel data of the number of bits, a similar conversion circuit can be easily realized no matter how many times the ratio of the numbers of bits and digits is.

[Second Embodiment] FIG. 5 is a block diagram showing the configuration of a second embodiment of the present invention. This shows an example of the configuration of a three-stage packet switch network.

In the figure, 331-334 are large lines, 301-308
is the first stage unit packet switch, and 311 to 318 are the 2nd stage unit packet switches.
Unit packet switches 321 to 324 in the third stage are unit packet switches in the third stage. Also, 341-356
are the inter-stage links between the first and second stages, 357 to 36.1 are the inter-stage links between the second and third stages, and these inter-stage links 34l to 364 are all based on handshake. It is used to transfer data.

Incoming lines 301 to 308 are each accommodated in two first-stage unit packet switches. For example, incoming line 3
31 is accommodated in a unit packet switch 301 and a unit packet switch 303. And incoming line 3
Only data sent from 31 to outgoing lines 371 and 372 is stored in the buffer memory of unit packet switch 301, and data sent to outgoing lines 373 and 374 is written to the buffer memory of unit packet switch 303.

Data transfer from the first stage unit packet switches 301 to 308 to the second stage unit packet switches 311 to 3I8, and the second stage unit packet switches 311 to 31
Data transfer from 8 to the third-stage unit packet switches 321 to 324 is performed by the handshake method, as in the first embodiment.
~324 buffer memory to each output line 371~374
will be sent to.

Also in this configuration, for example, links 341, 342, .
Links 341, 343 accommodated in the second-stage unit packet switch 311, links 357, 361, etc. accommodated in the third-stage unit packet switch 321, etc. 2 each
Within the range where the sum of the speeds of the links is less than or equal to the operating speed of the buffer memory in the unit packet switch, the speed of each link changes dynamically according to the traffic imbalance, and the capacity of the link between the unit packet switch stages Packet loss within the packet switch network due to shortage will not occur.

In the configuration shown in FIG. 5, the number of incoming lines accommodated in the first stage unit packet switches 301 to 308 and the number of outgoing lines accommodated in the third stage unit packet switches 321 to 324 are respectively Since there is only one line, it can accommodate high-speed lines.

[Effects of the Invention] As explained above, in the present invention, the link between the unit packet switch stages is a link based on handshake, and the speed of the interstage link is dynamically changed according to the traffic imbalance. The following effects can be achieved.

■Since the speed of the buffer memory, which is the main part of the packet switch, can be utilized to the maximum, the throughput of the packet switch network increases.

■Since the information transfer rate at the link section can flexibly respond to changes in traffic, a packet switch network with low packet loss and average delay time can be realized with a small amount of hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the main parts inside the unit packet switch of the first embodiment, and FIG. 3 is the output circuit 131.
FIG. 4 is a block diagram showing the configuration of the parallel-serial conversion circuit provided inside the input circuit +41. FIG. 5 is a block diagram showing the configuration of the serial-parallel conversion circuit provided in the input circuit +41.
FIG. 6 is a block diagram showing the structure of a conventional two-stage packet switch network. 31-39.341-364...Link, 10
1-106.301~308.311~318.321
~324...Unit packet switch, ill,
112...Buffer memory, 121.122.
...Selection control circuit, 131-133...
Output circuit, 141-143...Input circuit. First cause Figure 2 Figure 5

Claims (1)

[Claims] In a communication path that performs packet switching such as a packet switch, one or more packet input terminals, one or more packet output terminals, and common access from the input terminal and output terminal. and a buffer memory with a capacity capable of storing a plurality of packets, and a write request to the buffer memory from the input terminal and a read request from the buffer memory to the output terminal cause writing to the buffer memory. , and a configuration in which a plurality of unit packet switches that read data from the buffer memory are arranged in multiple stages; a link that connects the stages of the unit packet switches and performs asynchronous packet data transfer using handshake; Data transfer by handshaking is performed while dynamically changing the capacity of each link within a range in which the sum of the speeds of the links accommodated in the unit packet switch is less than or equal to the operating speed of the buffer memory in the unit packet switch. A packet switch network comprising: a control circuit for controlling the network;